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XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

Rev. 1.0.1

October 2012

GENERAL DESCRIPTION

APPLICATIONS

 Servers

 Base Stations

 Switches/Routers

 Broadcast Equipment

 Industrial Control Systems

 Automatic Test Equipment

 Video Surveillance Systems

The XRP7724 is a quad channel Digital Pulse

Width Modulated (DPWM) Step down (buck)

controller. A wide 4.75V to 5.5V and 5.5V to

25V input voltage dual range allows for single

supply operation from standard power rails.

With integrated FET gate drivers, two LDOs for

standby power and a 105kHz to 1.23MHz

independent channel to channel programmable

constant operating frequency, the XRP7724

reduces overall component count and solution

footprint and optimizes conversion efficiencies.

A selectable digital Pulse Frequency Mode

(DPFM) capable of better than 80% efficiency

at light current load and low operating current

allow for portable and Energy Star compliant

applications. Each XRP7724 output channel is

individually programmable as low as 0.6V with

FEATURES

 Quad Channel Step-down Controller

 Digital PWM 105kHz-1.23MHz Operations

 Individual Channel Frequency Selection

 Patented digital PFM with Ultrasonic mode

 Patented Over Sampling Feedback

 Integrated MOSFET Drivers

 Programmable 5 coefficient PID control

 4.75V to 25V Input Voltage

a

resolution as fine as 2.5mV, and

configurable for precise soft start and soft stop

sequencing, including delay and ramp control.

 4.75V-5.5 and 5.5V-25V Input Ranges

 0.6V to 5.5V Output voltage

The XRP7724 operations are fully controlled

via a SMBus-compliant I²C interface allowing

 SMBus Compliant - I²C Interface

 Full Power Monitoring and Reporting

 3 x 15V Capable PSIO + 2 x GPIOs

 Full Start/Stop Sequencing Support

for

advanced

local

and/or

remote

reconfiguration, full performance monitoring

and reporting as well as fault handling.

Built-in independent output over voltage, over

temperature, over-current and under voltage

lockout protections insure safe operation

under abnormal operating conditions.

 Built-in Thermal, Over-Current, UVLO

and Output Over-Voltage Protections

 On Board 5V and 3.3V Standby LDOs

 On Board Non-volatile Memory

 Supported by PowerArchitect™

The XRP7724 is offered in a RoHS compliant,

“green”/halogen free 44-pin TQFN package.

TYPICAL APPLICATION DIAGRAM

Fig. 1: XRP7724 Application Diagram

Exar Corporation

48720 Kato Road, Fremont CA 94538, USA

www.exar.com

Tel. +1 510 668-7000 – Fax. +1 510 668-7001

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

ABSOLUTE MAXIMUM RATINGS

OPERATING RATINGS

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

Input Voltage Range V_CC...............................5.5V to 25V

Input Voltage Range V_CC= LDO5 ................4.75V to 5.5V

VOUT1, 2, 3, 4 ......................................................5.5V

Junction Temperature Range ....................-40°C to 125°C

JEDEC Thermal Resistance θ_JA..........................30.2°C/W

VCCD, LDO5, LDO3_3, GLx, VOUTx .............-0.3V to 7.0V

ENABLE, 5V_EXT .......................................-0.3V to 7.0V

GPIO0/1, SCL, SDA................................................ 6.0V

PSIOs Inputs, BFB .................................................. 18V

DVDD, AVDD ........................................................ 2.0V

VCC...................................................................... 28V

LX# .............................................................-1V to 28V

BSTx, GHx....................................................VLXx + 6V

Storage Temperature..............................-65°C to 150°C

Power Dissipation ................................ Internally Limited

Lead Temperature (Soldering, 10 sec)....................300°C

ESD Rating (HBM - Human Body Model).................... 2kV

ELECTRICAL SPECIFICATIONS

Specifications with standard type are for an Operating Junction Temperature of T_J= 25°C only; limits applying over the full

Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise indicated, V_CC= 5.5V to 25V, 5V EXT open. Note that in cases where there is a

discrepancy in values shown in this section and other sections of the datasheet, the values in the Electrical Specification

section shall be deemed correct and supersede the other values.

QUIESCENT CURRENT

Parameter

Min.

Typ.

Max.

Units

Conditions

EN = 0V, VCC = 12V

µA

VCC Supply Current in SHUTDOWN

ENABLE Turn On Threshold

10

20

V

VCC = 12V Enable Rising

0.95

10

0.82

-10

uA

EN=5V

EN=0V

ENABLE Pin Leakage Current

LDO3_3 disabled, all channels disabled

GPIOs programmed as inputs

VCC=12V,EN = 5V

µA

VCC Supply Current in STANDBY

440

3.1

600

2 channels on set at 5V, VOUT forced to

5.1V, no load, non-switching, Ultra-sonic

off, VCC=12 V, No I²C activity.

mA

VCC Supply Current 2ch PFM

4 channels on set at 5V, VOUT forced to

5.1V, no load, non-switching, Ultra-sonic

off, VCC=12V, No I²C activity.

mA

VCC Supply Current 4ch PFM

VCC Supply Current ON

4.0

18

All channels enabled, Fsw=600kHz, gate

drivers unloaded, No I²C activity.

2/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

INPUT VOLTAGE RANGE AND UNDERVOLTAGE LOCKOUT

Parameter

Min.

Typ.

Max.

Units

Conditions

•

25

V

5.5

VCC Range

5.5

With VCC connected to LDO5

4.75

VOLTAGE FEEDBACK ACCURACY AND OUTPUT VOLTAGE SET POINT RESOLUTION

Parameter

Min.

Typ.

Max.

Units

Conditions

5

20

7.5

22.5

15

45

20

50

30

90

40

100

5.5

mV

V

-5

-20

-7.5

-22.5

-15

-45

-20

-50

-30

-90

-40

-100

0.6

VOUT Regulation Accuracy

Low Output Range

0.6V to 1.6V

0.6 ≤ VOUT ≤ 1.6V

•

0.6 ≤ VOUT ≤ 1.6V

VCC=LDO5

PWM Operation

VOUT Regulation Accuracy

Mid Output Range

0.6V to 3.2V

0.6 ≤ VOUT ≤ 3.2V

VCC=LDO5

PWM Operation

VOUT Regulation Accuracy

High Output Range

0.6V to 5.5V

0.6 ≤ VOUT ≤ 5.5V

0.6 ≤ VOUT ≤ 4.2V

VCC=LDO5

PWM Operation

•

VOUT Regulation Range

Without external divider network

12.5

25

50

Low Range

Mid Range

High Range

VOUT Native Set Point

Resolution

mV

kΩ

2.5

5

10

Low Range

Mid Range

High Range

VOUT Fine Set Point Resolution¹

VOUT Input Resistance

120

90

75

Low Range

Mid Range

High Range

Low Range

Mid Range

High Range

10

1

0.67

VOUT Input Resistance in PFM

Operation

MΩ

mV

157.5

315

630

Low Range

Mid Range

High Range

-155

-310

-620

Power Good and OVP Set Point

Range (from set point)

5

10

20

Low Range

Mid Range

High Range

-5

-10

-20

Power Good and OVP Set Point

Accuracy

BFB Set Point Range

BFB Set Point Resolution

BFB Accuracy

16

V

9

1

0.5

-0.5

Note 1: Fine Set Point Resolution not available in PFM

3/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

CURRENT AND AUX ADC (MONITORING ADCS)

Parameter

Min.

Typ.

Max.

Units

Conditions

±1.25

3.75

10

5

mV

LSB

-3.75

-10

-5

Low Range (≤120mV) Note 2

-60mV applied

•

Current Sense Accuracy

±2.5

High Range (≤280mV)

-150mV

+12.5

-12.5

Current Sense ADC INL

DNL

+/-0.4

0.27

Current Limit Set Point

Resolution and Current

Sense ADC Resolution

1.25

mV

Low Range (≤120mV)

2.5

High Range (≤280mV)

20

40

Low Range (≤120mV)

-120

-280

Current Sense ADC Range

High Range (≤280mV)

15

30

60

Low Range

Mid Range

High Range

VOUT ADC Resolution

mV

VOUT ADC Accuracy

VCC ADC Range

1

LSB

V

-1

25

Note 3

4.6

UVLO WARN SET

4.72

4.55

V

UVLO WARN set point 4.6V, VCC=LDO5

UVLO FAULT set point 4.4V, VCC=LDO5

4.4

4.2

UVLO WARN CLEAR

UVLO FAULT SET (Note 4)

VCC ADC Resolution

VCC ADC Accuracy

V

200

5

mV

LSB

°C

1

Vin <= 20V

-1

Die Temp ADC Resolution

Die Temp ADC Range

156

Output value is in Kelvin

-44

Note 2: Final test limits are ±2.5mV or ±2 LSB

Note 3: Although Range of VCC ADC is technically 0V to 25V, below 4.55 the LDO5 hardware UVLO may have tripped.

Note 4: This test ensures an UVLO FAULT flag will be given before the LDO5 hardware UVLO trips.

LINEAR REGULATORS

Parameter

Min.

Typ.

Max.

Units

Conditions

5.5V ≤ VCC ≤ 25V

0mA < I_LDO5OUT< 130mA, LDO3_3 Off

LDO5 Output Voltage

5.0

5.15

V

4.85

•

LDO5 Current Limit

155

180

mA

V

LDO5 Fault Set

VCC Rising

135

LDO5 UVLO

4.74

LDO5 PGOOD Hysteresis

LDO5 Bypass Switch Resistance

375

1.1

mV

Ω

VCC Falling

1.5

2.5

Bypass Switch Activation

Threshold

•

%

V5EXT Rising, % of threshold setting

V5EXT Falling

2.5

Bypass Switch Activation

Hysteresis

150

3.3

mV

4.6V ≤ LDO5 ≤ 5.5V

0mA < I_{LDO3_3OUT}< 50mA

•

LDO3_3 Output Voltage

LDO3_3 Current Limit

3.45

85

V

3.15

53

mA

LDO3_3 Fault Set

ENABLE transition from logic low to

high. Once LDO5 in regulation above

limits apply.

Maximum total LDO loading

during ENABLE start-up

30

mA

4/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

PWM GENERATORS AND OSCILLATOR

Parameter

Min.

Typ.

Max.

Units

Conditions

Steps defined in table

Switching Frequency (fsw)

Range

1230

5

kHz

%

105

–5

fsw Accuracy

CLOCK IN

Synchronization Frequency

When synchronizing to an external clock

(Range 1)

25.7

12.8

31

MHz

20

CLOCK IN

Synchronization Frequency

When synchronizing to an external clock

(Range 2)

15.5

MHz

10

GPIOS⁵

Parameter

Min.

Typ.

Max.

Units

Conditions

Input Pin Low Level

0.8

V

Input Pin High Level

Input Pin Leakage Current

Output Pin Low Level

Output Pin High Level

2.0

1

µA

V

0.4

I_SINK= 1mA

V

I_SOURCE= 1mA

I_SOURCE= 0mA

2.4

3.3

3.6

10

V

Output Pin High-Z leakage

Current (GPIO pins only)

µA

Maximum Sink Current

I/O Frequency

Open Drain Mode

1

mA

30

MHz

Note 5: 3.3V CMOS logic compatible, 5V tolerant.

PSIOS⁶

Parameter

Min.

Typ.

Max.

Units

Conditions

Input Pin Low Level

0.8

V

Input Pin High Level

Input Pin Leakage Current

Output Pin Low Level

2.0

1

µA

V

0.4

I_SINK= 3mA

Open Drain. External pull-up resistor to

user supply

Output Pin High Level

15

V

Output Pin High-Z leakage

Current (PSIO pins only)

10

5

µA

I/O Frequency

MHz

Note 6: 3.3V/5.0V CMOS logic compatible, maximum rating of 15.0V

5/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

SMBUS (I2C) INTERFACE

Parameter

Min.

Typ.

Max.

Units

Conditions

VIO = 3.3 V ±10%

Input Pin Low Level, V_IL

Input Pin High Level, V_IH

0.3 VIO

V

VIO = 3.3 V±10%

0.7 VIO

Hysteresis of Schmitt Trigger

inputs, V_hys

V

VIO = 3.3 V±10%

0.05 VIO

Output Pin Low Level (open

drain or collector), V_OL

0.4

10

V

I_SINK= 3mA

Input leakage current

µA

ns

pF

Input is between 0.1 VIO and 0.9 VIO

-10

Output fall time from V_IHminto

V_ILmax

With a bus capacitance (Cb)from 10 pF to

400 pF

20 + 0.1

Cb

250

1

Internal Pin Capacitance

GATE DRIVERS

Parameter

Min.

Typ.

Max.

Units

Conditions

GH, GL Rise Time

GH, GL Fall Time

17

11

ns

At 10-90% of full scale, 1nF C_load

GH, GL Pull-Up On-State Output

Resistance

4

2

5

Ω

GH, GL Pull-Down On-State

Output Resistance

2.5

GH, GL Pull-Down Resistance in

Off-Mode

50

9

kΩ

Ω

VCC = VCCD = 0V.

@ 10mA

Bootstrap diode forward

resistance

Minimum On Time

Minimum Off Time

50

ns

1nF of gate capacitance.

1nF of gate capacitance

125

Minimum Programmable Dead

Time

20

ns

Does not include dead time variation from

driver output stage

Tsw=switching period

Maximum Programmable Dead

Time

Tsw

607

Programmable Dead Time

Adjustment Step

ps

6/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

BLOCK DIAGRAM

BST1

Channel 1

GH1

LX1

Feedback

ADC

Digital

PID

Hybrid

DPWM

VOUT1

Gate

Driver

GL1

PreScaler

1/2/4

Dead

Time

GL_RTN1

VCC

V_REF

DAC

Current

ADC

SS & PD

VCCD1-2

VOUT3

VOUT4

Channel 2

Channel 3

VCCD3-4

Channel 4

Vout1

Vout2

Vout3

Vout4

Vtj

4uA

ENABLE

GPIO 0-1

Internal

POR

MUX

NVM

(FLASH)

GPIO

Sequencing

BFB

VCC

Fault

Handling

OTP

UVLO

OCP

PSIO 0-2

SDA,SCL

PWR

Good

Configuration

Registers

PSIO

I2C

LDO5

OVP

5V LDO

LOGIC

CLOCK

LDO3_3

3.3V LDO

Fig. 2: XRP7724 Block Diagram

LDO BLOCK DIAGRAM

VCCD3-4 VCCD1-2

LDO5

DVDD

AVDD

1.8V

Regulator

Gate Drivers

5V LDO

1.8V Analog

1.8V Digital

5V Blocks

PSIO

3.3V Regulator

3.3V GPIO

VCC

LDO3_3

3.3V LDO

+

-

4.75V – 4.9V

V5EXT

Fig. 3: XRP7724 LDO Block Diagram

7/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

PIN ASSIGNMENT

LDO3_3

1

2

33

32

31

30

29

28

27

26

25

24

23

GL_RTN2

GL2

AGND

CPLL

3

LX2

AVDD

VOUT1

VOUT2

VOUT3

VOUT4

GPIO0

GPIO1

SDA

4

GH2

5

BST2

GL_RTN3

GL3

XRP7724

TQFN

7mm X 7mm

6

7

8

LX3

9

GH3

Exposed Pad: AGND

10

11

BST3

VCCD3-4

Fig. 4: XRP7724 Pin Assignment

PIN DESCRIPTION

Name

Pin Number

Description

Input voltage. Place a decoupling capacitor close to the controller IC. This input is used

in UVLO fault generation.

41

16

VCC

1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling

capacitor close to the controller IC.

DVDD

Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies

drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be

connected to the LDO5 pin to enable two power rails initially. It is recommended that

the other VCCD pin be connected to the output of a 5V switching rail(for improved

efficiency or for driving larger external FETs), if available, otherwise this pin may also

be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for

each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch.

VCCD1-2

VCCD3-4

23,34

2

Analog ground pin. This is the small signal ground connection.

AGND

Ground connection for the low side gate driver. This should be routed as a signal trace

with GL. Connect to the source of the low side MOSFET.

39,33, 28,22

38,32, 27,21

36,30, 25,19

GL_RTN1-4

Output pin of the low side gate driver. Connect directly to the gate of an external N-

channel MOSFET.

GL1-GL4

GH1-GH4

Output pin of the high side gate driver. Connect directly to the gate of an external N-

channel MOSFET.

8/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

Name

Pin Number

Description

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching

node at the junction between the two external power MOSFETs and the inductor. These

pins are also used to measure voltage drop across bottom MOSFETs in order to provide

output current information to the control engine.

37,31, 26,20

LX1-LX4

High side driver supply pin(s). Connect BST to the external capacitor as shown in the

Typical Application Circuit on page 2. The high side driver is connected between the

BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each

cycle.

35,29, 24,18

9,10

BST1-BST4

GPI0-GPIO1

PSIO0-PSIO2

These pins can be configured as inputs or outputs to implement custom flags, power

good signals, enable/disable controls and synchronization to an external clock.

Open drain, these pins can be used to control external power MOSFETs to switch loads

on and off, shedding the load for fine grained power management. They can also be

configures as standard logic outputs or inputs just as any of the GPIOs can be

configured, but as open drains require an external pull-up when configured as outputs.

13,14,15

SMBus/I²C serial interface communication pins.

11,12

SDA, SCL

Connect to the output of the corresponding power stage. The output is sampled at least

once every switching cycle

5,6,7,8

VOUT1-VOUT4

Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of

the IC is in shutdown. This LDO is also used to power the internal Analog Blocks.

44

1

LDO5

Output of the 3.3V standby LDO. This is a micro power LDO that can remain active

while the rest of the IC is in shutdown.

LDO3_3

If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,

registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be

placed into shutdown.

40

42

ENABLE

BFB

Input from the 15V output created by the external boost supply. When this pin goes

below a pre-defined threshold, a pulse is created on the low side drive to charge this

output back to the original level. If not used, this pin should be connected to GND.

Digital ground pin. This is the logic ground connection, and should be connected to the

ground plane close to the PAD.

17

3

DGND

CPLL

Connect to a 2.2nF capacitor to GND.

External 5V that can be provided. If one of the output channels is configured for 5V,

then this voltage can be fed back to this pin for reduced operating current of the chip

and improved efficiency.

43

V5EXT

Output of the internal 1.8V LDO. A decoupling capacitor should be placed between

AVDD and AGND close to the chip.

4

AVDD

PAD

This is the die attach paddle, which is exposed on the bottom of the part. Connect

externally to the ground plane.

45

ORDERING INFORMATION

Temperature

Part Number

Packing

Quantity

I²C Default

Address

Marking

Package

Note 1

Range

XRP7724ILB-F

Bulk

Halogen Free

-40°C≤T_J≤+125°C

XRP7724ILB

YYWW X

0x28 (7Bit)

44-pin TQFN

XRP7724ILBTR-F

2.5K/Tape & Reel

Evaluation kit includes XRP7724EVB-DEMO-1 Evaluation Board with Power

Architect software and XRP77XXEVB-XCM (USB to I²C Exar Configuration Module)

XRP7724EVB-DEMO-2P-KIT

“YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable.

9/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

TYPICAL PERFORMANCE CHARACTERISTICS

All data taken at VCC = 12V, T_J= T_A= 25°C, unless otherwise specified - Schematic and BOM from XRP7724EVB. See

XRP7724EVB-DEMO-1 Manual.

Fig. 6 PWM to PFM Transition

Fig. 5: PFM to PWM Transition

Fig. 7 0-6A Transient 300kHz PWM only

Fig. 9 Sequential Start-up

Fig. 8 10-6A Transient 300kHz with OVS ±5.5%

Fig. 10 Sequential Shut Down

10/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

Example

Fig. 11: Simultaneous Start-up

Fig. 12 Simultaneous Shut Down

Fig. 13: PFM Zero Current Accuracy

Fig. 14: LDO5 Brown Out Recovery, No Load

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

Vin=25V

Rising

Vin=25V

Falling

Vin=4.75

V Rising

Vin=4.75

V Falling

-40°C

25°C

85°C

125°C

Fig. 15: Enable Threshold Over Temp

11/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

System Integration Capabilities

 Single supply operation

 I²C interface allows:

FEATURES AND BENEFITS

Programmable Power Benefits

 Fully Configurable

 Output set point

 Communication with a System Controller

or other Power Management devices for

optimized system function

 Feedback compensation

 Frequency set point

 Under voltage lock out

 Input voltage measurement

 Gate drive dead time

 Access to modify or read internal

registers that control or monitor:

 Output Current

 Input and Output Voltage

 Soft-Start/Soft-Stop Time

 ‘Power Good’

 Reduced Development Time

 Configurable and re-configurable for

different Vout, Iout, Cout, and Inductor

values

 Part Temperature

 Enable/Disable Outputs

 Over Current

 No need to change external passives for a

new output specification.

 Over Voltage

 Higher integration and Reliability

 Temperature Faults

 Many external circuits used in the past

can be eliminated significantly improving

reliability.

 Adjusting fault limits and

disabling/enabling faults

 Packet Error Checking (PEC) on I²C

communication

PowerArchitect™ 5.0 Design and

 5 GPIO pins with a wide range of

Configuration Software

configurability

 Wizard quickly generates a base design

 Calculates all configuration registers

 Projects can be saved and/or recalled

 Fault reporting (including UVLO

Warn/Fault, OCP Warn/Fault, OVP,

Temperature, Soft-Start in progress,

Power Good, System Reset)

 GPIOs can be configured easily and

intuitively

 Allows a Logic Level interface with other

non-digital IC’s or as logic inputs to other

devices

 “Dashboard” Interface can be used for

real-time monitoring and debug

 Frequency and Synchronization

System Benefits

Capability

 Reliability is enhanced via communication

with the system controller which can obtain

real time data on an output voltage, input

voltage and current.

 Selectable switching frequency between

105kHz and 1.2MHz

 Main oscillator clock and DPWM clock can

be synchronized to external sources

 System processors can communicate with

the XRP7724 directly to obtain data or

make adjustments to react to circuit

conditions

 ‘Master’, ‘Slave’ and ‘Stand-alone’

Configurations are possible

 Internal MOSFET Drivers

 Internal FET drivers (4Ω/2Ω) per channel

 Built-In Automatic Dead-time adjustment

 30ns Rise and Fall times

 A system process or could also be

configured to log and analyze operating

history, perform diagnostics and if required,

take the supply off-line after making other

system adjustments.

 4 Independent SMPS channels and 2

LDOs in a 7x7mm TQFN

12/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

external circuitry. The 3.3V LDO is solely for

customer use and is not used by the chip.

There is also a 1.8V linear which is for internal

use only and should not be used externally.

FUNCTIONAL OVERVIEW

The XRP7724 is a quad-output digital pulse

width modulation (DPWM) controller with

integrated

gate

drivers

for

use

with

A key feature of the XRP7724 is its powerful

power management capabilities. All four

outputs are independently programmable and

gives the user not only full control of the

delay, ramp, and sequence during power up

and power down. One can also control of how

the outputs interact and power down in the

event of a fault. This includes active ramp

down of the output voltages to remove an

output voltage as quickly as possible. Another

nice feature is that the outputs can be defined

and controlled as groups.

synchronous buck switching regulators. Each

output voltage can be programmed from 0.6V

to 5.5V without the need of an external

voltage divider. The wide range of the

programmable DPWM switching frequency

(from 105 kHz to 1.2 MHz) enables the user to

optimize for efficiency or component sizes.

Since the digital regulation loop requires no

external

passive

components,

loop

performance is not compromised due to

external component variation or operating

condition.

The XRP7724 has two main types of

programmable memory. The first types are

runtime registers that contain configuration,

control and monitoring information for the

chip. The second type is rewritable Non-

Volatile Flash Memory (NVFM) that is used for

permanent storage of the configuration data

along with various chip internal functions.

During power up the run time registers are

loaded from the NVFM allowing for standalone

operation.

The XRP7724 provides a number of critical

safety

features, such

as

Over-Current

Protection (OCP), Over-Voltage Protection

(OVP), Over Temperature Protection (OTP)

plus input Under Voltage Lockout (UVLO). In

addition, a number of key health monitoring

features such as warning level flags for the

safety functions, Power Goods (PGOOD), etc.,

plus full monitoring of system voltages and

currents. The above are all programmable

and/or readable from the SMBus and many

are steerable to the GPIOs for hardware

monitoring.

The XRP7724 brings an extremely high level of

functionality

programmable

and

performance

system.

to

a

Ever

power

For hardware communication, the XRP7724

has two logic level General Purpose Input-

Output (GPIO) pins and three, 15V, open

drain, Power System Input-Output (PSIO)

pins. Two pins are dedicated to the SMBus

data (SDA) and clock (SCL). Additional pins

include Chip Enable (Enable), Aux Boost

Feedback (BFB) and External PLL Capacitor

(CPLL).

decreasing product budgets require the

designer to quickly make good

cost/performance tradeoffs to be truly

successful. By incorporating 4 switching

channels, two user LDOs, a charge pump

boost controller, along with internal gate

drivers, all in a single package, the XRP7724

allows for extremely cost effective power

system designs. Another key cost factor to

put into the cost tradeoffs, which is often

overlooked, is the unanticipated Engineering

Change Order (ECO). The programmable

versatility of the XRP7724, along with the lack

of hard wired, on board configuration

components, allows for minor and major

changes to be made, in circuit, on the board

by simple reprogramming.

In addition to providing four switching outputs,

the XRP7724 also provides control for an Aux

boost supply, and two stand-by linear

regulators that produce 5V and 3.3V for a total

of 7 customer usable supplies in a single

device.

The 5V LDO is used for internal power and is

also available for customer use to power

13/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

THEORY OF OPERATION

CHIP ARCHITECTURE

REGULATION LOOPS

Vin

(VCC)

Vdrive

(VCCD)x

AFE

Vref

DAC

Vin Feed

Forward

Fine

Adjust

GHx

GLx

LXx

Scalar

÷1,2,4

Error

Amp

AFE

ADC

Error

Register

Gate

Driver

VFB

(VOUTx)

PID

DPWM

Window

Comp.

Current

ADC

OVS

PFM/

Ultrasonic

PWM-

PFM Sel

Fig 16 XRP7724 Regulation Loops

Figure 16 shows a functional block diagram of

the regulation loops for an output channel.

There are four separate parallel control loops;

up to 1.6V (low range) the scalar has a gain of

1. For output voltages from 1.6V to 3.2V (mid

range) the scalar gain is 1/2 and for voltages

greater than 3.2V (high range) the gain is 1/4.

This results in the low range having a

reference voltage resolution of 12.5mV, mid

range of 25mV and the high range having a

resolution of 50mV. The error amp has a gain

of 4 and compares the output voltage of the

scalar to Vref to create an error voltage on its

output. This is converted to a digital error

term by the AFE ADC which is stored in the

error register. The error register has a fine

adjust function that can be used to improve

the output voltage set point resolution by a

factor of 5 resulting in a low range resolution

of 2.5mV, mid range resolution of 5mV and a

high range resolution of 10mV. The output of

the error resister is then used by the

Pulse

Width

Modulation

(PWM),

Pulse

Frequency Modulation (PFM), Ultrasonic, and

Over Sampling (OVS). Each of these loops is

fed by the Analog Front End (AFE) as shown at

the left of the diagram. The AFE consist of an

input voltage scalar, a programmable Voltage

Reference (Vref) DAC, Error Amplifier, and a

window comparator. (Please note that the

block diagram shown is simplified for ease of

understanding. Some of the function blocks

are common and shared by each channel by

means of a multiplexer.)

PWM Loop

The PWM loop operates in Voltage Control

Mode (VCM) with optional Vin feed forward

based on the voltage at the VCC pin. The

reference voltage (Vref) for the error amp is

created by a 0.15V to 1.6V DAC that has a

12.5mV resolution. In order to get a full 0.6V

to 5.5V output voltage range an input scalar is

used to reduce feedback voltages for higher

output voltages to bring them within the 0.15V

to 1.6V control range. So for output voltages

Proportional

Integral

Derivative

(PID)

controller to manage the loop dynamics.

The XRP7724 PID is a 17-bit five coefficient

control engine that calculates the correct duty

cycle under the various operating conditions

and feeds it to the Digital Pulse Width

Modulator (DPWM). Besides the normal

14/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

coefficients the PID also uses the Vin voltage

to provide a feed forward function.

The PFM loop works in conjunction with the

PWM loop and is entered when the output

current falls below a programmed threshold

level for a programmed number of cycles.

When PFM mode is entered, the PWM loop is

disabled and instead, the scaled output

voltage is compared to Vref with a window

comparator. The window comparator has three

thresholds; normal (Vref), high (Vref +

%high) and low (Vref - %low). The %high and

%low values are programmable and track

Vref.

The XRP7724 DPWM includes a special delay

timing loop that gives a timing resolution that

is 16 times the master oscillator frequency

(103MHz) for a timing resolution of 607ns for

both the driver pulse width and dead time

delays. The DWPM creates and outputs the

Gate High (GH) and Gate Low (GL) signals to

the driver. The maximum and minimum on

times and dead time delays are programmable

by configuration resisters.

In PFM mode, the normal comparator is used

to regulate the output voltage. If the output

voltage falls below the Vref level, the

comparator is activated and triggers the

DPWM to start a switching cycle. When the

high side FET is turned on, the inductor

current ramps up which charges up the output

capacitors and increasing their voltage. After

the completion of the high side and low side

on-times, the lower FET is turned off to inhibit

any inductor reverse current flow. The load

current then discharges the output capacitors

until the output voltage falls below Vref and

the normal comparator is activated this then

triggers the DPWM to start the next switching

cycle. The time from the end of the switching

cycle to the next trigger is referred to as the

dead zone. This PFM methodology ensures

output voltage ripple does not increase from

PWM to PFM.

To provide current information, the output

inductor current is measured by a differential

amplifier that reads the voltage drop across

the RDS of lower FET during its on time. There

are two selectable ranges, a low range with a

gain of 8 for a +20mV to -120 mV range and a

high range with a gain of 4 for +40mV to -

280mV range. The optimum range to use will

depend on the maximum output current and

the RDS of the lower FET. The measured

voltage is then converted to a digital value by

the current ADC block. The resulting current

value is stored in a readable register and also

used to determine when PWM to PFM

transitions should occur.

PFM mode loop

The XRP7724 has a PFM loop that can be

enabled to improve efficiency at light loads.

By reducing switching frequency and operating

in the discontinuous conduction mode (DCM),

both switching and I²R losses are minimized.

When PFM mode is initially entered the

switching duty cycle is the same that it was in

PWM mode. The cause the inductor ripple

current to be the same level that it was in

PWM mode. During operation the PFM duty

cycle is calculated based on the ratio of the

output voltage to VCC.

Figure 17 shows a functional diagram of the

PFM logic.

# Cycles Reg

Default = 20

A

CHx Fsw

COUNTER

A<B

If the output voltage ever goes outside the

high/low windows, PFM mode is exited and the

PWM loop is reactivated.

Clk

PFM Current

Threshold Reg

Clear

A

B

A<B

I_ADC

B

Although the PFM mode does a good job in

improving efficiency at light load, at very light

loads the dead zone time can increase to the

point where the switching frequency can enter

the audio hearing range. When this happens

some components, like the output inductor

and ceramic capacitors, can emit audible

noise. The amplitude of the noise depends

PWM MODE

PFM MODE

Q

S

R

VOUT

+

-

V_REFHIGH

PFM EXIT

TRIGGER PULSE

-

+

V_REF

-

+

V_REFLOW

Fig 17: PFM Enter/Exit Functional Diagram

15/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

mostly on the board design and on the

delay of up to one switching cycle before the

control loop can respond. With OVS enabled if

output voltage drops below the lower level, an

immediate GH pulse will be generated and

sent to the driver to increase the output

inductor current toward the new load level

without having to wait for the next cycle to

begin. If the output voltage is still below the

lower limit at the beginning of the next cycle,

OVS will work in conjunction with the PID to

insert additional GH pulses to quickly return

the output voltage back within its regulation

band. The result of this system is transient

response capabilities on par or exceeding

those of a constant on-time control loop.

manufacturer and construction details of the

components. Proper selection of components

can reduce the sound to very low levels. In

general Ultrasonic Mode is not used unless

required as it reduces light load efficiency.

Ultrasonic Mode

Ultrasonic mode is an extension of PFM to

ensure that the switching frequency never

enters the audible range. When this mode is

entered, the switching frequency is set to

30kHz and the duty cycle of the upper and

lower FETs, which are fixed in PFM mode, are

decreased as required to keep the output

voltage in regulation while maintaining the

30kHz switching frequency.

Over Voltage OVS: When there is a step load

current decrease, the output voltage will

increase (bump up) as the excess inductor

current that is no longer used by the load,

flows into the output capacitors causing the

Under extremely light or zero load currents,

the GH on time pulse width can decrease to its

minimum width. When this happens, the lower

FET on time is increased slightly to allow a

small amount of reverse inductor to flow back

into Vin to keep the output voltage in

regulation while maintaining the switching

frequency above the audio range.

output voltage to rise.

The voltage will

continue to rise until the inductor current

decreases to the new load current. With OVS

enabled, if the output voltage exceeds the

high limit of the window comparator, a

blanking pulse is generated to truncate the GH

signal. This causes inductor current to

immediately begin decreasing to the new load

level. The GH will continue to be blanked until

the output voltage falls below the high limit.

Again, since the output voltage is sampled at

four times the switching frequency, over shoot

will be decreased and the time required to get

back into the regulation band is also

decreased.

Oversampling OVS Mode

Oversampling (OVS) mode is a feature added

to the XRP7724 to improve transient

responses. This mode can only be enabled

when the channel switching frequency is

operating in 1x frequency mode. In OVS mode

the output voltage is sampled 4 times per

switching cycle and is monitored by the AFE

window comparator. If the voltage goes

outside the set high or low limits, the OVS

control electronics can immediately modify the

pulse width of the GH or GL drivers to respond

accordingly, without having to wait for the

next cycle to start. OVS has two types of

response depending on whether the high limit

is exceeded during an unloading transient

(Over Voltage), or the low limit is exceeded

during a loading transient (Under Voltage).

OVS can be used in conjunction with both the

PWM and PFM operating modes. When it is

activated it can noticeably decrease output

voltage excursions when transitioning between

PWM and PFM modes.

INTERNAL DRIVERS

The internal high and low gate drivers use

totem pole FETs for high drive capability. They

are powered by two external 5V power pins

(VCCD1-2) and (VCCD3-4), VCCD1-2 powers

the drivers for channels 1 and 2 and VCCD3-4

powers channels 3 and 4. The drivers can be

powered by the internal 5V LDO by connecting

their power pins to the LDO5 output through

Under Voltage OVS: If there is an increasing

current load step, the output voltage will drop

until the regulator loop adapts to the new

conditions to return the voltage to the correct

level. Depending on where in the switching

cycle the load step happens there can be a

16/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

an RC filter to avoid conducted noise back into

the analog circuitry.

(VCC) supply. The output of LDO5 should be

bypassed by good quality capacitor

a

connected between the pin and ground close

to the device. The 5V output is used by the

XRP7724 as a standby power supply and is

also used to power the 3.3V and 1.8V linear

regulators inside the chip and can also supply

power to the 5V gate drivers. The total output

current that the 5V LDO can provide is 130mA.

The XRP7724 consumes approximately 20mA

and the rest is shared between LDO3_3 and

the gate drive currents. During initial power

up, the maximum external load should be

limited to 30mA.

To minimize power dissipation in the 5V LDO it

is recommended to power the drivers from an

external 5V power source either directly or by

using the V5EXT input. Good quality 1uF to

4.7uF capacitors should be connected directly

between the power pins to ground to optimize

driver performance and minimize noise

coupling to the 5V LDO supply.

The driver outputs should be connected

directly

to

their

corresponding

output

switching FETs, with the Lx output connected

to the drain of the lower FET for the best

current monitoring accuracy.

The 3.3V LDO output available on the LDO3_3

pin is solely for customer use and is not used

internally. This supply may be turned on or off

by the configuration registers. Again a good

bypass capacitor should be used.

See ANP-32 “Practical Layout Guidelines for

Power^XRDesigns”

LDOS

The AVVD pin is the 1.8V regulator output and

needs to be connected externally to the DVVD

pin on the device. A good quality capacitor

should be connected between this pin and

ground close to the package.

The XRP7724 has two internal Low Drop Out

(LDO) linear regulators that generate 5.0V

(LDO5) and 3.3V (LDO3_3) for both internal

and external use. Additionally it also has a

1.8V regulator that supplies power for the

XRP7724 internal circuits. Figure 3 shows a

block diagram of the linear power supplies.

LDO5 is the main power input to the device

and is supplied by an external 5.5V to 25V

For operation with a VCC of 4.75V to 5.5V, the

LDO5 output needs to be connected directly to

VCC on the board.

CLOCKS AND TIMING

Ext Clock Output

GPIO1

¸4/¸8

Clock

Reg

Divider

Freg Mult Reg

PLL

DPWM

System Clock

Ext Clock Input

GPIO0

SEL

Base Frequency

2x

4x

CH1 Timing

x4/x8

Reg

Frequency

Set Reg

Sequencer

To Channels 2®4

Fig 18 XRP7724 Timing Block Diagram

17/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

Base

Frequency

Available 2x

Frequencies

kHz

Available 4x

Frequencies

kHz

Figure 18 shows a simplified block diagram of

the XRP7724 timings. Again, please note that

the function blocks and signal names used are

chosen for ease of understanding and do not

necessarily reflect the actual design.

kHz

422.1

429.2

436.4

444.0

451.8

459.8

468.2

476.9

485.8

495.2

504.9

515.0

525.5

536.5

547.9

559.8

572.2

585.2

598.8

613.1

628.0

643.8

660.3

677.6

695.9

715.3

735.7

757.4

780.3

804.7

830.6

858.3

887.9

919.6

953.7

990.4

1030.0

1072.9

1119.6

1170.5

1226.2

211.1

214.6

218.2

222.0

225.9

229.9

234.1

238.4

242.9

247.6

252.5

257.5

262.8

268.2

273.9

279.9

286.1

292.6

299.4

306.5

314.0

321.9

330.1

338.8

348.0

357.6

367.9

378.7

390.2

402.3

415.3

429.2

444.0

459.8

476.9

495.2

515.0

536.5

559.8

585.2

613.1

105.5

107.3

109.1

111.0

112.9

115.0

117.0

119.2

121.5

123.8

126.2

128.8

131.4

134.1

137.0

139.9

143.1

146.3

149.7

153.3

157.0

160.9

165.1

169.4

174.0

178.8

183.9

189.3

195.1

201.2

207.7

214.6

222.0

229.9

238.4

247.6

257.5

268.2

279.9

292.6

306.5

The system timings are generated by a

103MHz internal system clock (Sys_Clk).

There are two ways that the 103 MHz system

clock can be generated. These include an

internal oscillator and a Phase Locked Loop

(PLL) that is synchronized to an external clock

input. The basic timing architecture is to

divide the Sys_Clk down to create a

fundamental switching frequency (Fsw_Fund)

for all the output channels that is settable

from 105kHz to 306kHz. The switching

frequency for a channel (Fsw_CHx) can then

be selected as 1 times, 2 times or 4 times the

fundamental switching frequency.

To set the base frequency for the output

channels a “Fsw_Set” value representing the

base frequency shown in Table 1, is entered

into the switching frequency configuration

register (Fsw_Set is basically equal to the

base frequency times 256). The system

timings are then created by dividing down

Sys_Clk to produce a base frequency clock,

2X and 4X times the base frequency clocks,

and sequencing timing to position the output

channels relative to each other. Each output

channel then has its own frequency multiplier

register that is used to select its final output

switching frequency.

Table 1 shows the available channel switching

frequencies for the XRP7724 device. In

practice the PowerArchitect™ 5.0 design tool

handles all the details and the user only has

to enter the fundamental switching frequency

and the 1x, 2x, 4x frequency multiplier for

each channel.

Table 1

If an external clock is used, the frequencies in

this table will shift accordingly.

18/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

 General Output – set with

an I2C

SUPERVISORY AND CONTROL

command

Power system design with XRP7724 is

accomplished using PowerArchitect™ design

tool version 5 (PA5). All figures referenced in

the following sections are taken from PA5.

Furthermore, the following sections reference

I²C commands. For more on these commands

please refer to ANP-38.

 General Input – triggers an interrupt;

state read with an I2C command

 Power Group Enable

–

controls

enabling and disabling of Group 1 and

Group 2

 Power Channel Enable – controls

enabling and disabling of a individual

channel including LDO3.3

 I²C Address Bit – controls an I2C

DIGITAL I/O

XRP7724 has two General Purpose Input

Output (GPIO) and three Power System Input

Output (PSIO) user configurable pins.

address bit

 Power OK – indicates that selected

channels have reached

their target

levels and have not faulted. Multiple

channel selection is available in which

case the resulting signal is the AND logic

function of all channels selected

 ResetOut – is delayed Power OK. Delay

is programmable in 1msec increments

with the range of 0 to 255 msecs

 Low Vcc – indicates when Vcc has fallen

below the UVLO fault threshold and

when the UVLO condition clears (Vcc

voltage rises above the UVLO warning

level)

 GPIOs are 3.3V CMOS logic compatible

and 5V tolerant.

 PSIO configured as outputs are open

drain and require external pull-up

resistor. These I/Os are 3.3V and 5V

CMOS logic compatible, and up to 15V

capable.

 Interrupt – the controller generated

interrupt selection and clearing is done

through I²C commands

Interrupt, Low Vcc, Power OK and ResetOut

signals can only be forwarded to a single

GPIO/PSIO.

The polarity of the GPIO/PSIO pins is set in

PA5 or with an I²C command.

In addition, the following are functions that

are unique to GPIO0 and GPIO1.

Configuring GPIO/PSIOs

The following functions can be controlled from

or forwarded to any GPIO/PSIO:

19/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

HW Flags – these are hardware monitoring

functions forwarded to GPIO0 only. The

functions include Under-Voltage Warning,

Over- Temperature Warning, Over-Voltage

Fault, Over-Current Fault and Over -Current

Warning for every channel. Multiple selection

is available in which case the resulting signal

is the OR logic function

 “PGood Max” is the upper window and

“PGood Min” is the lower window. The

minimum and maximum for each of these

values can be calculated by the following

equation:

ꢇ ꢈ ꢉꢊꢋꢃꢌꢍꢅ ꢈ ꢎꢏ^ꢐ

ꢃ ꢅ

ꢀꢁꢁꢂ ꢄ ꢆ

ꢍꢑꢒꢓꢔꢕꢑꢖꢃꢍꢅ

 External

Clock-in

–

enables

the

 Where N =1 to 63 for the PGOOD Max

value and N=1 to 62 for the PGOOD Min

controller to lock to an external clock

including one from another XRP7724

applied to the GPIO0 pin. There are two

ranges of clock frequencies the controller

accepts, selectable by a user

value.

For example, with the target

voltage of 1.5V and set point resolution of

2.5mV (LSB), the Power Good min and

max values can range from 0.17% to

10.3% and 0.17% to 10.5% respectively.

A user can effectively double the values

by changing to the next higher output

voltage range setting, but at the expense

of reduced set point resolution.

 External Clock-out – clock sent out

through GPIO1 for synchronizing with

another XRP7724 (see the clock out

section for more information).

FAULT HANDLING

There are seven different types of fault

handling:

 HW Power Good – the Power Good

hardware monitoring function. It can only

be forwarded to GPIO1. It is an output

voltage monitoring function that is a

hardware comparison of channel output

voltage against its user defined Power

Good threshold limits (Power Good

minimum and maximum levels). . It has

no hysteresis. Multiple channel selection is

available in which case the resulting signal

is the AND logic function of all channels

selected.

 Under

Voltage

Lockout

(UVLO)

monitors voltage supplied to the Vcc pin

and will cause the controller to shutdown

all channels if the supply drops to critical

levels.

 Over Temperature Protection (OTP)

monitors temperature of the chip and will

cause the controller to shutdown all

channels if temperature rises to critical

levels.

 Over

Voltage

Protection

(OVP)

monitors regulated voltage of a channel

and will cause the controller to react in a

user specified way if the regulated voltage

surpasses threshold level.

 Over

Current

Protection

(OCP)

 The Power Good minimum and maximum

levels are expressed as percentages of the

target voltage.

monitors current of a channel and will

cause the controller to react in a user

20/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

specified way if the current level

surpasses threshold level.

level at 4.6V may result in the outputs not re-

enable until a full 5.0V is reached on Vcc.

Setting the warning level to 4.6v and the fault

level at 4.4V would likely make UVLO handing

as desired, however, below 4.6V the device

has a hardware UVLO on LDO5 to ensure

proper shutdown of the internal circuitry of

the controller. This means the 4.4V UVLO

fault level will never occur. A special test has

been added to ensure that if UVLO FAULT will

 Start-up Time-out Fault monitors if a

channel gets into regulation in a user

defined time period

 LDO5 Over Current Protection (LDO5

OCP) monitor current drawn from the

regulator and will cause the controller to

be reset if the current exceeds LDO5 limit

(155mA typical)

 LDO3.3

Over

Current

Protection

OTP

(LDO3.3 OCP) monitors current drawn

from the regulator and will cause the

controller to shut down the regulator if the

current exceeds LDO3.3 current limit

(65mA typical)

User defined OTP warning, fault and restart

levels are set at 5°C increments in PA5.

UVLO

Both UVLO warning and fault levels are user

programmable and set at 200mV increments

in PA5.

When the warning level is reached the

controller

will

generate

the

In

TEMP_WARNING_EVENT

interrupt.

addition, the host can be informed about the

event through HW Flags on GPIO0 (see the

Digital I/O section).

When the warning level is reached the

When an OTP fault condition occurs, the

XRP7724 outputs are shutdown and the

TEMP_OVER_EVENT interrupt is generated.

controller

UVLO_WARNING_EVENT

will

generate

the

In

interrupt.

addition, the host can be informed about the

event through HW Flags on GPIO0 (see the

Digital I/O section).

Once temperature reaches a user defined OTP

Restart

TEMP_UNDER_EVENT

Threshold

level,

interrupt

the

be

will

When an under voltage fault condition occurs,

the XRP7724 outputs are shutdown and the

generated and the controller will reset.

UVLO_FAULT_ACTIVE_EVENT

interrupt

is

OVP

generated. In addition, the host can be

informed by forwarding the Low Vcc signal to

any GPIO/PSIO (see the Digital I/O section).

This signal transitions when the UVLO fault

occurs. When coming out of the fault, rising

Vcc crossing the UVLO fault level will trigger

the UVLO_FAULT_INACTIVE_EVENT interrupt.

A user defined OVP fault level is set in PA5

and is expressed in percentages of a

regulated target voltage.

Once UVLO condition clears (Vcc voltage rises

Above or TO the user defined UVLO warning

level), the Low Vcc signal will transition and

the controller will be reset.

Resolution is the same as for the target

voltage (expressed in percentages). The OVP

minimum and maximum values are calculated

by the following equation where the range for

N is 1 to 63:

A special attention needs to be paid in the

case when Vcc = LDO5 = 4.75V to 5.5V.

Since the input voltage ADC resolution is

200mV, the UVLO warning and fault set

points are coarse for a 5V input. Therefore,

setting the warning level at 4.8V and the fault

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When the OVP level is reached and the fault is

generated, the host will be notified by the

21/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

SUPPLY_FAULT_EVENT interrupt generated by

the controller. The host then can use anI2C

command to check which channel is at fault.

as defined in the electrical characteristics.

The maximum value the user can program is

limited by Rdson of the synchronous Power

FET and current monitoring ADC range. For

example, using a synchronous FET with Rdson

of 30mΩ, using the wider ADC range, the

maximum current limit programmed would

be:

In addition, OVP fault can be monitored

through GPIO0.

A user can choose one of three options on

how to react to an OVP event: to shutdown

the faulting channel, to shut down faulting

channel and to perform auto-restart of the

channel, or to restart the chip.

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The current is sampled approximately 30ns

before the low side MOSFET turns off, so the

actual measured DC output current in this

example would be 9.33A plus approximately

half the inductor ripple.

An OCP Fault is considered to have occurred

only if the fault threshold has been tripped in

4 consecutive switching cycles. When the

switching frequency is using the 4x multiplier,

the current is sampled only every other cycle.

As a result it can take as many as 8 switching

cycles for an over current event to be

In the case of shutting down the faulting

channel and auto-restarting, the user has an

option to specify startup timeout (the time in

which the fault is validated) and hiccup

timeout (the period after which the controller

will try to restart the channel) periods in 1

msec increments with a maximum value of

255 msec.

detected.

When operating in 4x mode

inductors with a soft saturation characteristic

are recommended.

When the OCP level is reached and the fault is

generated, the host will be notified by the

SUPPLY_FAULT_EVENT interrupt generated by

the controller. The host then can use an I2C

command to check which channel is at fault.

In addition, OCP fault can be monitored

through HW Flags on GPIO0. The host can

also monitor OCP warning flag through HW

Flags on GPIO0. The OCP warning level is

calculated by PowerArchitect™ as 85% of the

OCP fault level.

Note: a channel will share a response to an

OVP or OCP event.

A user can choose one of three options on

how to react to an OCP event: to shutdown

the faulting channel, to shut down faulting

channel and to perform auto-restart of the

channel, or to restart the chip.

OCP

A user defined OCP fault level is set with 1mA

increments in PA5. PA5 uses calculations to

give the user the approximate DC output

current entered in the current limit field.

However the actual current limit trip value

programmed into the part is limited to 280mV

The output current reported by the XRP7724

is processed through a 7 sample median filter

in order to reduce noise. The OCP limit is

compared against unfiltered ADC output.

22/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

V5EXT SWITCHOVER

The V5EXT gives a user an opportunity to

supply an external 5 Volt rail to the controller

in order to reduce the controller’s power

dissipation. The 5 Volt rail can be an

independent power rail present in a system or

any of 7724 channels regulated to 5 Volts (in

the PFM mode in particular) and routed back

to the V5EXT pin. It is important to mention

that voltage to Vcc must be applied all the

time even after the switchover in which case

the current drawn from Vcc supply will be

minimal.

In the case of shutting down the faulting

channel and auto-restarting, the user has an

option to specify startup timeout (the time in

which the fault is validated) and hiccup

timeout (the period after which the controller

will try to restart the channel) periods in 1

msec increments with a maximum value of

255 msec.

If the function not used, we recommend the

pin to be either grounded or left floating in

conjunction with making sure the function

gets disabled through register settings.

Note: a channel will share a response to an

OCP or OVP event.

V5EXT switchover control

The function is enabled in PA5. The

switchover thresholds are programmable in

50mV steps with a total range of 200mV.

Hysteresis to go in-out is 150mV. LDO5

automatically turns off when the external

voltage is switched in and turns on when the

external voltage drops below the lower

threshold.

Start-up Time-out Fault

A channel will be at Start-up Time-out Fault if

it does not come-up in a time period specified

in the “Startup Timeout” box. In addition, a

channel is at Start-up Timeout Fault if in pre-

bias configuration voltage is a defined value

too close to the target.

When the fault is generated, the host will be

notified

by

the

SUPPLY_FAULT_EVENT

interrupt generated by the controller. The

host then can use an I2C command to check

which channel is at fault.

LDO5 OCP

When current is drawn from LDO5 exceeds

LDO5 current limit the controller gets reset.

When the controller switches over to the

V5EXT rail, the V5EXT_RISE interrupt is

generated to inform the host. Similarly, when

the controller switches out, the V5EXT_FALL

interrupt gets generated.

LDO3.3 OCP

When current drawn from LDO3.3 exceeds

LDO3.3 current limit the regulator gets shut

down, a fault is generated, and the host will

be notified by the SUPPLY_FAULT_EVENT

interrupt generated by the controller. The

EXTERNAL CLOCK SYNCHRONIZATION

XRP7724 can be run off an external clock

available in the system or another XRP7724.

The external clock must be in the ranges of

10.9MHz to 14.7MHz or 21.8MHz to 29.6MHz.

Locking to the external clock is done through

an internal Phase Lock Loop (PLL) which

requires an external loop capacitor of 2.2nF to

host then can through

an I2C command

check which channel/regulator is at fault.

Once the fault condition is removed, the host

needs to turn the regulator on again.

23/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

be connected between the CPLL pin and

AGND.

Channels including LDO3.3 can be controlled

independently by any GPIO/PSIO or I2C

command. Channels will start-up or shut-

down following transitions of signals applied

to GPIO/PSIOs set to control the channels.

The control can always be overridden with an

I2C command.

In applications where this functionality is not

desired, the CPLL capacitor is not necessary

and can be omitted, and the pin shall be left

floating. In addition, the user needs to make

sure the function gets disabled through

register settings.

Regardless

whether

the

channels

are

controlled independently or are in a group,

the ramp rates specified are followed (see the

Power Sequencing section).

The external clock must be routed to GPIO0.

The GPIO0 setting must reflect the range of

the external clock applied to it: Sys_Clock/8

corresponds to the range of 10.9MHz to

Regulated voltages and voltage drops across

synchronous FET on each switching channel

can be read back using x I2C commands y.

The regulated voltage read back resolution is

15mV, 30mV and 60mV per LSB depending

on the target voltage range. The voltage drop

across synchronous FET read back resolution

is 1.25mV and 2.5mV per LSB depending on

the range.

14.7MHz

while

Sys_Clock/4

setting

corresponds to the range of 21.8Mhz to

29.6MHz.

The

functionality

is

enabled

in

PowerArchitect™ 5.0 by selecting External

Clock-in function under GPIO0.

Through an I2C command the host can check

the status of the channels; whether they are

in regulation or at fault.

For more on details how to monitor PLL lock

in-out, please contact Exar or your local Exar

representative.

Regulated voltages can be dynamically

changed on switching channels using I2C

commands with resolution of 2.5mV, 5mV

and 10mV depending on the target voltage

range (in PWM mode only).

CLOCK OUT

XRP7724 can supply clock out to be used by

another XRP7724 controller. The clock gets

routed out through GPIO1 and can be set to

system clock divided by 8 (Sys_Clock/8) or

system clock divided by 4 (Sys_Clock/4)

frequencies.

For more information on I2C commands

please contact Exar or your local Exar

representative.

POWER SEQUENCING

The functionality is enabled in PA5 by

selecting External Clock-Out function under

GPIO1.

All four channels and LDO3.3 can be grouped

together and as such start-up and shut-down

in a user defined sequence.

Selecting none means channel(s) will not be

assigned to any group and as such will be

controlled independently.

CHANNEL CONTROL

Group Selection

There are three groups:

24/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

 Group 0 – is controlled by the chip

milliseconds with a range of 0msec to

255msec.

ENABLE or I2C command. Channels

assigned to this group will come up with

the ENABLE signal being high, and will go

down with the ENABLE signal being low.

The control can always be overridden with

an I2C command.

Shut-down

 Since it is recommended to leave the

ENABLE pin floating in the applications

when Vcc = LDO5 = 4.75V to 5.5V, please

contact Exar for how to configure the

channels to come up at the power up in

this scenario.

 Group 1 – can be controlled by any

GPIO/PSIO or I2C command. Channels

assigned to this group will start-up or

shut-down following transitions of a signal

applied to the GPIO/PSIO set to control

the group. The control can always be

overridden with an I2C command.

 Group 2 – can be controlled by any

GPIO/PSIO or I2C command. Channels

assigned to this group will start-up or

shut-down following transitions of a signal

applied to the GPIO/PSIO set to control

the group. The control can always be

overridden with an I2C command.

For each channel within a group a user can

specify

the

following

shut-down

characteristics:

 Ramp Rate – expressed in milliseconds

per Volt. It does not apply to LDO3.3.

 Order – order position of a channel to

come-down within the group

 Wait Stop Thresh? – selecting this

option for a channel means the next

channel in the order cannot start ramping-

down until this channel reaches the Stop

Threshold level. The stop threshold level is

fixed at 600mV.

 Delay – additional time delay a user can

specify to postpone a channel shut-down

with respect to the previous channel in the

order. The delay is expressed in

milliseconds with a range of 0msec to

255msec.

Start-up

MONITORING VCC AND TEMPERATURE

Through I2C commands, the host can read

back voltage applied to the Vcc pin and the

die temperature respectively. The Vcc read

back resolution is 200mV per LSB; the die

temperature read back resolution is 5C° per

LSB. For more on I2C commands please refer

to ANP-38 “XRP7724 Command Set and

Programming Guide”.

For each channel within a group a user can

specify the following start-up characteristics:

 Ramp Rate – expressed in milliseconds

per Volt. It does not apply to LDO3.3.

 Order – order position of a channel to

come-up within the group

 Wait PGOOD? – selecting this option for

a channel means the next channel in the

order cannot start ramping-up until this

channel reaches the target level and its

Power Good flag gets asserted.

PROGRAMMING XRP7724

XRP7724 is a FLASH based device which

means its configuration can be programmed

into FLASH NVM and re-programmed a

number of times.

 Delay – an additional time delay a user

can specify to postpone a channel start-up

with respect to the previous channel in the

order. The delay is expressed in

Programming of FLASH NVM is done through

PA5.

25/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

By clicking on the Flash button, user will start

programming sequence of the design

configuration into the Flash NVM. After the

programming sequence completes, the chip

will reset (if automatically reset After Flashing

box is checked), and boot the design

configuration from the Flash.

ENABLING XRP7724

XRP7724 has a weak internal pull-up ensuring

it gets enabled as soon as internal voltage

supplies have ramped up and are in

regulation.

Driving the Enable pin low externally will keep

the controller in the shut-down mode. A

simple open drain pull down is the

recommended way to shut XRP7724 down.

If the Enable pin is driven high externally to

control XRP7724 coming out of the shut-down

mode, care must be taken in such a scenario

to ensure the Enable pin is driven high after

Vcc gets supplied to the controller.

For users that wish to create their own

programming procedure so they can re-

program Flash in-circuit using their system

software, please contact Exar for a list of I2C

Flash Commands needed.

In the configuration when Vcc = LDO5 =

4.75V to 5.5V, disabling the device by

During a design process a user might want to

repeatedly download a design configuration

onto run time registers without saving it in

Flash. This is done through PA5 as well.

grounding

the

Enable

is

not

recommended. At this time we recommend

leaving the Enable pin floating and placing the

controller in the “Standby Mode” instead in

this scenario. The standby mode is defined as

the state when all switching channels and

LDO3.3 are disabled, all GPIO/PSIOs are

programmed as inputs, and system clock is

disabled. In this state chip consumes 440uA

typical.

26/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

Short duration Enable pin toggled low

Short duration shutdown pulses to the

ENABLE pin of the XRP7724 which does not

provide sufficient time for the LDO5 voltage

to fall below 3.5V can result in significant

delay in re-enabling of the device. Some

examples below show LDO5 and ENABLE

pins:

Adding a 200 ohm load on LDO5 pulls voltage

below 3.5V and restart is short.

Note that as V_CCincreases, the restart time

falls as well. 5.5V input is shown as the worst

case.

Since the ENABLE pin has an internal current

source, a simple open drain pull down is the

recommended way to shut down the

XRP7724. A diode in series with a resistor

between the LDO5 and ENABLE pins may

offer a way to more quickly pull down the

LDO5 output when the ENABLE pin is pulled

low.

No load on LDO5, blue trace. Recovery time

after ENABLE logic high is approximately

40ms.

available in the system and connected to the

5V EXT pin. If there is no 5V available in the

system, then the power loss will increase

significantly and proper thermal design

APPLICATION INFORMATION

THERMAL DESIGN

As a 4 channel controller with internal

MOSFET drivers and 5V gate drive supply all

in one 7x7mm 44pin TQFN package, there is

the potential for the power dissipation to

exceed the package thermal limitations. The

XRP7724 has an internal LDO which supplies

5V to the internal circuitry and MOSFET

becomes critical.

For lower power levels

using properly sized MOSFETs, the use of the

internal 5V regulator as a gate drive supply is

considered appropriate.

LAYOUT GUIDELINES

Refer to application note ANP-32 “Practical

Layout Guidelines for Power^XRDesigns”.

drivers during startup.

expected that either one of the switching

regulator outputs is 5V or another 5V rail is

It is generally

27/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

PACKAGE SPECIFICATION

44-PIN 7X7MM TQFN

28/29

Rev. 1.0.1

XRP7724

Quad Channel Digital PWM/PFM

Programmable Power Management System

REVISION HISTORY

Revision

Date

Description

10/04/2012

Initial Release of Data Sheet

Eliminated “Native GH, GL Rise and Fall Time” typical specification.

1.0.0

1.0.1

FOR FURTHER ASSISTANCE

Email:

customersupport@exar.com

powertechsupport@exar.com

Exar Technical Documentation:

http://www.exar.com/TechDoc/default.aspx?

EXAR CORPORATION

HEADQUARTERS AND SALES OFFICES

48720 Kato Road

Fremont, CA 94538 – USA

Tel.: +1 (510) 668-7000

Fax: +1 (510) 668-7030

www.exar.com

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve

design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a

user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,

is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in

writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all

such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

29/29

Rev. 1.0.1


型号：	V5EXT
厂家：	EXAR CORPORATION
描述：	Quad Channel Digital PWM/PFM Programmable Power Management System 四通道数字PWM / PFM可编程电源管理系统
文件：	总29页 (文件大小：1681K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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