XR-2212N [EXAR]
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| 型号： | XR-2212N |
| 厂家： | 
EXAR CORPORATION |
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XR-2212
Precision
Phase-Locked Loop
...the analog plus companyTM
October 2006
FEATURES
APPLICATIONS
D Quadrature VCO Outputs
D Frequency Synthesis
D Data Synchronization
D FM Detection
D Wide Frequency Range (0.01Hz to 300kHz)
D Wide Supply Voltage Range (4.5V to 20V)
D TTL/HCMOS Compatible (V = 5VDC)
D Tracking Filters
CC
D Wide Dynamic Range (2mV to 3Vrms)
D Adjustable Tracking Range ("1% to "80%)
D Excellent Temp. Stability 20ppm/°C, Typ.
D FSK Demodulation
GENERAL DESCRIPTION
The XR-2212 is an ultra-stable monolithic phase-locked
loop (PLL) system especially designed for data
communications and control system applications. Its on
board reference and uncommitted operational amplifier,
together with a typical temperature stability of better than
20ppm/°C, make it ideally suited for frequency synthesis,
FM detection, and tracking filter applications. The wide
input dynamic range, large operating voltage range, large
frequency range, and HCMOS and TTL compatibility
contribute to the usefulness and wide applicability of this
device.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
16 Lead 300 Mil CDIP
16 Lead 300 Mil PDIP
XR-2212M
-55°C to +125°C
0°C to +70°C
XR-2212CP
BLOCK DIAGRAM
V
GND
4
CC
1
Pre Amplifier
2
INP
Phase
Detector
0-DET O
10
16
14
0-DET I
TIM C1
15 VCOQO
VCOOC
VCOOV
3
5
VCO
Amp
13
TIM C2
12
9
V
REF
11
TIM R
PINP
V
REF
8
6
Op Amp
OUT
7
NINP
COMP
Figure 1. XR-2212 Block Diagram
Rev. 2.10
E1979-2006
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-2212
PIN CONFIGURATION
VCC
INP
VCOOC
0-DET I
VCOQO
TIM C1
1
2
3
4
5
6
7
8
16
15
14
GND
13 TIM C2
12 TIM R
VREF
10 0-DET O
VCOOV
COMP
NINP
11
OUT
9
PINP
16 Lead PDIP, CDIP (0.300”)
PIN DESCRIPTION
Pin #
1
Symbol
VCC
Type Description
Positive Power Supply.
Receive Analog Input.
2
INP
I
3
VCOOC
GND
O
VCO Current Output.
4
Ground Pin.
5
VCOOV
COMP
NINP
O
I
VCO Voltage Source Output.
6
Uncommitted Amplifier, Frequency Compensation Input.
Inverted Input. Uncommitted amplifier.
7
I
8
OUT
O
I
Uncommitted Amplifier Output.
9
PINP
Positive Input. Uncommitted amplifier.
10
11
12
13
14
15
16
0-DET O
VREF
O
O
I
Phase Detector Output.
Internal Voltage Reference. The value of VREF is VCC /2 -650mV.
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
VCO Quadrature Output.
TIM R
TIM C2
TIM C1
VCOQO
0-DET I
I
I
O
I
Phase Detector Input.
Rev. 2.10
2
XR-2212
ELECTRICAL CHARACTERISTICS
Test Conditions: V = +12V, T = + 25°C, R = 30kW, C = 0.033mF, unless otherwise specified. See
CC
A
0
0
Figure 3 for component designation.
XR-2212M
XR-2212CP
Typ.
Parameter
Units
Conditions
Min.
Typ.
Max.
Min.
Max.
General Characteristics
Supply Voltage
4.5
15
10
4.5
15
12
V
Supply Current
6
6
mA
R0 > 10kW., See Figure 5
Oscillator Section
Frequency Accuracy
Frequency Stability
Temperature
+1
+3
+1
%
Deviation from f0 = 1/R0C0
R1 = R
+20
0.05
0.2
+50
+20
0.05
0.2
ppm/°C See Figure 9
Power Supply
0.5
%/V
%/V
kHz
Hz
VCC = 12 + 1V, See Figure 8
VCC = 5 + 0.5V, See Figure 8
R0 = 8.2kW, C0 = 400pF
R0 = 2MW, C0 = 50mF
Upper Frequency Limit
100
300
300
0.01
Lowest Practical Operating
Frequency
0.01
Timing Resistor, R0
Operating Range
See Figure 5
5
2000
100
5
2000
100
kW
kW
Recommended Range
Oscillator Outputs
Voltage Output
15
15
See Figure 8 and Figure 9
Measured at Pin 5
Positive Swing, VOH
Negative Swing, VOL
Current Sink Capability
Current Output
11
0.4
1
11
0.5
1
V
V
0.8
mA
Measured at Pin 3
Peak Current Swing
Output Impedance
Quadrature Output
Output Swing
100
150
1
150
1
mA
MW
Measured at Pin 15
Referenced to Pin 11
Measured at Pin 10
0.6
0.3
3
0.6
0.3
3
V
V
DC Level
Output Impedance
Loop Phase Detector Section
Peak Output Current
Output Offset Current
Output Impedance
Maximum Swing
kW
+150 +200 +300 +100 +200 +300
mA
mA
MW
V
+1
1
+2
1
+4
+5
+4
+5
Referenced to Pin 11
Note
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 2.10
3
XR-2212
ELECTRICAL CHARACTERISTICS (CONT’D)
XR-2212M
Parameter
XR-2212CP
Typ.
Units
Conditions
Min.
Typ.
Max.
Min.
Max.
Input Preamp Section
Input Impedance
Input Signal to Cause Limiting
Op Amp Section
Voltage Gain
Measured at Pin 2
20
2
20
2
kW
10
mV rms
55
70
0.1
+5
2
55
70
0.1
+5
2
dB
mA
RL = 5.1kW, RF = R
Input Bias Current
Offset Voltage
1
1
+20
+20
mV
Slew Rate
V/msec
Internal Reference
Voltage Level
Measured at Pin 11
AC Small Signal
4.9
5.3
100
80
5.7
4.75
5.3
100
80
5.85
V
W
Output Impedance
Maximum Source Current
WA
Note
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation:
Ceramic Package: . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above T = + 25°C . . . . . . . . 6mW/°C
A
Plastic Package: . . . . . . . . . . . . . . . . . . . . . . . . 625mW
Derate Above T = + 25°C . . . . . . . . 5mW/°C
A
SYSTEM DESCRIPTION
The XR-2212 is a complete PLL system with buffered
inputs and outputs, an internal reference, and an
uncommitted op amp. Two VCO outputs are pinned out;
one sources current, the other sources voltage. This
enables operation as a frequency synthesizer using an
external programmable divider. The op amp section can
be used as an audio preamplifier for FM detection or as a
high speed sense amplifier (comparator) for FSK
demodulation. The center frequency, bandwidth, and
tracking range of the PLL are controlled independently by
external components. The PLL output is directly
compatible with CMOS, HCMOS and TTL logic families
as well as microprocessor peripheral systems.
The precision PLL system operates over a supply voltage
range of 4.5V to 20V, a frequency range of 0.01Hz to
300kHz, and accepts input signals in the range of 2mV to
3V rms. Temperature stability of the VCO is typically
better than 20 ppm/°C with the optimum timing resistor
value.
Rev. 2.10
4
XR-2212
Loop
Filter
Pre
Amp
+
Signal
Input
Phase
Detector
-
Op Amp
0-DET
Input
AMP
VCO
Voltage
Output
VCO
Phase
Quadrature
VCO
Current
Output
Output
Figure 2. Functional Block Diagram of XR-2212 Precision PLL System
V
CC
R
L
6
5.6K
2
10
9
7
C
O
Phase
Detector
8
Demod
Output
0.1mF
C
1
Input
Signal
R
F
16
R
C
11
0.1mF
R
3
Internal
Reference
0.1mF
R
1
5
12
%N
VCO
R
0
External
Divider
(Optional)
14
13
C
O
Figure 3. Generalized Circuit Connection for FM Detection, Signal
Tracking or Frequency Synthesis
Rev. 2.10
5
XR-2212
Phase
Detector
Input
1
Vcc
Loop
Phase
Detector
Output
Reference
Output
Voltage
16
10
11
Signal
Input
2
30K
30K
Input Preamplifier
2K
Phase Detector
Internal Voltage Reference
2K
VCO
Out
Non
Inv
Inp
Amp
Out
8
A
A1
Timing
Capacitor
5
9
3
C
Inv
Inp
0
13
14
VCO
Quad
Out
5K
5K
5K
5K
VCO
Current
Output
A
A1
7
15
6
Comp
Op Amp
4
GND
Timing
Resistor
12
R
O
Figure 4. Simplified Circuit Schematic of XR-2212
Rev. 2.10
6
XR-2212
TYPICAL CHARACTERISTICS
20
15
10
R =5kW
0
R =10kW
0
R = 5K
L
R = 10K
L
R =20kW
0
10
5
0.1
R > 100K
L
R =40kW
0
R =80kW
0
R =160kW
0
0
0.01
4
6
8
10 12 14 16 18 20 22 24
Supply Voltage V (V)
100
1000
f (Hz)
10,000
CC
0
Figure 5. Typical Supply Current vs.
Figure 6. VCO Frequency vs.
Timing Resistor
V
CC
(Logic Outputs Open Circuited)
1000
1.02
C =0.001mF
0
f = 1kHz
0
5
1
5
R > 10R
0
1.01
1.00
4
C =0.0033mF
2
0
3
C =0.01mF
0
4
3
100
C =0.033mF
0
CURVE
R
0.99
0.98
0
1
2
3
5K
10K
30K
2
C =0.1mF
0
4
5
100K
300K
1
C =0.33mF
0
0.97
10
4
6
8
10
12 14
(V)
16
18
20
22 24
0
1000
f (Hz)
10,000
V
CC
0
Figure 7. VCO Frequency vs.
Timing Capacitor
Figure 8. Typical f vs. Power
0
Supply Characteristics
Rev. 2.10
7
XR-2212
+1.0
+0.5
1MΩ
R =10K
0
500K
R =50K
0
0
-0.5
-1.0
50K
10K
R =500K
0
V
=12V
CC
1
R =1MΩ
0
R =12R
f =1kHz
0
0
-50
-25
0
25
50
75
100
125
Temperature (C)
Figure 9. Typical Center Frequency Drift vs. Temperature
DESCRIPTION OF CIRCUIT CONTROLS
Signal Input(Pin 2): Signal is AC coupled to this terminal.
The internal impedance at Pin 2 is 20kW. Recommended
input signal level is in the range of 10mV to 5V
peak-to-peak.
Op Amp Output (Pin 8): The op amp output is an open-
collector type gain stage and requires a pull-up resistor,
R , toV forproperoperation. Formostapplications, the
L
CC
recommended value of R is in 5kW to 10kW range.
L
Phase Detector Output (Pin 10): This terminal provides
a high-impedance output for the loop phase-detector. The
VCO Current Output (Pin 3): This is a high impedance
(MW) current output terminal which can provide +100mA
PLL loop filter is formed by R and C connected to Pin 10
1
1
drive capability with a voltage swing equal to V . This
CC
(see Figure 3). With no input signal, or with no
phase-error within the PLL, the DC level at Pin 10 is very
output can directly interface with CMOS or NMOS logic
families.
nearly equal to V . The peak voltage swing available at
REF
the phase detector output is equal to $V
.
VCO Voltage Output (Pin 5): This terminal provides a
low- impedance (ꢀ 50W) buffered output for the VCO. It
can directly interface with low-power Schottley TTL. For
interfacing with standard TTL circuits, a 750W pull-down
resistor from Pin 5 to ground is required. For operation of
the PLL without an external divider, Pin 5 can be DC
coupled to Pin 16.
REF
Reference Voltage, V
(Pin 11): This pin is internally
REF
biased at the reference voltage level. V
:V
= V /2
REF REF CC
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at Pins 10, 12 and 16. Pin
1 must be bypassed to ground with a 0.1mF capacitor, for
proper operation of the circuit.
VCO Control Input (Pin 12): VCO free-running
frequencies determined by external timing resistor, R ,
connected from this terminal to ground. For optimum
Op Amp Compensation (Pin 6): The op amp section is
frequency compensated by connecting an external
capacitor from Pin 6 to the amplifier output (Pin 8). For
0
temperature stability, R must be in the range of 10KW to
0
100kW (see Figure 9).
unity-gain compensation
recommended.
a
20pF capacitor is
VCO Frequency Adjustment: VCO can be fine-tuned
by connecting a potentiometer, R , in series with R at Pin
X
0
Op Amp Inputs (Pins 7 and 9): These are the inverting
and the non-inverting inputs for the op amp section. The
common-mode range of the op amp inputs is from +1V to
12 (see Figure 11).
This terminal is a low-impedance point, and is internally
biased at a DC level equal to V . The maximum timing
(V - 1.5) volts.
CC
REF
Rev. 2.10
8
XR-2212
current drawn from Pin 12 must be limited to <3 mA for
proper operation of the circuit.
is connected to this pin. The DC level of the sensing
threshold for the phase detector is referenced to V . If
REF
the signal is capacitively coupled to Pin 16, then this pin
must be biased from Pin 11, through an external resistor,
VCOTimingCapacitor(Pins13and14):VCOfrequency
is inversely proportional to the external timing capacitor,
R (R [ 10kW). The peak voltage swing applied to Pin
B
B
C , connected across these terminals (see Figure 6). C
0
0
16 must not exceed (V - 1.5) volts.
CC
must be nonpolar, and in the range of 200pF to 10mF.
VCO Quadrature Output (Pin 15): The low-level ([
0.6Vpp) output at this pin is at quadrature phase (i.e. 90°
phase-offset) with the other VCO outputs at Pins 3 and 5.
The DC level at Pin 15 is approximately 300mV above
PHASE-LOCKED LOOP PARAMETERS
Transfer Characteristics
V
. The quadrature output can be used with an external
REF
Figure 10 shows the basic frequency to voltage
characteristics of XR-2212. With no input signal present,
filtered phase detector output voltage is approximately
multiplier as a “lock detect” circuit. In order not to degrade
oscillator performance, the output at Pin 15 must be
buffered with an external high impedance low
capacitance amplifier. When not in use, Pin 15 should be
left open-circuited.
equal to the internal reference voltage, V
at Pin 11.
REF
The PLL can track an input signal over its tracking
bandwidth, shown in the figure. The frequencies f and
TL
Phase Detector Input (Pin 16): Voltage output of the
f
TH
represent the lower and the upper edge of the tracking
VCO (Pin 5) or the output of an external frequency divider
range, f represents the VCO center frequency.
0
Tracking
Bandwidth
2V
R
Df
Df
V
R
0
f
TL
f
O
f
TH
Frequency
Input Signal Frequency
Figure 10. Phase Detector Output Voltage (Pin 10) as a Function of Input Signal Frequency
Note
Output Voltage is Referenced to Internal Reference Voltage VREF at Pin 11
Rev. 2.10
9
XR-2212
Design Equations
8. Total Loop Gain, K
T
(See Figure 3 and Figure 10 for definition of
components.)
K = 2pK K = 4/C R rad/sec/volt
O
T
0
0 1
9. Peak Phase-Detector Current, I ; available at Pin 10.
A
1. VCO Center Frequency, f : f = 1/R C Hz
I = V
A
(volts)/25mA
REF
0
0
0 0
2. Internal Reference Voltage, V
Pin 11)
(measured at
REF
APPLICATION INFORMATION
FM Demodulation
V
REF
= V /2 - 650mV
CC
3. Loop Low-Pass Filter Time Constant, t : t = R C
1
1
4. Loop Damping, j:
XR-2212can be used as a linear FM demodulator for both
narrow-band and wide-band FM signals. The generalized
circuit connection for this application is shown in
Figure 11, where the VCO output (Pin 5) is directly
connected to the phase detector input (Pin 16). The
demodulated signal is obtained at phase detector output
(Pin 10). In the circuit connection of Figure 10, the op amp
section of XR-2212 is used as a buffer amplifier to provide
both additional voltage amplification as well as current
drive capability. Thus, the demodulated output signal
availableat the op amp output (Pin 8) is fully buffered from
the rest of the circuit.
NC0
C1
Ǹ
j + 0.25
where N is the external frequency divider modular
(See 2). If no divider is used, N = 1.
5. Loop Tracking Bandwidth, $Df/f : Df/f = R /R
1
0
0
0
6. Phase Detector Conversion Gain, K : (K is the
O
O
differentialDCvoltageacrossPins10and11, perunit
of phase error at phase-detector input)
K = -2V
/p volts/radian
O
REF
7. VCO Conversion Gain, K : (K is the amount of
0
0
change in VCO frequency, per unit of DC voltage
change at Pin 10. It is the reciprocal of the slope of
conversion characteristics shown in Figure 10).
In the circuit of Figure 11, R C set the VCO center
0 0
frequency, R sets the tracking bandwidth, C sets the
1
1
low-pass filter time constant. Op amp feedback resistors
R and R set the voltage gain of the amplifier section.
K = -1/V
C R Hz/V
REF 0 1
0
F
C
Rev. 2.10
10
XR-2212
V
CC
0.1mF
1
V
CC
6
8
R
5K
L
30pF
2
10
9
7
Phase
Demod
Output
Detector
0.1mF
C
1
R
FM
F
Input
16
4
R
C
11
Internal
Reference
0.1mF
R
1
5
12
VCO
R
0
14
13
C
O
Rx Fine Tune
Figure 11. Circuit Connection for FM Demodulation
Design Instructions
d) Choose R to determine the tracking bandwidth, Df
1
(see design equation 5). The tracking bandwidth, Df,
should be set significantly wider than the maximum
The circuit of Figure 11 can be tailored to any FM
demodulation application by a choice of the external
input FM signal deviation, Df . Assuming the
SM
components R , R , R , R , C and C . For a given FM
0
1
C
F
0
1
tracking bandwidth to be “N” times larger than
center frequency and frequency deviation, the choice of
these components can be calculated as follows, using the
design equations and definitions given on page 10.
Df , one can re-unite design equation 5 as:
SM
DfSM
f0
R0
R1
a) Choose VCO center frequency f to be the same as
Df
f0
0
+
+ N
FM carrier frequency.
b) Choose value of timing resistor R , to be in the range
0
of 10kW to 100kW. This choice is arbitrary. The
Table 2. lists recommended values of N, for various
values of the maximum deviation of the input FM
signal.
recommended value is R +ꢀ 20kW. The final value
0
of R is normally fine-tuned with the series
0
potentiometer, R .
X
c) CalculatevalueofC fromdesignequation(1)orfrom
0
e) Calculate C to set loop damping (see design
1
Figure 7:
equation 4). Normally, ς = 1/2 is recommended.
C = 1/R f
Then, C = C /4 for ς = 1/2.
1 0
0
0 0
Rev. 2.10
11
XR-2212
R /R = (3)(0.0746) = 0.224
or:
R = 89.3kW.
1
% Deviation of FM
Signal (DfSM/f0)
Recommended Value of
Bandwidth Ratio, N
0
1
(N = Df/DfSM
)
1% or less
1% to 3%
10
5
Step e): Calculate C1 = (C /4) = 186pF.
0
Step f): Calculate R and R to get $4V peak
C
F
1% to 5%
4
output swing: Let R = 100kW. Then,
F
5% to 10%
10% to 30%
30% to 50%
3
R = 80.6kW.
C
2
Note: All values except R0 can be rounded-off to nearest
1.5
standard value.
FREQUENCY SYNTHESIS
Table 2.
Figure 12 shows the generalized circuit connection for
frequency synthesis. In this application an external
frequency divider is connected between the VCO output
(Pin 5) and the phase-detector input (Pin 16). When the
circuit is in lock, the two signals going into the
Recommended values of bandwidth ratio, N, for various
values of FM signal frequency deviation. (Note: N is the
ratio of tracking bandwidth Df to max. signal frequency
deviation, Df ).
SM
phase-detector are at the same frequency, or f = f /N
S
1
f) Calculate R and R to set peak output signal
C
F
where N is the modulus of the external frequency divider.
Conversely, the VCO output frequency, f is equal to N .
amplitude. Output signal amplitude, V , is given
OUT
as:
1
fS
In the circuit configuration of Figure 12, the external
timing components, R and C , set the VCO free running
DfSM
f0
R1
R0
ǒRC ) RF
RC
Ǔ
ǒ Ǔ ǒ Ǔ
)
VREF
(
VOUT +
0
0
frequency; R sets the tracking bandwidth and C setsthe
1
1
loop damping, i.e., the low-pass filter time constant (see
design equations).
In most applications, R = 100kW is recommended;
F
then R , can be calculated from the above equation
C
The total tracking range of the PLL (see Figure 10),
should be chosen to accommodate the lowest and the
togivedesiredoutputswing. Theoutputamplifiercan
alsobeusedasaunity-gainvoltagefollower, byopen
circuiting R (i.e., R = ∞).
highest frequency, f
and f , to be synthesized. A
min
max
C
C
recommended choice for most applications is to choose a
tracking half-bandwidth Df, such that:
Note: All calculated component values except R0 can be
rounded-offtothenearest standard value, andR canbe
0
Df ꢀ f
- f
varied to fine-tune center frequency, through a series
potentiometer, RX, (See Figure 11).
max min
If a variable input frequency and a variable counter
modulus N is used, then the maximum and the minimum
values of output frequency will be:
Design Example
f
= N
(f )
and f
= N (f )
min S min
max
max S max
min
Demodulator for FM signal with 67kHz carrier frequency
with $5kHz frequency deviation. Supply voltage is +12V
and required peak output swing is $4V.
If a fixed output frequency is desired, i.e. N and f are
S
fixed, then a $10% tracking bandwidth is recommended.
Excessively large tracking bandwidth may cause the PLL
tolockontheharmonicsoftheinputsignals;andthesmall
tracking range increases the “lock-up” or acquisition time.
Step a) f is chosen as 67kHz.
0
Step b) Choose R = 20kW (18kW fixed resistor in
0
series with 5kW potentiometer).
Design Instructions
Step c) Calculate C ; from design equation (1).
0
C = 746pF
For a given performance requirement, the circuit of
Figure 12 can be optimized as follows:
0
Step d) Calculate R . For given FM deviation,
1
Df /f = 0.0746, and N = 3 from Table 2.
SM 0
a) Choose centerfrequency, f , tobeequaltotheoutput
0
Then:
frequency to be synthesized. If a range of output
Rev. 2.10
12
XR-2212
frequencies is desired, set f to be at mid-point of the
If a single fixed output frequency is desired, set R to
0
1
desired range.
get:
b) Choose timing resistor R to be in the range of 15kW
0
Df = 0.1 f
0
to 100kW. This choice is arbitrary. R can be fine
0
e) Calculate C to obtain desired loop damping. (See
tuned with a series potentiometer, R .
1
X
design equation 4). For most applications, ς = 1/2 is
recommended, thus:
c) Choose timing capacitor, C from Figure 7 or
0
Equation 1.
C = NC /4
0
0
d) Calculate R to set tracking bandwidth (see
1
Figure 10 and design equation 5). If a range of output
Note
frequencies are desired, set R to get:
1
All component values except R0 can be rounded off to the
nearest standard value.
Df = f
- f
max min
V
CC
0.1mF
1
6
8
V
CC
2
10
9
7
Phase
Detector
0.1mF
C
Input
1
Signal
16
4
74LS90
11
Internal
Reference
or
%N
Similar
0.1mF
F = F1/N
O
Output
R
R
1
0
5
12
VCO
F1 = Nfs
14
13
1K
C
O
Figure 12. Circuit Connection for Frequency Synthesizer
Rev. 2.10
13
XR-2212
INPUT SENSITIVITY
The input to the XR-2212 may sometimes be too sensitive
to noise conditions on the input line. Figure 13 illustrates
a method of de-sensitizing the XR-2212 from such noisy
lineconditionsbytheuseofaresistor, Rx, connectedfrom
pin 2 to ground. The value of Rx is chosen by the equation
and the desired minimum signal threshold level.
VIN minimum (peak) + Va–Vb +
20, 000
(20, 000 ) RX)
DV " 2.8V offset + VREF +
or
ǒVREF
DV
Ǔ
* 1
RX + 20, 000
V
IN
minimum (peak) input voltage must exceed this value
to be detected (equivalent to adjusting V threshold).
Vcc
To Phase
Detector
Va
Vb
Input
2
20K
20K
Rx
11
V
REF
Figure 13. Desensitizing Input Stage
Rev. 2.10
14
XR-2212
16 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
16
9
8
1
E
E
1
D
A
1
Base
Plane
A
Seating
Plane
L
e
c
B
B
1
α
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.100
0.015
0.014
0.045
0.008
0.740
0.250
0.200
0.060
0.026
0.065
0.018
0.840
0.310
2.54
0.38
0.36
1.14
0.20
18.80
6.35
5.08
1.52
0.66
1.65
0.46
21.34
7.87
A
B
B
c
1
1
D
E
E
e
L
1
0.300 BSC
0.100 BSC
7.62 BSC
2.54 BSC
0.125
0.200
3.18
5.08
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 2.10
15
XR-2212
16 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
9
8
16
1
E
1
E
D
A
2
A
L
Seating
Plane
C
α
A
1
B
e
B
e
A
B
1
e
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.015
0.115
0.014
0.030
0.008
0.745
0.300
0.240
0.210
0.070
0.195
0.024
0.070
0.014
0.840
0.325
0.280
3.68
0.38
2.92
0.36
0.76
0.20
5.33
1.78
4.95
0.56
1.78
0.38
21.34
8.26
7.11
A
A
B
B
1
2
1
C
D
E
18.92
7.62
6.10
E
e
1
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
e
A
e
B
L
α
0.310
0.430
0.160
15°
7.87
10.92
4.06
15°
0.115
2.92
0°
0°
Note: The control dimension is the inch column
Rev. 2.10
16
XR-2212
Notes
Rev. 2.10
17
XR-2212
Notes
Rev. 2.10
18
XR-2212
Notes
Rev. 2.10
19
XR-2212
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1979-2006 EXAR Corporation
Datasheet October 2006
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.10
20
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