XR-T6165IP [EXAR]
Codirectional Digital Data Processor; 同向数字数据处理器
| 型号： | XR-T6165IP |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Codirectional Digital Data Processor |
| 文件： | 总16页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-T6165
Codirectional Digital
Data Processor
...the analog plus companyTM
May 1997–3
FEATURES
APPLICATIONS
D Low Power CMOS Technology
D CCITT G.703 Compliant 64kbps Codirectional
Interface
D All Receiver and Transmitter Inputs and Outputs are
TTL Compatible
D Performs the Digital and Analog Functions for a
Complete 64kbps Data Adaption Unit (DAU) When
Used With the XR-T6164
D Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions
D Alarm Output Indicates Loss of Received Bipolar
Violations
D Up to 125µs Variance of Data Transfer Timing in
Both Transmit and Receive Paths Allows Operation
in Plesiochronous Networks
D Both Receiver and Transmitter Perform Byte
Insertion or Deletion in Response to Local Clock
Slips
GENERAL DESCRIPTION
The XR-T6165 is a CMOS device which contains the
digital circuitry necessary to interface both directions of a
64kbps data stream to 2.048Mbps transmit and receive
PCM time-slots. The XR-T6165 and the companion
XR-T6164 line interface chip together form a CCITT
G.703 compliant 64kbps codirectional interface.
sections. The transmitter transforms 8 bit serial data from
a 2.048Mbps time-slot into an encoded 64kbps data
stream. The receiver, which performs the reverse
operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps
time-slot. The XR-T6165 provides features which allow
the repetitions and deletions of both received and
transmitted data as clock skews and transients occur.
The XR-T6165 contains separate transmit and receive
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
22 Lead 400 Mil PDIP
XR-T6165CP
XR-T6165IP
XR-T6165CD
XR-T6165ID
0°C to +70°C
–40°C to +85°C
0°C to +70°C
22 Lead 400 Mil PDIP
24 Lead 300 Mil JEDEC SOIC
24 Lead 300 Mil JEDEC SOIC
–40°C to +85°C
Rev. 2.02
E1990
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7010
1
XR-T6165
1
(17)
15
16
8
PCMIN
TX2MHz
TS1T
D
1
8 Bit Input Register
(18)
CLK
Byte
Deletion
8
8 Bit Latch
Time
Slot
Mux
9
TS2T
LOAD
CLK
Byte
Insertion
8
1
(14)
12
TTSEL
8 Bit Output Register
LOAD
Q
Control
Circuitry
1
1
(16)
14
13
D
CLK
TX256kHz
ALARMIN
Octet
Counter
Violation
Insertion
Coding
Logic
T+R
T-R
10
11
Q
(15)
D
CLK
Q
Note
1
Number in brackets are for SOIC package
Figure 1. XR-T6165 Transmit Section Block Diagram
Byte Sync
Violation
1
(24)
22
Detection
CLK
Loss
ALARM
Alarm
S+R
S-R
1
2
Data
Decoder
CLK
BLS
3
4
D
Q
Q
1
(23)
21
8 Bit Reg 0
PCMOUT
RX2MHz
TS1R
Register
Select
Logic
CLK
1
(20)
18
D
8 Bit Reg 1
Time
Slot
Mux
1
CLK
REG 0 SEL
(21)
(22)
19
TS2R
RTSEL 20
REG 1 SEL
Time Slot
1
128kHz Recovered CLK
5
BLANK
Clock
Recovery
RXCK2MHz
7
Note
1
Number in brackets are for SOIC package
Figure 2. XR-T6165 Receiver Section Block Diagram
Rev. 2.02
2
XR-T6165
PIN CONFIGURATION
S+R
ALARM
1
24
1
22
21
20
19
18
17
16
15
14
13
12
S+R
S-R
BLS
ALARM
PCMOUT
PCMOUT
RTSEL
TS2R
TS1R
VSS
TX2MHz
PCMIN
TX256kHz
ALARMIN
TTSEL
2
3
23
22
21
20
19
18
17
16
15
S-R
BLS
RX2MHz
BLANK
VDD
2
3
RTSEL
TS2R
TS1R
4
4
RX2MHz
BLANK
5
5
6
6
VDD
VSS
TX2MHz
PCMIN
7
RXCK2MHz
7
RXCK2MHz
8
TS1T
TS2T
T+R
T-R
8
TS1T
TS2T
9
9
TX256kHz
ALARMIN
TTSEL
10
T+R 10
11
12
14
13
11
T-R
NC
NC
22 Lead PDIP (0.400”)
24 Lead SOIC (JEDEC, 0.300”)
PIN DESCRIPTION
DIP
Pin #
SOIC
Pin #
Symbol
S+R
Type Description
1
2
3
1
2
3
I
I
I
Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side.
Active low.
S-R
Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side.
Active low.
BLS
Byte Locking Supervision. When active, causes blanking of PCMOUT under
received alarm conditions. Active low.
4
5
4
5
RX2MHz
BLANK
I
I
Receiver 2.048MHz Clock. Used to clock out PCM data.
PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS).
Active high.
6
7
6
7
VDD
RXCK2MHz
TS1T
+5V +10% Power Source.
I
I
2.048MHz Clock. Used by receiver clock recovery circuit.
Transmitter time-slot 1 Input.
8
8
9
9
TS2T
I
Transmitter time-slot 2 Input.
10
10
T+R
O
Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input.
Active low
11
11
T-R
O
Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input.
Active low.
12
13
14
NC
NC
No Connect.
No Connect.
12
13
14
TTSEL
I
I
I
Transmit time-slot Select. When high, TS1T is selected; when low, TS2T is
selected.
15
16
ALARMIN
TX256kHz
Alarm Input. When active, inhibits insertion of violations used for octet timing in
transmitter output. Active high
Transmitter 256kHz Clock. Used to output 64kbps encoded data.
Rev. 2.02
3
XR-T6165
PIN DESCRIPTION (CONT’D)
DIP
Pin #
SOIC
Pin #
Symbol
Type Description
15
16
17
18
19
20
17
18
19
20
21
22
PCMIN
TX2MHz
VSS
I
I
Transmit PCM Input. Data read from the system PCM bus.
Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN.
Ground.
TS1R
I
I
I
Receiver time-slot 1 Input.
TS2R
Receiver time-slot 2 Input.
RTSEL
Receive time-slot Select. When high, TS1R is selected; when low, TS2R is se-
lected.
21
22
23
24
PCMOUT
ALARM
O
O
Received PCM Output Data. Data sent to the system PCM bus.
Octet Timing Alarm. When active, indicates loss of received bipolar violations that
are used for octet timing. Active high.
Rev. 2.02
4
XR-T6165
ELECTRICAL CHARACTERISTICS
Test Conditions: V = 5V + 10%, T = 25°C, Unless Otherwise Specified
DD
A
Symbol
Parameter
Min.
2.4
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
VIH
VIL
Logic 1
V
V
Logic 0
0.4
5.5
VDD
IDD
IIL
Supply
4.5
V
Supply Current
Input Leakage
500
µA
µA
V
Dynamic Supply Current
1
VOL
VOH
0.4
At 1.6mA
At 0.4mA
2.4
V
AC Electrical Characteristics
General
tr, tf
Receiver
tRS
Output Rise/Fall Time
20
ns
All Outputs
RX2MHz Rising Edge to TS
Rising Edge Set Up Time
0
0
tRXL -
100
ns
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
tRH
RX2MHz Rising Edge to TS
Falling Edge Hold Time
tRXL -
100
tDRS
tDRH
tRXD
TS Rising Edge to Leading Edge
of PCMOUT D0 Bit Delay
10
10
10
TS Falling Edge to Trailing Edge
of PCMOUT D7 Bit Hold Time
0
RX2MHz Rising Edge to
PCMOUT Bits D1 Through D6
Rising Edge Delay
tPW
tRXH
PCMOUT Pulse Width
RX2MHz High Time
RX2MHz Low Time
RX2MHz Period
488
244
244
488
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
+100ppm
tRXL
tRXCLK
Transmitter
tTS
TS Rising Edge to TX2MHz Set
Up Time
20
0
tTXL -
100
ns
ns
ns
ns
ns
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
tTH
tDS
TS Falling Edge to TX2MHz Hold
Time
tTXL -
100
PCMIN Edge to TX2MHz Set Up
Time
100
100
tDH
PCMIN Edge to TX2MHz Hold
Time
tTXH
TX2MHz High Time
244
Rev. 2.02
5
XR-T6165
ELECTRICAL CHARACTERISTICS (CONT’D)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
AC Electrical Characteristics (Cont’d)
Transmitter (Cont’d)
tTXL
tTXCLK
tKXH
TX2MHz Low Time
TX2MHz Period
244
488
ns
ns
µs
µs
µs
Figure 4
Figure 4
TX256kHz High Time
TX256kHz Low Time
TX256kHz Period
1.95
tKXL
1.95
tKXCLK
3.9063
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Magnetic Supplier Information:
Pulse
Transpower Technologies, Inc.
24 Highway 28, Suite 202
Crystal Bay, NV 89402-0187
Tel. (702) 831-0140
Telecom Product Group
P.O. Box 12235
San Diego, CA 92112
Tel. (619)674-8100
Fax. (619)674-8262
Fax. (702) 831-3521
Rev. 2.02
6
XR-T6165
tRS
tRXCLK
tRH
tRXL
tRXH
RX2MHz
tDRS
tDRH
time-slot
tPW
D2
tRXD
PCMOUT
D0
D1
D3
D4
D5
D6
D7
Figure 3. Receive Time-slot Timing
tTS
tTXH
tTXL
tTH
tTXCLK
TX2MHz
time-slot
tDS
tDH
PCMIN
D0
D1
D2
D3
D4
D5
D6
D7
Figure 4. Transmit Time-slot Timing
tKXCLK
tKXH
tKXL
Tr
Tf
V
IH
V
IH
50%
50%
50%
V
IL
V
IL
Clock
Figure 5. Clock Timing
Rev. 2.02
7
XR-T6165
SYSTEM DESCRIPTION
Transmitter
transmitter output as specified by CCITT G.703.
Transmission of octet timing is performed by feeding the
seventh and eighth data bits in each word to the same
transmitter output. This function may be inhibited by
setting ALARMIN (pin 13) high to transmit an alarm
condition. Should skew occur between the TX2MHz and
TX256kHz clocks signals, or during an adjustment of the
timing of the time-slot signal, circuitry is included to delete
or repeat complete words of data. This could happen, for
example, when changing from one time-slot position to
another. A byte repetition or insertion occurs once if no
new PCM data is received. A byte repetition just occurs
once. If no new PCM data is received, the T+R and T-R
outputs stay high. A byte deletion occurs when the
transmitter receives a new byte of data before the
previous byte is transferred from the storage latch to the
output register. Under this condition, the stored data is
overwritten.
Figure 1 shows the XR-T6165 transmitter section block
diagram. The transmitter converts eight bit bursts or
octets of 2.048Mbps serial data present in a PCM
time-slot to a coded continuous 64kbps data stream.
During operation, data input is controlled by external
clock and time-slot signals, and the 64kbps data output is
timed by an external 256kHz clock. Since the input and
output rates may not be exactly equal because of slight
clock rate differences, periodic slips can occur.
Therefore, circuitryisincludedtodeleteorrepeatoctets, if
necessary. Transmitter operation is as follows. Pin
numbers, refer to the DIP package.
PCM data is applied to PCMIN (pin 15), a 2.048MHz local
clock is applied to TX2MHz (pin 16), and a time-slot signal
is applied through the time-slot multiplexer. This
multiplexer allows the transmitter to be hard wired to two
time-slot positions. A time-slot signal is applied to
multiplexer inputs TS1T (pin 8) or TS2T (pin 9), and a
time-slot select logic level is applied to TTSEL (pin 12). A
high level at TTSEL selects TS1T while a low level
enables TS2T. The time-slot is an envelope derived
externally from TX2MHz that covers eight clock pulses.
The rising edge of the time-slot signal should be made to
coincide with the falling edge of TX2MHz. Eight bits of
PCM data are clocked into the transmitter input register
on the rising edge of TX2MHz while the selected time-slot
signal is high. The input register data is then transferred
to a storage latch.
Receiver
Figure 2 shows the block diagram of the XR-T6165
receiver section.
The receiver converts coded
continuous 64kbps data to eight bit bursts of 2.048Mbps
serial data suitable for insertion in a PCM time-slot.
During operation, data input is timed by a clock that is
extracted from the input signal, while output is controlled
by external locally supplied clock and time-slot signals.
Since the data input and output rates may not be exactly
equal, circuitryisincludedtodeleteorrepeateightbitdata
blocks, if necessary. Receiver operation is as follows.
A line interface chip such as the receive section of the
XR-T6164 converts the encoded bipolar 64kbps signal to
dual-rail active-low logic levels. These signals are
applied to the XR-T6165 receiver S+R (pin 1) and S-R
(pin 2) inputs. A 128kHz clock, which is derived from the
received signal, is used to decode this data, and then to
clock it into one of two storage registers. Two registers
are used so that one may be receiving continuous data at
64kbps while the other is sending eight bit bursts at a
2.048Mbps rate to PCMOUT (pin 21) while the receiver
time-slot signal is high. The time-slot is an envelope
derived externally from RX2MHz that covers eight clock
pulses. The rising edge of the time-slot signal should be
made to coincide with the rising edge of RX2MHz. Eight
bits of PCM data are clocked out of the receiver register
on the rising edge of RX2MHz while the time-slot signal is
high. A two input multiplexer at the time-slot input allows
the receiver to be hard wired to two time-slot positions.
Transmission of 64kbps data is controlled by the 256kHz
local clock that is applied to TX256kHz (pin 14). It is not
necessary for this clock to be synchronized with any other
signals that are applied to the transmitter. The output
process begins by transferring data from the storage latch
to the output shift register after transmission of the
previous eight bits of data is complete. Four periods of
TX256kHz are required to encode each data bit. A “logic
0” applied to PCMIN is coded as 0101 while a “logic 1” is
coded as 0011. This data is output on either T+R (pin 10)
or T-R (pin 11) according to the AMI (alternate mark
inversion) coding rule. Note that the T+R and T-R outputs
as well as the corresponding XR-T6164 transmitterinputs
(TX+I/P, TX-I/P) are all active-low. Therefore, a “logic 0”
is coded as a 1010 and a “logic 1” as a 1100 at the bipolar
Rev. 2.02
8
XR-T6165
time-slot signals are applied to TS1R (pin 18) and TS2R
(pin 19) and the active time-slot is selected by RTSEL (pin
20). A high level applied to RTSEL selects TS1R and a
low level selects TS2R. Data appearing at PCMOUT is
framed by the read time-slot signal and is guaranteed
glitch free.
Slip control logic is included in the receiver to
accommodate rate differences between input and output
data. The 64kbps input rate is determined by the remote
transmitter, while the PCMOUT rate is set by RX2MHz
which is a local clock. If this clock is slow, an octet will be
deleted periodically, while the last octet will be repeated
under fast conditions. Octet timing is maintained during
these operations.
Recovery of the 128kHz timing signal is performed by a
variablelengthcounterwhichisclockedbythe2.048MHz
signal applied to RXCK2MHz (pin 7). This clock is not
required to be synchronized with any other signals that
are applied to the XR-T6165. However, the RX2MHz
clock (pin 4) may also be used for this function. Positive
input data transitions are used tosynchronizethiscounter
with the data. If synchronization is lost, the counter length
is shortened, and the clock recovery circuit enters a seek
mode until a transition is found.
APPLICATION INFORMATION
64kbps Codirectional Interface
Figure 6 shows a codirectional interface circuit using the
XR-T6165 with the XR-T6164 line interface. The
XR-T6164 first converts the bipolar 64kbps transmit and
receive signals to active-low TTL compatible data
required by the XR-T6165. The XR-T6165 then performs
the digital functions that are necessary to interface this
64kbps continuous data to a 2.048Mbps PCM time-slot.
Octet timing ensures that bit grouping is maintained when
the data is converted from a 64kbps continuous stream to
eight bit 2.048Mbps bursts. Bipolar violations are used to
identifythelastbitineacheightbitoctet. Intheabsenceof
these violations, for example when receiving
a
transmitted alarm condition (transmitter ALARMIN is
high), the circuit will continue to operate in
synchronizationwith respect to the last received violation.
During this time, the data present at PCMOUT is still
correct as long as synchronization based on the last
received violation is still valid, and the BLS input (pin 3) is
held high. However, if BLS is low and an octet timing
violation is not received, receiver output data is blanked
by forcing PCMOUT to a high level. Also, if eight
successive octet timing violations are not received, the
ALARM output (pin 22) goes to a high level. A high level
applied to the BLANK input (pin 5) will also force
PCMOUT to an all-ones state.
The 64kbps signals that have been attenuated and
distorted
by
the
twisted
pair
cable
are
transformer-coupled to the line side of the XR-T6164 as
shown on the left side of Figure 6. A suggested
transformer for both the input and output applications is
the pulse type PE-65535.
TherightsideofFigure 6showstheXR-T6164LOS(Loss
of Signal) output and the XR-T6165 digital inputs and
outputs. All of these pins are TTL compatible. Please
refer to the pin description section of this data sheet for
detailed information about each signal.
Rev. 2.02
9
XR-T6165
T6164 LOS Output
+5V
+5V
XR-T6165
6
V
DD
0.1µF
22
21
0.1µF
ALARM
Loss of TX Sync
Data to PCM BUS
Blank O/P for Alarm
2.048MHz Clock
time-slot 1
PCMOUT
3
0.1µF
BLS
Receive RX2MHz
4
Side
9
13 15
3
64kbps Data
from Line
1:2
18
19
20
5
TS1R
V
V
C
C
A
T
C
M
C
O
N
R
12
5
1
2
16
S+R
S-R
S+R
S-R
C
C
RX+I/P
time-slot 2
TS2R
RTSEL
X
A
L
TIP
D
time-slot Select
Forces all Ones
2.048MHz Clock
480
A
R
M
BLANK
1
2
RING
RX-I/P
7
RXCK2MHz
I/P BIAS
PE-65535
TTI-17147
0.1µF
14
PEAK CAP
0.1µF
XR-T6164
64kbs Data
to Line
+5V
15
16
8
1:2
300
Data from PCM BUS
PCMIN
10
11
11
6
10
8
T+R
T-R
TIP
TX+O/P
TX-O/P
TX+I/P
TX-I/P
TX2MHz
2.048MHz Clock
time-slot 1
G
N
D
A
G
N
D
D
300
TS1T
Transmit
Side
RING
9
TS2T
time-slot 2
0.1µF
12
14
13
PE-65535
TTI-17147
TTSEL
TX256kHz
ALARMIN
4
7
time-slot Select
256kHz Clock
Inhibit Violations
17
V
SS
Figure 6. Typical Codirectional Application Circuit
Rev. 2.02
10
XR-T6165
Transmitter Code Conversion
Figure 7 shows the transmitter code conversion process
that CCITT G.703 specifies for a 64kbps codirectional
interface.
Step 3 - A binary 0 is coded as a 1010.
Step 4 - The binary signal is converted into a three-level
signal by alternating the polarity of consecutive blocks.
Step 1 - A 64kbps bit period is divided into four unit
intervals.
Step 5 - The alternation in polarity of the blocks is violated
every eighth block. The violation block marks the last bit
in an octet.
Step 2 - A binary 1 is coded as a 1100.
Bit Number
7
1
8
0
1
0
2
1
3
0
4
0
5
1
6
1
7
1
8
0
1
1
64kbps data
Steps 1-3
Step 4
Step 5
Violation
Violation
Octet Timing
Figure 7. Transmitter Code Conversion for a 64kbps Bipolar Line Signal
Rev. 2.02
11
XR-T6165
Codirectional Interface Pulse Masks
pulses respectively of either polarity. Note that this mask
is for the pulse measured at the XR-T6164 transmitter
output (application circuit shown in Figure 6) when
terminated with a 120Ω resistor.
Figure 8 and Figure 9 show the CCITT G.703 64kbps
codirectional interface pulse masks for single and double
V
1.0
3.12µs
(3.9 -0.78)
0.5
0
3.51µs
(3.9 -0.39)
3.9µs
4.29µs
(3.9 + 0.39)
6.5µs
(3.9 + 2.6)
7.8µs
(3.9 + 3.9)
Figure 8. Mask for a Single Pulse
V
1.0
7.02µs
(7.8 - 0.78)
0.5
0
7.41µs
(7.8 - 0.39)
7.8µs
8.19µs
(7.8 + 0.39)
10.4µs
(7.8 + 2.6)
11.7µs
(7.8 + 3.9)
Figure 9. Mask for Double Pulse
Rev. 2.02
12
XR-T6165
22 LEAD PLASTIC DUAL-IN-LINE
(400 MIL PDIP)
22
1
12
11
E
1
E
D
A
1
A
L
Seating
Plane
B
e
B
1
C
α
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A
B
B
0.145
0.015
0.014
0.030
0.008
1.050
0.390
0.330
0.210
0.070
0.024
0.070
0.016
1.120
0.425
0.380
3.68
0.38
0.36
0.76
0.20
26.67
9.91
8.38
5.33
1.78
1
0.56
1.78
1
C
D
E
0.38
28.45
10.80
9.65
E
e
L
1
0.100 BSC
2.54 BSC
0.115
0.160
2.92
4.06
α
0°
15°
0°
15°
Rev. 2.02
13
XR-T6165
24 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
D
24
13
E
H
12
C
A
Seating
Plane
e
B
A
1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
B
C
D
E
e
0.093
0.004
0.013
0.009
0.598
0.291
0.104
0.012
0.020
0.013
0.614
0.299
2.35
0.10
0.33
0.23
2.65
0.30
0.51
0.32
15.60
7.60
15.20
7.40
0.050 BSC
1.27 BSC
H
L
0.394
0.016
0.419
0.050
10.00
0.40
10.65
1.27
Rev. 2.02
14
XR-T6165
Notes
Rev. 2.02
15
XR-T6165
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1990 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.02
16
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