XR10910IL40TR-F [EXAR]
IC AFE 14BIT 16:1 I2C 40QFN;型号: | XR10910IL40TR-F |
厂家: | EXAR CORPORATION |
描述: | IC AFE 14BIT 16:1 I2C 40QFN |
文件: | 总22页 (文件大小:1030K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XR10910
16:1 Sensor Interface AFE
FEATURES
■■
General Description
Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA:
16:1 differential mux with I2C interface
Instrumentation amplifier
The XR1ꢀ91ꢀ is a unique sensor interface integrated circuit with an on-board
16:1 multiplexer, offset correction DAC, instrumentation amplifier and voltage
reference0 The XR1ꢀ91ꢀ is designed to integrate multiple bridge sensors
with a microcontroller (MCU) or field-programmable gate array (FPGA)0
LDO
Offset correction DAC with I2C interface
(±±6ꢀmꢁ offset correction range - RTI)
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors0 The DAC is controlled by an I2C compatible 2 wire serial
interface0The serial interface also provides the user with easy controls to the
XR1ꢀ91ꢀ’s many functions such as input and gain selection0
■■
Eight selectable voltage gains from 2ꢁ/ꢁ
to 76ꢀꢁ/ꢁ with only ±ꢀ0±5 gain error
1mꢁ maximum input offset voltage
1ꢀꢀpA maximum input bias current
■■
■■
■■
±±6μA maximum supply current
207ꢁ to ±ꢁ analog supply voltage range
108ꢁ to ±ꢁ digital supply voltage range
-4ꢀ˚C to +8±˚C temperature range
An integrated LDO provides a regulated voltage to power the input bridge
sensors and is selectable, between 3ꢁ and 206±ꢁ, via the serial interface
for lower voltage compatibility0 The LDO current can be sensed and a
proportional voltage present at the output of the IC for monitoring the LDO
current0
■■
■■
■■
■■
6mm x 6mm QFN-4ꢀ package
The XR1ꢀ91ꢀ offers 8 fixed gain settings (from 2ꢁ/ꢁ to 76ꢀꢁ/ꢁ), each with
an error of only ±ꢀ0±5, that are selectable via the I2C interface0 It also offers
less than 1mꢁ maximum input offset voltage, 1ꢀꢀpA maximum input bias
current, and 1ꢀꢀpA maximum input offset current0
APPLICATIONS
■■
Bridge sensor interface
■■
Pressure & temperature sensors
■■
Strain gauge amplifier
■■
Industrial process controls
The XR1ꢀ91ꢀ is designed to operate from 207ꢁ to ±ꢁ supplies and is specified
over the industrial temperature range of -4ꢀ°C to +8±°C0 It is offered in a
space saving 6mm x 6mm QFN-4ꢀ package0 It consumes less than ±±6μA
maximum supply current and offers a sleep mode for added power savings0
■■
Weigh scales
Ordering Information - back page
The low power, low input bias current and integrated features make the
XR1ꢀ91ꢀ well suited for both industrial and consumer applications using
bridge sensors0
Typical Application
m
DD
m
CC
6.8μF
+
6.8μF
+
2.5
2
ꢀ.1μF
mDD
ꢀ.1μF
BRDG
mCC
ꢀ.1μF
1ꢀk
BRIDGE 16
1.5
1
LDO
IN16+
IN16-
0.5
0
OUT
INA /
PGA
ADC
µC
1ꢀnF
16:1
MUX
±±6ꢀ0m
OFFSET TRIM
-0.5
-1
m
m
DD
DD
BRIDGE 1
1ꢀ-BIT
DAC
PGA
4.7k
4.7k
-1.5
-2
IN1+
IN1-
SDA
SCL
2
I C
CONTROL
-2.5
0
2
4
6
8
10
Time (sec)
XR10910
AGND
DGND
Figure 10 Typical Application
Figure 20 ꢀ01Hz to 1ꢀHz RTI ꢁoltage Noise
REV 1E
1/22
XR10910
Absolute Maximum Ratings
Operating Conditions
Analog Supply ꢁoltage Range 0000000000000000000000000000000000207ꢁ to ±02±ꢁ
Digital Supply ꢁoltage Range 000000000000000000000000000000000000107ꢁ to ±02±ꢁ
Operating Temperature Range 000000000000000000000000000000000-4ꢀ°C to 8±°C
Junction Temperature 000000000000000000000000000000000000000000000000000000000001±ꢀ°C
Storage Temperature Range00000000000000000000000000000000000-6±°C to 1±ꢀ°C
Lead Temperature (Soldering, 1ꢀs) 0000000000000000000000000000000000000026ꢀ°C
Stresses beyond the limits listed below may cause
permanent damage to the device0 Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime0
Analog Supply ꢁoltage (ꢁCC)00000000000000000000000000000000000000000ꢀꢁ to ±0±ꢁ
Digital Supply ꢁoltage (ꢁDD)000000000000000000000000000000000000000000ꢀꢁ to ±0±ꢁ
Digital Input/Output (ꢁDDIO)0000000000000000000000000000000000000000000ꢀꢁ to ±0±ꢁ
ꢁIN 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000ꢀ to ꢁCC
Differential Input ꢁoltage (current limit of 1ꢀmA)0000000000000000000000 ꢁCC
ESD Rating (HBM - Human Body Model)0000000000000000000000000000000004kꢁ
Package thermal resistance θJA 0000000000000000000000000000000000000000 32°C/W
NOTE:
1. JEDEC standard, multi-layer test boards, still air0
REV 1E
2/22
XR10910
Electrical Characteristics
T = 2±°C, ꢁ = 303ꢁ, ꢁ = 108ꢁ, R = 1ꢀkΩ to 10±ꢁ; G = 76ꢀ; unless otherwise noted0
A
CC
DD
L
Symbol
Parameter
Conditions
Min
-1
Typ
Max
Units
DC Performance
ꢁ
IO
Input offset voltage
Input referred
±ꢀ0ꢀ2
3
1
mꢁ
μꢁ/°C
pA
d
Input offset voltage average drift
Input bias current
Input offset current
Power supply rejection ratio
Gain = 2
ꢁIO
I
I
-1ꢀꢀ
-1ꢀꢀ
6ꢀ
1±
1ꢀꢀ
1ꢀꢀ
B
1
pA
OS
PSRR
Gain
ꢁ
CC
= 207ꢁ to ±ꢁ
91
dB
20ꢀ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
ꢁ/ꢁ
5
Gain = 2ꢀ
2ꢀ0ꢀ
4ꢀ0ꢀ
8ꢀ0ꢀ
1±ꢀ0ꢀ
29909
±9906
7±904
Gain = 4ꢀ
Gain = 8ꢀ
Nominal; refer to Gain Register Table (pg0 1ꢀ)
Gain = 1±ꢀ
Gain = 3ꢀꢀ
Gain = 6ꢀꢀ
Gain = 76ꢀ
G
Gain error
-ꢀ0±
ꢀ0±
E
Gain error vs temperature
±1ꢀ
43±
48
ppm/°C
μA
I
I
I
I
ꢁ
CC
supply current
No load to output; no load to LDO
±3ꢀ
±9
SꢁCC
Disable ꢁ supply current
No load to output; no load to LDO
μA
SꢁCCD
SꢁDD
CC
ꢁ
supply current
No load to output; no load to LDO; I2C running
22
26
μA
DD
Total supply current
No load to output; no load to LDO
4±7
4±
±±6
μA
STOTAL
No load to output; no load to LDO; LDO DIS
No load to output; no load to LDO; LDO EN
μA
I
Total disable supply current
SDTOTAL
7ꢀ
8±
μA
Input Characteristics
1ꢀ13 || 1102
Input impedance
Ω || pF
ꢁ
ꢀ023 to
30ꢀ6
CMIR
Common mode input range
Common mode rejection ratio
ꢀ0±
7±
20±
CMRR
Input referred0 ꢁ
= ꢀ0± to 20ꢀꢁ
88
dB
CM
Output Characteristics
ꢀ0ꢀ4 to
3029
ꢁ
Output voltage swing
R = 1ꢀkΩ to 10±ꢁ
ꢀ01
104
301
106
ꢁ
ꢁ
OUT
L
ꢁ
OO
Output offset
Offset DAC ꢀ ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ; G = 2
RTI (referred to input)
10±
Offset DAC
Offset DAC range
Offset monotonicity
±±6ꢀ
8
mꢁ
1ꢀ
Bits
LDO
10±k load, LDO bit LOW
10±k load, LDO bit HIGH
-65
-65
3
+65
+65
1±ꢀ
ꢁ
Output voltage
206±
ꢁ
Dropout voltage
Output current
ꢁ
CC
= 208ꢁ, LDO = 206±ꢁ, I
= 1ꢀmA
mꢁ
mA
dB
dB
LOAD
1ꢀ
4±
4±
2±
63
63
Output referred, ꢁ = 3ꢁ to ±ꢁ, LDO = 206±ꢁ
CC
Power supply rejection ratio
Output referred, ꢁ = 303ꢁ to±ꢁ, LDO = 3ꢁ
CC
Output current sense transimpedance
slope
Output voltage relative to 10±ꢁ / LDO current,
G = 2
ꢀ0ꢀ8
ꢀ01
ꢀ012
ꢁ/mA
mA
Output current sense range clip
G = 2
1808
REV 1E
3/22
XR10910
Electrical Characteristics (Continued)
T = 2±°C, ꢁ = 303ꢁ, ꢁ = 108ꢁ, R = 1ꢀkΩ to 10±ꢁ; G = 76ꢀ; unless otherwise noted0
A
CC
DD
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Dynamic Performance
BW -3dB bandwidth
SR Slew rate
G = 76ꢀ
G = 2
66
13ꢀꢀ
1
kHz
kHz
ꢁ
OUT
= 1ꢁ ; Gain = 2
ꢁ/μs
pp
f = 1ꢀHz
f = 1ꢀꢀHz
f = 1kHz
f = 1ꢀHz
7±
nꢁ/√Hz
nꢁ/√Hz
nꢁ/√Hz
fA/√Hz
e
Input voltage noise - RTI
46
ni
3±
i
n
Input current noise
Peak-to-peak noise
Crosstalk
ꢀ06
2
e
npp
f = ꢀ01 to 1ꢀHz
μꢁ
pp
XTALK
Channel-to-channel, f = 1kHz
9ꢀ
dB
T
T
Set-up time, 15 settling
Wake up time, 15 settling
Analog ready after serial register finished write
Wake from ACK of SLEEP_OUT command
30±
906
μs
μs
S
WAKE
Digital Characteristics (CMOS)
Symbol
Parameter
Conditions
Min
ꢀ07 x ꢁ
ꢀ
Typ
Max
Units
ꢁ
ꢁ
IH
Logic Input HIGH
ꢁ
DD
DD
ꢁ
IL
Logic Input LOW
Input Leakage HIGH
Input Leakage LOW
Clock Rate
ꢀ03 x ꢁ
ꢁ
μA
DD
I
I
ꢁ = ꢁ
S
1ꢀ
IH
IL
I
ꢁ = ꢀ
I
-1ꢀ
μA
CLK
ꢀ04
MHz
F
I2C Bus Timing
T = -4ꢀ to +8±°C, ꢁ = 108 - ±ꢁ; unless otherwise noted0
A
DD
Standard Mode
I2C-BUS
Fast Mode
I2C-BUS
Symbol
Parameter
Units
Min
ꢀ
Max
1ꢀꢀ
Min
Max
4ꢀꢀ
f
Operating frequency
ꢀ
kHz
μs
μs
μs
μs
μs
ns
ns
μs
μs
ns
ns
μs
SCL
T
T
T
T
T
T
T
T
T
T
T
T
Bus free time between STOP and START
START condition hold time
START condition setup time
Data hold time
407
40ꢀ
407
ꢀ
103
ꢀ06
ꢀ06
ꢀ
BUF
HD;STA
SU;STA
HD;DAT
ꢁD;ACK
ꢁD;DAT
SU;DAT
LOW
Data valid acknowledge
SCL LOW to data out valid
Data setup time
ꢀ06
ꢀ06
ꢀ06
ꢀ06
2±ꢀ
407
40ꢀ
1±ꢀ
103
ꢀ06
Clock LOW period
Clock HIGH period
HIGH
F
Clock/data fall time
3ꢀꢀ
3ꢀꢀ
3ꢀꢀ
Clock/data rise time
1ꢀꢀꢀ
R
Pulse width of spikes tolerance
ꢀ0±
ꢀ0±
SP
REV 1E
4/22
XR10910
Electrical Characteristics (Continued)
Figure 3: I2C Bus Timing Diagram
REV 1E
±/22
XR10910
Register Information
Table 10 Register List
R/
W/
C
Reg No0
Byte of
Parameter
Default Power-up
Name
Function
Parameter
Remark
Code
Condition
Hex Dec
Does not execute a function0 NOP
is used to test successful I2C
communication
NOP
ꢀxꢀꢀ
ꢀ
No operation
C
C
ꢀ
N/A
Reset
SW_RESET
Software reset
Read Device ID
Resets all registers to default values
ꢀxꢀ1
1
ꢀ
N/A
Read ID
Instructs the XR1ꢀ91ꢀ to report its
device ID “ꢀ91ꢀ” in binary form
(ꢀꢀꢀꢀ 1ꢀꢀ1 ꢀꢀꢀ1 ꢀꢀꢀꢀ)
[1±:ꢀ]: report “ꢀ91ꢀ” in
BCD
DEꢁICE_ID
ꢀxꢀ91ꢀ
N/A
ꢀxꢀ2
2
3
R
R
2
2
[1±:12]: reserved
Read HW & SW
version numbers
ꢁERSION_ID
[11:8]: Hardware version #
[7:ꢀ]: Software version #
Initial H/W version number is ‘ꢀ’;
Initial S/W version number is ‘ꢀ1’0
ꢀxꢀ3
Sleep in/out
Normal operating
mode, system
active
SLEEP_OUT
_ REG
Puts the XR1ꢀ19ꢀ into active mode0
(wake up)
ꢀxꢀ4
4
C
C
ꢀ
ꢀ
N/A
N/A
Active
Active
Puts the analog portion of the XR1ꢀ91ꢀ
into sleep mode0
During sleep mode, the only I2C command
that can be received/processed is the
SLEEP_OUT command (ꢀxꢀ4)0 All other
register addresses will be ignored0
SLEEP_IN_
REG
Sleep Mode
ꢀxꢀ±
±
Basic Config
Eight gain settings are selectable (from
2ꢁ/ꢁ to 76ꢀꢁ/ꢁ), refer to the Gain Register
Table for more information0
Bit ꢀ controls the LDO voltage (ꢀ: 3ꢁ;
1: 206±ꢁ)0
Bit 1 (Sleep Mode only)0 Bit 1 controls
whether the LDO shuts down or stays on
during Sleep Mode0 (ꢀ: Enable; 1: Disable)0
When the XR1ꢀ91ꢀ is active, the LDO is
always on0
Gain
= 2
Gain
LDO
Gain select
R/W
R/W
[2:ꢀ]: Gain select
ꢀxꢀ6
6
1
1
ꢀxꢀꢀ
ꢀxꢀꢀ
[ꢀ]:LDO 3ꢁ, 206±ꢁ
[1]:LDO disable
LDO
= 3ꢁ
LDO Settings
ꢀxꢀ7
ꢀxꢀ8
7
When on, the LDO current is sensed and
a proportional voltage is present at the
output of the XR1ꢀ91ꢀ0
Current Sense Mode remains active until
an input select command is received by
the XR1ꢀ91ꢀ0
LDO Current
Sense Select
LDO Current Sense
8
C
ꢀ
N/A
Off
REV 1E
6/22
XR10910
R/
W/
C
Reg No0
Byte of
Parameter
Default Power-up
Name
Function
Parameter
Remark
Code
Condition
Hex Dec
Channel Switch (Input Mux Select)
Select_
Select Channel 1
Select Channel 2
Select Channel 3
Select Channel 4
Select Channel ±
Select Channel 6
Select Channel 7
Select Channel 8
Select Channel 9
Select Channel 1ꢀ
Select Channel 11
Select Channel 12
Select Channel 13
Select Channel 14
Select Channel 1±
Select Channel 16
ꢀx1ꢀ 16
ꢀx11 17
ꢀx12 18
ꢀx13 19
ꢀx14 2ꢀ
ꢀx1± 21
ꢀx16 22
ꢀx17 23
ꢀx18 24
ꢀx19 2±
ꢀx1A 26
ꢀx1B 27
ꢀx1C 28
ꢀx1D 29
ꢀx1E 3ꢀ
ꢀx1F 31
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Select +IN1, -IN1; Channel 1
Select +IN2, -IN2; Channel 2
Select +IN3, -IN3; Channel 3
Select +IN4, -IN4; Channel 4
Select +IN±, -IN±; Channel ±
Select +IN6, -IN6; Channel 6
Select +IN7, -IN7; Channel 7
Select +IN8, -IN8; Channel 8
Select +IN9, -IN9; Channel 9
Select +IN1ꢀ, -IN1ꢀ; Channel 1ꢀ
Select +IN11, -IN11; Channel 11
Select +IN12, -IN12; Channel 12
Select +IN13, -IN13; Channel 13
Select +IN14, -IN14; Channel 14
Select +IN1±, -IN1±; Channel 1±
Select +IN16, -IN16; Channel 16
Input_1
Select_
Input_2
Select_
Input_3
Select_
Input_4
Select_
Input_±
Select_
Input_6
Select_
Input_7
Select_
Input_8
Channel
1 is
selected
N/A
Select_
Input_9
Select_
Input_1ꢀ
Select_
Input_11
Select_
Input_12
Select_
Input_13
Select_
Input_14
Select_
Input_1±
Select_
Input_16
REV 1E
7/22
XR10910
R/
W/
C
Reg No0
Byte of
Parameter
Default Power-up
Name
Function
Parameter
Remark
Code
Condition
Hex Dec
Offset DAC Config
Configures DAC
offset applied to
Channel 1
DAC1
ꢀx2ꢀ 32
ꢀx21 33
ꢀx22 34
ꢀx23 3±
ꢀx24 36
ꢀx2± 37
ꢀx26 38
ꢀx27 39
ꢀx28 4ꢀ
ꢀx29 41
ꢀx2A 42
ꢀx2B 43
ꢀx2C 44
ꢀx2D 4±
ꢀx2E 46
ꢀx2F 47
NOTE:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Configures DAC
offset applied to
Channel 2
DAC2
DAC3
DAC4
DAC±
DAC6
DAC7
DAC8
DAC9
DAC1ꢀ
DAC11
DAC12
DAC13
DAC14
DAC1±
DAC16
Configures DAC
offset applied to
Channel 3
Configures DAC
offset applied to
Channel 4
Configures DAC
offset applied to
Channel ±
Configures DAC
offset applied to
Channel 6
Configures DAC
offset applied to
Channel 7
Configures DAC
offset applied to
Channel 8
Bit 1ꢀ controls the sign of the DAC offset
voltage0 Bits 9 thru ꢀ control the value of
the DAC offset voltage0
[1ꢀ]: DAC Sign
ꢀmꢁ
offset
ꢀxꢀꢀ
[9:ꢀ]: DAC Range
Configures DAC
offset applied to
Channel 9
[1ꢀ]: DAC Sign ꢀ = positive; 1 = negative
Configures DAC
offset applied to
Channel 1ꢀ
Configures DAC
offset applied to
Channel 11
Configures DAC
offset applied to
Channel 12
Configures DAC
offset applied to
Channel 13
Configures DAC
offset applied to
Channel 14
Configures DAC
offset applied to
Channel 1±
Configures DAC
offset applied to
Channel 16
Register Numbers not listed above have no function0
REV 1E
8/22
XR10910
Table 20 DAC Registers
Hex
D1ꢀ D9
D8
1
D7
1
D6
1
D±
1
D4
1
D3
1
D2
1
D1
1
Dꢀ
1
Offset 5 of FS Input
ꢁoltage RTI
ꢀx3FF
ꢀxꢀꢀꢀ
ꢀx7FF
ꢀx4ꢀꢀ
ꢀ
ꢀ
1
1
1
ꢀ
1
ꢀ
±ꢀ
ꢀ
+±6ꢀmꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-±6ꢀmꢁ
ꢀ
1
1
1
1
1
1
1
1
1
-±ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DAC
Sign
1ꢀ-bit DAC Range
Table 3: Gain Registers
Hex
D2
D1
Dꢀ
Gain
ꢀxꢀꢀ
ꢀxꢀ1
ꢀxꢀ2
ꢀxꢀ3
ꢀxꢀ4
ꢀxꢀ±
ꢀxꢀ6
ꢀxꢀ7
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
2
2ꢀ
4ꢀ
8ꢀ
1±ꢀ
3ꢀꢀ
6ꢀꢀ
76ꢀ
REV 1E
9/22
XR10910
Pin Configuration
ꢉꢅ1ꢋ
ꢉꢅ1ꢆ
ꢉꢅ1ꢏꢆ
ꢉꢅ1ꢏꢋ
ꢉꢅ1ꢇꢆ
ꢉꢅ1ꢇꢋ
ꢉꢅ1ꢊꢆ
ꢉꢅ1ꢊꢋ
ꢉꢅ1ꢈꢆ
ꢉꢅ1ꢈꢋ
ꢉꢅ11ꢆ
1
ꢈ
ꢊꢁ
ꢈꢂ
ꢈꢍ
ꢈꢎ
ꢈꢌ
ꢈꢏ
ꢈꢇ
ꢈꢊ
ꢈꢈ
ꢈ1
ꢉꢅꢈꢋ
ꢉꢅꢈꢆ
ꢉꢅꢊꢋ
ꢉꢅꢊꢆ
ꢉꢅꢇꢋ
ꢉꢅꢇꢆ
ꢉꢅꢏꢋ
ꢉꢅꢏꢆ
ꢊ
ꢇ
ꢀR1ꢁꢂ1ꢁ
ꢏ
ꢃꢄꢅꢆꢇꢁ
ꢌ
ꢎ
ꢍ
ꢂ
ꢉꢅ11ꢋ
1ꢁ
NOTE:
MaxLinear recommends grounding the exposed pad0
Pin Functions
Pin No0
Pin Name
IN1+
IN1-
Description
Pin No0
Pin Name
IN11+
IN11-
IN12+
IN12-
IN13+
IN13-
IN14+
IN14-
IN1±+
IN1±-
IN16+
IN16-
BRDG
AGND
OUT
Description
1
2
Positive Input 1
Negative Input 1
Positive Input 2
Negative Input 2
Positive Input 3
Negative Input 3
Positive Input 4
Negative Input 4
Positive Input ±
Negative Input ±
Positive Input 6
Negative Input 6
Positive Input 7
Negative Input 7
Positive Input 8
Negative Input 8
Positive Input 9
Negative Input 9
Positive Input 1ꢀ
Negative Input 1ꢀ
21
22
23
24
2±
26
27
28
29
3ꢀ
31
32
33
34
3±
36
37
38
39
4ꢀ
Positive Input 11
Negative Input 11
Positive Input 12
Negative Input 12
Positive Input 13
Negative Input 13
Positive Input 14
Negative Input 14
Positive Input 1±
Negative Input 1±
Positive Input 16
Negative Input 16
3
IN2+
IN2-
4
±
IN3+
IN3-
6
7
IN4+
IN4-
8
9
IN±+
IN±-
1ꢀ
11
12
13
14
1±
16
17
18
19
2ꢀ
IN6+
IN6-
IN7+
IN7-
BRDG Power Connection ( LDO output )
Analog Ground
IN8+
IN8-
Output
ꢁCC
Analog Supply
IN9+
IN9-
DGND
SCL
Digital Ground
Serial Clock Input
Serial Data Input/Output
Digital Supply
IN1ꢀ+
IN1ꢀ-
SDA
ꢁDD
REV 1E
1ꢀ/22
XR10910
Typical Performance Characteristics
T = 2±°C, ꢁ = 303ꢁ, ꢁ = 108ꢁ, R = 1ꢀkΩ to 10±ꢁ; G = 76ꢀ; unless otherwise noted0
A
CC
DD
L
2
1.75
1.5
G = 2, Vout = 2.5Vpp
G = 2, Vout = 0.5Vpp
3
2.5
2
1.5
1
1.25
1
0.5
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
Time (µs)
25
30
35
40
Time (µs)
Figure 40 Small Signal Pulse Response at G = 2
Figure ±0 Large Signal Pulse Response at G = 2
2
G = 300, Vout = 2.5Vpp
3
G = 300, Vout = 0.5Vpp
2.5
2
1.75
1.5
1.25
1
1.5
1
0.5
0
0
20
40
60
80
100
0
20
40
60
80
100
Time (µs)
Time (µs)
Figure 60 Small Signal Pulse Response at G = 3ꢀꢀ
Figure 70 Large Signal Pulse Response at G = 3ꢀꢀ
3
3
G = 2
G = 300
0
0
-3
-3
-6
VOUT = 0.5Vpp
VOUT = 0.5Vpp
VOUT = 1Vpp
VOUT = 1Vpp
-6
VOUT = 2.5Vpp
VOUT = 2.5Vpp
-9
-9
-12
-12
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 80 Frequency Response at G = 2
Figure 90 Frequency Response at G = 3ꢀꢀ
REV 1E
11/22
XR10910
Typical Performance Characteristics
T = 2±°C, ꢁ = 303ꢁ, ꢁ = 108ꢁ, R = 1ꢀkΩ to 10±ꢁ; G = 76ꢀ; unless otherwise noted0
A
CC
DD
L
3.5
4
3.5
3
G = 2
Current Sense Mode Active
VCC = 5V
3
2.5
2
2.5
2
VCC = 3.3V
1.5
1
0.5
0
1.5
0
5
10
15
20
25
0
10
20
30
40
50
ILDO (mA)
ILDO (mA)
Figure 1ꢀ0 LDO Current vs0 Output ꢁoltage
Figure 110 LDO Output Current
5
4
1.55
1.53
1.51
1.49
1.47
1.45
1.43
1.41
1.39
1.37
1.35
G = 2
G = 2
3
G = 300
2
G = 760
1
0
-1
0.25
0.75
1.25
1.75
2.25
2.75
-10
-5
0
5
10
Input Common Mode Voltage (V)
Output Current (mA)
Figure 120 Output Offset ꢁoltage vs0 Output Current
Figure 130 Output Offset vs0 Input Common Mode ꢁoltage
100
90
2.5
2
G = 760
80
70
60
50
40
30
20
10
0
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0.01
0.1
1
10
100
1000
0
2
4
6
8
10
Frequency (KHz)
Time (sec)
Figure 140 Input ꢁoltage Noise vs0 Frequency
Figure 1±0 ꢀ01Hz to 1ꢀHz RTI ꢁoltage Noise
REV 1E
12/22
XR10910
Typical Performance Characteristics
T = 2±°C, ꢁ = 303ꢁ, ꢁ = 108ꢁ, R = 1ꢀkΩ to 10±ꢁ; G = 76ꢀ; unless otherwise noted0
A
CC
DD
L
2.5
2
4
3.5
3
G = 2
Stop Time = 1% Settling
Stop Time = 1% Settling
SDA
1.5
1
2.5
2
DUT OUTPUT
DUT OUTPUT
SDA
1.5
1
0.5
0
Start Time = 50% Acknowledge
0.5
0
Start Time = 50% Acknowledge
-0.5
0
5
10
15
20
0
5
10
Time (µs)
15
20
Time (µs)
Figure 160 Sleep to Wake Time (DUT Output)
Figure 170 Set-up Time - from G = 2 to G = 3ꢀꢀ
(DUT Output)
4
3.5
3
3.5
3
2.5
2
LDO OUTPUT
SDA
Stop Time = 1% Settling
2.5
2
1.5
1
1.5
1
LDO Output
SDA
0.5
0
Stop Time = 1% Settling
0.5
0
Start Time = 50% Acknowledge
Start Time = 50% Acknowledge
10 20 30
-0.5
-0.5
0
50
100
150
200
250
0
40
50
Time (µs)
Time (µs)
Figure 180 LDO Enable to Disable Time
Figure 190 LDO Disable to Enable Time
REV 1E
13/22
XR10910
Functional Block Diagram
Vꢌꢌ
ꢟꢋꢇ ꢇꢙꢆꢪꢙꢆ
1ꢍꢎV
Rꢊꢈꢊꢏꢊꢐꢑꢊ
ꢟꢋꢇ Eꢐꢖꢄꢗꢊ
ꢟꢋꢇ ꢝꢊꢗꢊꢑꢆ ꢠ ꢡVꢢ ꢛꢍꢔꢎV ꢣ
ꢂꢁꢐꢩ
ꢜꢐꢪꢙꢆ 1 ꢒꢫꢓ
ꢜꢐꢪꢙꢆ ꢛ ꢒꢫꢓ
ꢜꢐꢪꢙꢆ ꢡ ꢒꢫꢓ
ꢜꢐꢪꢙꢆ ꢬ ꢒꢫꢓ
ꢀꢁꢂ
ꢇꢙꢆꢪꢙꢆ
ꢜꢐꢪꢙꢆ 1ꢬ ꢒꢫꢓ
ꢜꢐꢪꢙꢆ 1ꢎ ꢒꢫꢓ
ꢜꢐꢪꢙꢆ 1ꢔ ꢒꢫꢓ
1ꢃ ꢄꢅꢆ ꢇꢈꢈꢉꢊꢆ ꢋꢂꢌ
Vꢋꢋ
ꢝꢋꢂ
ꢝꢌꢟ
ꢜꢛꢌ ꢝꢊꢏꢅꢖꢗ ꢋꢅꢞꢅꢆꢖꢗ ꢜꢐꢆꢊꢏꢈꢖꢑꢊ
ꢋꢁꢐꢩ
Figure 2ꢀ: Functional Block Diagram
Application Information
The XR1ꢀ91ꢀ also provides the ability to monitor the LDO
current0 When the XR1ꢀ91ꢀ is in Current Sense Mode, an
internal 2:1 mux allows a voltage proportional to the LDO
current to be present at the output0 Once all channels have
been calibrated, the LDO current can be used to indirectly
monitor any voltage or resistive changes seen by the inputs0
The XR1ꢀ91ꢀ sensor interface includes a 16:1 differential
multiplexor (mux), a programmable gain instrumentation
amplifier, a 1ꢀ-bit offset correction DAC and an LDO0 An
I2C interface controls the many functions and features of the
XR1ꢀ91ꢀ0 The XR1ꢀ91ꢀ is designed to integrate multiple
bridge sensors with an ADC/MCU or FPGA0
The XR1ꢀ91ꢀ also includes an internal 10±ꢁ reference that
is used by the internal LDO circuitry and used to set the
reference voltage for the programmable gain instrumentation
amplifier0
Each bridge sensor connected to the XR1ꢀ91ꢀ has its
own inherent offset that if not calibrated out can decrease
sensitivity and overall performance of the sensor system0The
on-board DAC introduces an offset into the instrumentation
amplifier to calibrate the offset voltage generated by the
sensors0 An independent offset can be set for each of the
16 channels0 Only the offset voltage of the active channel is
applied to the PGA0
During sleep mode, the analog components of the XR1ꢀ91ꢀ
are powered down for added power savings0
The XR1ꢀ91ꢀ offers many functions, each controlled by the
I2C compatible serial interface:
The programmable gain instrumentation amplifier offers 8
selectable gains from 2ꢁ/ꢁ to 76ꢀꢁ/ꢁ to amplify the signal
such that it falls within the input range of the ADC0
■■
Input Selection
■■
Gain Selection
■■
Offset Correction
An integrated LDO provides a regulated voltage to power
the input bridge sensors and is selectable, between 3ꢁ and
206±ꢁ0 The LDO can be set to turn off when the XR1ꢀ91ꢀ is
in Sleep Mode to save power0
■■
LDO Enable / Select
■■
Current Sense Mode
■■
Sleep Mode (Analog Power Down)
REV 1E
14/22
XR10910
Application Information (Continued)
Power Up
Data Cycle
After initial system power up, the I2C master must provide
one SCL clock pulse prior to the first I2C access (first start
condition)0 The first access to the XR1ꢀ91ꢀ must be a
RESET command0
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address0 This 8-bit
sub-address contains the address of the register to access0
The XR1ꢀ91ꢀ Register List is shown in Table 10 Depending
on the register accessed, there will be up to two additional
data bytes transmitted by the master0 Refer to the “Byte of
Parameter” column in the Register Table0 The XR1ꢀ91ꢀ will
respond to each write with an acknowledge0
SDA
SCL
Stop Condition
Figure 21: I2C Power Up
I2C Bus Interface
To signal the end of the data transfer, the master generates
a stop condition by pulling the SDA line from low to high
while the SCL line is high, as shown in Figure 220
The I2C-bus interface consists of two lines: serial data (SDA)
and serial clock (SCL)0 The XR1ꢀ91ꢀ works as a slave and
supports both standard mode transfer rates (1ꢀꢀ kbps) and
fast mode transfer rates (4ꢀꢀ kbps) as defined in the I2C-
Bus specification0 The I2C-bus interface follows all standard
I2C protocols0 Some information is provided below, for
additional information, refer to the I2C-bus specifications0
Figures 23 and 24 illustrate a write and a read cycle0 For
complete details, see the I2C-bus specifications0
SLAꢁE
ADDRESS
REGISTER
ADDRESS
S
W
A
A
nDATA
A
P
NOTES:
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Figure 23: Master Writes to Slave (XR1ꢀ91ꢀ)
SLAꢁE
ADDRESS
REGISTER
ADDRESS
SLAꢁE
ADDRESS
LAST
DATA
nDATA
S
W A
A S
R A
A
NA P
NOTES:
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Figure 22: I2C Start and Stop Conditions
Figure 24: Master Reads from Slave (XR1ꢀ91ꢀ)
I2C Bus Addressing
The basic I2C access cycle for the XR1ꢀ91ꢀ consists of:
■■
A start condition
The XR1ꢀ91ꢀ uses a 7-bit address space0 For the standard
XR1ꢀ91ꢀ, the default address is ꢀx67 (11ꢀ ꢀ111)0
■■
A slave address cycle
■■
Zero, one, or two data cycles - depending on the XR1ꢀ91ꢀ
Table 4: XR1ꢀ91ꢀ I2C Address Map
register accessed
■■
A stop condition
I2C Address
ꢀx67
Orderable Part Number
XR1ꢀ91ꢀIL4ꢀTR-F
Start Condition
The master initiates data transfer by generating a start
condition0The start condition is when a high-to-low transition
occurs on the SDA line while SCL is high, as shown in
Figure 220
A read or write transaction is determined by bit-ꢀ of the
slave address, (shown as an “x” in Table 4 above)0 If bit-ꢀ is
’ꢀ,’ then it is a write transaction0 If bit-ꢀ is ’1,’ then it is a read
transaction0
Slave Address Cycle
An I2C sub-address is sent by the I2C master following
the slave address0 The sub-address contains the XR1ꢀ91ꢀ
register address being accessed0 Table 1 illustrates the
available XR1ꢀ91ꢀ register addresses0
After the start condition, the first byte sent by the master
is the 7-bit address and the read/write direction bit R/W
on the SDA line0 If the address matches the XR1ꢀ91ꢀ’s
internal fixed address, the XR1ꢀ91ꢀ will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high0
After the last read or write transaction, the I2C-bus master
will set the SCL signal back to its idle state (HIGH)0
REV 1E
1±/22
XR10910
Application Information (Continued)
Gain Selection
Inputs and Input Selection
The XR1ꢀ91ꢀ offers 8 selectable fixed gains ranging from
2ꢁ/ꢁ to 76ꢀꢁ/ꢁ0 When the XR1ꢀ91ꢀ is powered-up, the
default gain is 2ꢁ/ꢁ0
The gain is selected via I2C using the register address ꢀxꢀ6
followed by another byte of data to select the gain0 Refer
to the Register List in Table 1 and the Gain Register list in
Table 30
The XR1ꢀ91ꢀ includes 16 differential inputs and a 16:1
differential mux that is controlled by an I2C compatible 2
wire serial interface0 The XR1ꢀ91ꢀ is designed to accept 16
differential inputs0
■■
If fewer than 16 differential inputs are required, tie the unused
inputs to GND0
■■
If single ended inputs are required, tie the unused inputs to
10±ꢁ0
Example: The example below illustrates how to select a
gain of 1±ꢀꢁ/ꢁ0
The input common mode range of the XR1ꢀ91ꢀ is typically
ꢀ06ꢁ to 204ꢁ when running from a 303ꢁ supply0 The XR1ꢀ91ꢀ
offers a very wide gain range0 In most cases, the output
voltage swing will be the limiting factor0
To start communication with the XR1ꢀ91ꢀ, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
160
When the XR1ꢀ91ꢀ is powered-up, the default input selected
is Channel 10
Inputs are selected via I2C using one of 16 register addresses
ꢀx1ꢀ thru ꢀx1F0 Refer to the Register List in Table 10
Step 4
7
ꢀ
6
ꢀ
±
ꢀ
4
ꢀ
3
ꢀ
2
1
1
1
ꢀ
ꢀ
Master sends address of register to
access
Gain Select
register address = ꢀxꢀ6
Example: The example below illustrates how to select
Channel ±0
Step ±
9
Step 1
ꢀ
XR1ꢀ91ꢀ sends acknowledge
A
Master sends start condition
S
Since the Gain Select register was accessed, the XR1ꢀ91ꢀ
is expecting another byte of data from the master to complete
the command0 Refer to the “Byte of Parameter” column in
the Register List (Table 1)0 Dꢀ thru D2 are used to select
the gain0 Refer to the Gain Register list in Table 3, 1±ꢀꢁ/ꢁ is
D2 = 1, D1 = ꢀ, and Dꢀ = ꢀ0 This translates to a hex code of
ꢀxꢀ4, since a full byte of data (8-bits) will be sent0
Step 2
7
1
6
1
±
ꢀ
4
ꢀ
3
1
2
1
1
1
ꢀ
ꢀ
Master sends XR1ꢀ91ꢀ address with
write bit
7-bit XR1ꢀ91ꢀ
Address = ꢀx67
W
Step 3
9
Step 6
7
ꢀ
6
ꢀ
±
ꢀ
4
ꢀ
3
ꢀ
2
1
1
ꢀ
ꢀ
ꢀ
XR1ꢀ91ꢀ sends acknowledge
A
Master sends gain register data to select
G=1±ꢀ
Step 4
7
ꢀ
6
ꢀ
±
ꢀ
4
1
3
ꢀ
2
1
1
ꢀ
ꢀ
ꢀ
Gain of 1±ꢀꢁ/ꢁ = ꢀxꢀ4
Master sends address of register to
access
Select_Input 5
register address = ꢀx14
Step 7
9
XR1ꢀ91ꢀ sends acknowledge
A
Step ±
9
Step 8
ꢀ
XR1ꢀ91ꢀ sends acknowledge
A
Master sends stop condition
P
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Grey Block = Notes
Step 6
ꢀ
Master sends stop condition
P
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Grey Block = Notes
REV 1E
16/22
XR10910
Application Information (Continued)
Offset Correction
The XR1ꢀ91ꢀ has a 1ꢀ-bit offset correction DAC that can be
used to provide digital calibration on each of the 16 inputs0
Only the offset voltage of the active channel is applied to
the PGA0
The DAC offset of each channel is controlled by the I2C
compatible interface0 At any time, the master can read or
write to any of the DAC offset registers0 The DAC offset for
each channel is set via I2C using the register addresses
ꢀx2ꢀ thru ꢀx2F followed by another two bytes of data to
set the polarity and value of the offset voltage0 Refer to the
Register List in Table 10
Step ±
9
XR1ꢀ91ꢀ sends acknowledge
A
Since a DAC Offset register was accessed, the XR1ꢀ91ꢀ
is expecting another two bytes of data from the master to
complete the command0 Refer to the “Byte of Parameter”
column in the Register List (Table 1)0 Dꢀ thru D9 are used
to set the offset voltage and D1ꢀ is used to set the sign of
the offset voltage, ꢀ = positive and 1 = negative0 Refer to the
DAC Offset register list in Table 20
To determine what DAC output level corresponds to 7±mꢁ,
use the following equation:
A ±±6ꢀmꢁ offset correction range is available0 The full
range of the DAC offset is only available at a gain of 20 At
higher gains, the output voltage range of the XR1ꢀ91ꢀ will
be exceeded if the full range of the DAC offset is used0 The
internal 1ꢀ-bit DAC allows 1,ꢀ24 different offset voltage
settings between ꢀmꢁ and ±6ꢀmꢁ0 The polarity of the
offset correction is set with an additional bit0 The unit offset
is determined by the following:
ꢀꢈꢏꢍꢐꢈꢑ ꢃꢎꢎꢏꢈꢅ
ꢋꢌꢍꢅ ꢃꢎꢎꢏꢈꢅ
ꢔꢒꢖꢕ
ꢒꢓꢔnꢕ
ꢙ
ꢙ
ꢙ
ꢀꢁꢂ ꢃꢄꢅꢆꢄꢅ ꢇꢈꢉꢈꢊ
ꢗꢘꢔ
A decimal value of 137 corresponds to 7±mꢁ0 Therefore:
■■
ꢀx89 (hex) or ꢀ ꢀꢀ 1ꢀꢀꢀ 1ꢀꢀ1 (binary) applies a +7±mꢁ
offset
■■
ꢀx489 (hex) or 1 ꢀꢀ 1ꢀꢀꢀ 1ꢀꢀ1 (binary) applies a -7±mꢁ
offset
ꢏꢄꢃꢐꢍ ꢑꢅꢅꢆꢇꢃ
ꢈꢉꢊ ꢄꢋꢃꢌꢋꢃ ꢍꢇꢎꢇꢍꢆ
ꢖꢗꢓꢘꢙ
ꢒꢓꢔꢕ
ꢛ
ꢛ
ꢛ
ꢀꢁꢂꢃ ꢄꢅꢅꢆꢇꢃ
ꢖꢕꢚnꢙ
1± 14 13 12 11
1ꢀ
ꢀ
9
8
Step 6
Master sends 1st byte
of DAC offset register
data to select an offset
of +7±mꢁ
From Table 3:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
■■
ꢀxꢀꢀ (hex) or ꢀ ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (binary) applies a ꢀmꢁ offset
2 MSBs of 1ꢀ-bit DAC
output level that corre-
sponds to 137 (ꢀx89)
■■
■■
ꢀx3FF (hex) or ꢀ 11 1111 1111 (binary) applies a +±6ꢀmꢁ
offset
Sign
ꢀx7FF (hex) or 1 11 1111 1111 (binary) applies a -±6ꢀmꢁ
offset
Each DAC output level provides an additional ±47µꢁ of
offset0 To determine what DAC output level corresponds to
a specific desired offset, use the following equation:
Step 7
9
XR1ꢀ91ꢀ sends acknowledge
A
7
6
±
4
3
2
1
ꢀ
Step 8
Master sends 2nd byte of DAC offset
register data to select an offset of +7±mꢁ
1
ꢀ
ꢀ
ꢀ
1
ꢀ
ꢀ
1
See example below for additional information0
8 LSBs of 1ꢀ-bit DAC output
level that corresponds to 137
(ꢀx89)
Example: The example below illustrates how to set the DAC
offset for channel 4 to a value of 7±mꢁ0
To start communication with the XR1ꢀ91ꢀ, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
160
Step 9
9
XR1ꢀ91ꢀ sends acknowledge
A
Step 4
7
ꢀ
6
ꢀ
±
1
4
ꢀ
3
ꢀ
2
1
1
1
ꢀ
ꢀ
Master sends address of register to
access
Step 1ꢀ
ꢀ
Master sends stop condition
P
DAC4 register address
= ꢀx2±
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Grey Block = Notes
REV 1E
17/22
XR10910
Application Information (Continued)
7
6
±
4
3
2
1
ꢀ
ꢀ
ꢀ
Step 6
LDO Enable / Select (Power to External Bridge Sensors)
Master sends code to select LDO
voltage of 206±ꢁ and Enable LDO
during Sleep Mode
The XR1ꢀ91ꢀ includes an on-board LDO that provides a
regulated voltage that can be used to power external input
bridge sensors0 Two voltage options are available, 3ꢁ and
206±ꢁ0 The LDO voltage is selected via the I2C compatible
two-wire serial interface0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ =
1 =
Enable 206±ꢁ
When the XR1ꢀ91ꢀ is powered-up, the default LDO voltage
is 3ꢁ0
Step 7
9
XR1ꢀ91ꢀ sends acknowledge
A
When the XR1ꢀ91ꢀ is active (not in sleep mode), the LDO
is always on0 If the LDO voltage is not used, the LDO output
can be left floating0The LDO can either stay on or shut down
while the XR1ꢀ91ꢀ is in Sleep Mode0
Step 8
ꢀ
Master sends stop condition
P
■■
Set LDO to shut down while XR1ꢀ91ꢀ is in Sleep Mode to
White Block = host to XR1ꢀ91ꢀ, Red Block = XR1ꢀ91ꢀ to host
Grey Block = Notes
save power
■■
Set LDO to stay on while XR1ꢀ91ꢀ is in Sleep Mode to
improve wake-up time
The LDO voltage and disable setting are selected via I2C
using the register address ꢀxꢀ7 followed by another byte
of data to select the voltage and disable setting0 Refer to
the Register List in Table 1 and the example below for more
information0
Current Sense Mode (Monitoring the LDO Current)
Current Sense Mode is activated via I2C using the register
address ꢀxꢀ80 When activated, the LDO current is sensed
and a proportional voltage is present at the output of the
XR1ꢀ91ꢀ (ILDO = ꢁOUT/RL)0 Current Sense Mode stays
active until the XR1ꢀ91ꢀ receives any input select command
(ꢀx1ꢀ thru ꢀx1F)0
Example: The example below illustrates how to select an
LDO voltage of 206±ꢁ and keep the LDO enabled during
Sleep Mode0
Current sense mode can be used to monitor the change
over time of the bridge impedance0
To start communication with the XR1ꢀ91ꢀ, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
110
Sleep Mode (Analog Power Down)
Sleep Mode is activated via I2C using the register address
ꢀxꢀ±0 When activated, the XR1ꢀ91ꢀ will enter Sleep Mode0
During Sleep Mode, the analog portion of the XR1ꢀ91ꢀ
is disabled0 All register settings are retained during Sleep
Mode0
Step 4
7
ꢀ
6
ꢀ
±
ꢀ
4
ꢀ
3
ꢀ
2
1
1
1
ꢀ
1
Master sends address of register to
access
LDO Settings
register address = ꢀxꢀ7
During Sleep Mode, the nominal supply current will drop
below 7ꢀµA (with LDO on) and below 4±µA (with LDO off)0
Step ±
9
XR1ꢀ91ꢀ sends acknowledge
A
During Sleep Mode, the master can read the value in any
register that saves a value during sleep mode0 The only
I2C commands that can be received or processed is the
SLEEP_OUT (wake up) command (ꢀxꢀ4) or the LDO on/off
and voltage command (ꢀxꢀ7)0 All other register addresses
will be ignored0
Since the LDO Settings register was accessed, the
XR1ꢀ91ꢀ is expecting another byte of data from the master
to complete the command0 Refer to the “Byte of Parameter”
column in the Register List (Table 1)0 Dꢀ and D1 are used to
select the LDO voltage and enable/disable the LDO during
Sleep Mode0 Bit ꢀ (Dꢀ) controls the LDO voltage (ꢀ: 3ꢁ;
1: 206±ꢁ)0 Bit 1 (D1) is only applicable in Sleep Mode0 Bit
1 controls whether the LDO shuts down or stays on during
sleep mode (ꢀ: Enable; 1: Disable)0 When the XRꢀ91ꢀ is
active, the LDO is always on0
Register address ꢀxꢀ4 is used to return to normal operation
(exit Sleep Mode)0
By default, the XR1ꢀ91ꢀ is active0
REV 1E
18/22
XR10910
Application Information (Continued)
Typical Application – 16:1 Bridge Sensor Interface
The XR1ꢀ91ꢀ was designed to interface multiple bridge sensors with a microcontroller or FPGA as illustrated in Figure 2±0
The bridge output signal is differential (ꢁo+ and ꢁo-)0 Ideally, the unloaded bridge output is zero (ꢁo+ and ꢁo- are identical)0
However, in-exact resistive values result in a difference between ꢁo+ and ꢁo-0 This bridge offset voltage can be substantial
and vary between sensors0 The XR1ꢀ91ꢀ provides the ability to calibrate the bridge offset on each of the 16 bridge sensors
using the on-board DAC0
mDD
mCC
6.8μF
6.8μF
+
+
ꢀ.1μF
ꢀ.1μF
BRDG
mCC
mDD
ꢀ.1μF
BRIDGE 16
LDO
IN16+
IN16-
1ꢀk
OUT
INA /
PGA
ADC
µC
1ꢀnF
16:1
MUX
±±6ꢀ0m
OFFSET TRIM
mDD
4.7k
mDD
4.7k
BRIDGE 1
1ꢀ-BIT
DAC
PGA
IN1+
IN1-
SDA
SCL
2
I C
CONTROL
XR10910
AGND
DGND
Figure 2±: 16:1 Bridge Sensor Interface
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance0 Follow the steps below as a basis for
high frequency layout:
■■
Include 608µF and ꢀ01µF ceramic capacitors for power supply decoupling
■■
Place the 608µF capacitor within ꢀ07± inches of the power pin
■■
Place the ꢀ01µF capacitor within ꢀ01 inches of the power pin
■■
Connection to the exposed pad is not required0 Exposed pad can be connected to ground (GND)0
■■
Minimize all trace lengths to reduce series inductances
REV 1E
19/22
XR10910
Mechanical Dimensions
QFN-4ꢀ Package
TOP VIEW
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD-00000041
Revision: B.3
REV 1E
2ꢀ/22
XR10910
Recommended Land Pattern and Stencil
QFN-4ꢀ Package
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD-00000041
Revision: B.3
REV 1E
21/22
XR10910
Ordering Information(1)
Part Number
Operating Temperature Range
-4ꢀ°C to +8±°C
Lead-Free
Yes(2)
Package
QFN-4ꢀ
Packaging Method
XR1ꢀ91ꢀIL4ꢀ-F
Tray
XR1ꢀ91ꢀIL4ꢀTR-F
XR1ꢀ91ꢀIL4ꢀEꢁB
Tape & Reel
Evaluation Board
NOTES:
10 Refer to www0exar0com/XR1ꢀ91ꢀ for most up-to-date Ordering Information0
20 ꢁisit www0exar0com for additional information on Environmental Rating0
Revision History
Part
1A
Part
Part
May 2ꢀ1±
July 2ꢀ1±
Initial Release
1B
Added Typical Performance Characteristics section0
Updated to latest format and added figure numbers0 Updated Figures 1 and 2±0 Added
Figure 20 Updated page number reference in Gain section of Electrical Characteristics table0
Updated Figure 240 Added clarity to I2C Bus Addressing section0 Updated Table 40 Updated
Step 2 in Inputs and Input Selection section0
1C
May 2ꢀ16
Updated to MaxLinear logo0 Updated format and Ordering information table0 Added I2C
Power Up section0
1D
1E
March 2ꢀ18
January 2ꢀ19
Correct typo in Recommended Stencil0
Corporate Headquarters:
±966 La Place Court
Suite 1ꢀꢀ
Carlsbad, CA 92ꢀꢀ8
Tel0:+1 (76ꢀ) 692-ꢀ711
Fax: +1 (76ꢀ) 444-8±98
www0maxlinear0com
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system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the
risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances.
MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written
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Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated.
© 2016 - 2019 MaxLinear, Inc. All rights reserved
XR10910_DS_011519
REV 1E
22/22
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