XR16L2551IM [EXAR]
LOW VOLTAGE DUART WITH POWERSAVE; 具有省电模式低电压DUART
| 型号： | XR16L2551IM |
| 厂家： | 
EXAR CORPORATION |
| 描述： | LOW VOLTAGE DUART WITH POWERSAVE |
| 文件： | 总48页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
SEPTEMBER 2003
REV. 1.0.0
FEATURES
GENERAGENERAL DESCRIPTION
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
The XR16L2551 (L2551) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes additional capability over the ST16C2550:
Intel and Motorola data bus interface selection,
hardware and software flow control, infrared encoder/
decoder, sleep mode and a PowerSave mode for
battery operation. The L2551’s enhanced register set
is compatible to the ST16C2550 and XR16L2550. It
supports the Exar’s enhanced features of 16 bytes of
TX and RX FIFOs and a complete modem interface.
Onboard registers provide the user with operational
status and data error tags. An internal loopback
capability allows onboard diagnostics. Independent
programmable baud rate generator is provided in
each channel to support data rates up to 3.125 Mbps.
• Intel or Motorola Bus Interface Select (16/68#)
pin
• Pin-to-pin compatible to XR16L2751CM
• Two Independent UARTs
■ Up to 3.125 Mbps at 5V, 2 Mbps at 3.3V, and 1
Mbps at 2.5V with external clock input
■ Up to 1.5 Mbps at 5V, 1.25 Mbps at 3.3V and 1
Mbps at 2.5V with crystal clock input
■ 16 bytes of Transmit and Receive FIFOs
■ Automatic RTS/CTS hardware flow control
■ Automatic Xon/Xoff software flow control
■ Wireless infrared encoder/decoder
■ Receive FIFO trigger levels select
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
• Battery Operated Instruments
• Data Port Adapters
■ Programmable character lengths (5, 6, 7 or 8)
with even, odd, forced or no parity
■ Full Modem Interface (CTS#, RTS#, DSR#,
• Handheld Appliances
• Radio Frequency Data Modems
• Base Stations
DTR#, RI#, CD#) in the 48-TQFP package
• Sleep Mode with PowerSave feature for battery
operation
• USB Hubs
• Industrial Temperature range
• Tiny 32-QFN, no lead package (5x5x0.9mm)
• 48-TQFP Package
• Industrial Automation Controls
FIGURE 1. XR16L2551 BLOCK DIAGRAM
2.25 to 5.5 Volt VCC
*5 Volt Tolerant Inputs
PwrSave
GND
A2:A0
D7:D0
UART Channel A
IOR# (VCC)
TXA, RXA,
RTSA#, CTSA#,
( DTR#, DSR#
CD#, RIA#, OP2A# )
IOW# (R/W#)
16 Byte TX FIFO
UART
CSA# (CS#)
CSB# (A3)
Regs
IR
ENDEC
TX & RX
BRG
INTA (IRQ#)
16 Byte RX FIFO
INTB (logic 0)
Intel or
Motorola
Data Bus
Interface
TXB, RXB,
UART Channel B
(same as Channel A)
RTSB#, CTSB#,
( DTRB#, DSRB#
CDB#, RIB#, OP2B# )
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
XTAL1
XTAL2
Crystal Osc/Buffer
Reset (Reset#)
16/68#
2551BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
FIGURE 2. PIN OUT ASSIGNMENT
D6
D7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RESET
RTSA#
INTA
INTB
A0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RESET# (Reset)
D6
D7
RTSA#
IRQ#
NC (INTB)
A0
RXB
RXA
RXB
XR16L2551
32-pin QFN in
16 (Intel) Mode
XR16L2551
32-pin QFN in
68 (Motorola) Mode
RXA
TXA
TXB
TXA
A1
A1
TXB
VCC
A2
CSA#
CSB#
A2
CS#
16/68#
A3 (CSB#)
16/68#
GND
1
2
3
4
5
6
36
35
34
33
32
31
30
29
28
27
26
25
RESET
D5
D6
1
2
3
4
5
36 RESET#
DTRB#
D5
D6
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
35
D7
D7
34 DTRA#
33 RTSA#
32 OP2A#
RXB
RXB
RXA
RXA
XR16L2551
48-pin TQFP
in 16 (Intel) Mode
XR16L2551
48-pin TQFP in
68 (Motorola) Mode)
RXRDYA#
TXRDYB#
TXA
TXRDYB#
TXA
6
31
7
7
30 IRQ#
29 NC
TXB
8
9
TXB
8
9
A0
27 A1
A2
25 NC
OP2B#
OP2B#
CS#
28
A1
10
CSA# 10
CSB# 11
A2
A3 11
PWRSAVE
12
26
NC
PWRSAVE 12
VCC
GND
ORDERING INFORMATION
OPERATING TEMPERATURE
RANGE
PART NUMBER
PACKAGE
DEVICE STATUS
XR16L2551IL
XR16L2551IM
32-Lead QFN
48-Lead TQFP
-40°C to +85°C
-40°C to +85°C
Active
Active
2
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LOW VOLTAGE DUART WITH POWERSAVE
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PIN DESCRIPTIONS
Pin Description
32-QFN
48-TQFP
PIN #
NAME
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
3
IO
Data bus lines [7:0] (bidirectional).
1
2
32
31
30
29
28
27
1
48
47
46
45
44
IOR#
14
19
15
I
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this
input becomes read strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], puts the data byte on the data bus
to allow the host processor to read it on the rising edge.
(VCC)
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
IOW#
12
When 16/68# pin is at logic 1, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the inter-
nal write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the address lines.
(R/W#)
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CSA#
(CS#)
7
8
10
11
I
I
When 16/68# pin is at logic 1, this input is chip select A (active low) to
enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active
low) for the Motorola bus interface.
CSB#
(A3)
When 16/68# pin is at logic 1, this input is chip select B (active low) to
enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface. Input
logic 0 selects channel A and logic 1 selects channel B.
INTA
22
30
O
When 16/68# pin is at logic 1 for Intel bus interface, this output
becomes channel A interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1.
INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3].
(IRQ#)
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An external
pull-up resistor is required for proper operation.
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Pin Description
32-QFN
PIN #
48-TQFP
PIN #
NAME
TYPE
DESCRIPTION
INTB
(NC)
21
29
O
When 16/68# pin is at logic 1 for Intel bus interface, this output
becomes channel B interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output is
not used and will stay at logic zero level. Leave this output uncon-
nected.
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. If it is
not used, leave it unconnected.
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
-
-
-
-
43
31
6
O
O
O
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. If it is not used, leave it
unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. If it is not used, leave it
unconnected.
18
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. If it is not used, leave it
unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
5
4
7
5
O
I
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSA#
CTSA#
DTRA#
DSRA#
23
25
-
33
38
34
39
O
I
UART channel A Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used.
O
I
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
-
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDA#
RIA#
-
-
40
41
I
I
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
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Pin Description
32-QFN
48-TQFP
PIN #
NAME
TYPE
DESCRIPTION
PIN #
OP2A#
-
32
O
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTA output functionality. If it is not used at all, leave it
unconnected.
TXB
RXB
6
3
8
4
O
I
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSB#
CTSB#
DTRB#
DSRB#
15
16
-
22
23
35
20
O
I
UART channel B Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used.
O
I
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
-
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDB#
RIB#
-
-
-
16
21
9
I
I
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
OP2B#
O
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
ANCILLARY SIGNALS
XTAL1
XTAL2
16/68#
10
11
17
13
14
24
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Intel or Motorola Bus Select.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate
in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
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Pin Description
32-QFN
PIN #
48-TQFP
PIN #
NAME
TYPE
DESCRIPTION
9
12
I
PwrSave
PowerSave (active high). This feature isolates the L2551’s data bus
interface from the host preventing other bus activities that cause higher
power drain during sleep mode. See Sleep Mode with Auto Wake-up
and PowerSave Feature section for details.
RESET
24
36
I
When 16/68# pin is at logic 1 for Intel bus interface, this input becomes
RESET (active high). When 16/68# pin is at logic 0 for Motorola bus
interface, this input becomes RESET# (active low).
(RESET#)
A 40 ns minimum active pulse on this pin will reset the internal registers
and all outputs of channel A and B. The UART transmitter output will be
held at logic 1, the receiver input will be ignored and outputs are reset
during reset period (see UART Reset Conditions).
VCC
GND
N.C.
26
13
-
42
17
Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.
Pwr Power supply common, ground.
12, 25, 37
No Connection. These pins are not connected internally. But if there is
a possibility of migrating to the XR16L2751 for future needs, please
refer to the XR16L2751 datasheet to determine if these pins should be
connected to VCC or GND.
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
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1.0 PRODUCT DESCRIPTION
The XR16L2551 (L2551) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
necessary for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to
form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The L2551 represents such an integration with greatly enhanced features. The L2551 is fabricated with an
advanced CMOS process.
Transmit and Receive FIFOs (16 Bytes each)
The L2551 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The L2551 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased performance is realized in the
L2551 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However with
the 16 byte FIFO in the L2551, the data buffer will not require unloading/loading for 1.53 ms. This increases the
service interval giving the external CPU additional time for other applications and reducing the overall UART
interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel environment. The
FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
Data Bus Interface, Intel or Motorola Type
The L2551 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the 16/68# pin (pin 24 for 48-TQFP package and pin 17 for 32-QFN
package).
Enhanced Features
The XR16L2551 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Its features set is compatible to the XR16L2550 device but offers Intel or Motorola data
bus interface and PowerSave to isolate the data bus interface during Sleep mode. Each UART is independently
controlled having its own set of device configuration registers. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Additionally, each UART channel has automatic RTS/CTS
hardware flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and
decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up
to 3.125 Mbps at 5V with a 50 MHz external clock.
The rich feature set of the L2551 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset (and operating in 16 or Intel Mode), the L2551 is functionally and software
compatible with the previous generation ST16C2450 and ST16C2550.
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2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2551 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs.
Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel
and Motorola mode is shown in Figure 3.
FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
2.25 to 5.5 Volt VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
UART
Channel A
RS-232 Serial Interface
A0
A1
A0
A1
A2
A2
RIA#
OP2A#
(no connect)
IOR#
IOR#
IOW#
IOW#
TXB
RXB
CSA#
CSB#
UART_CSA#
UART_CSB#
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
UART_INTA
UART_INTB
INTA
INTB
UART
Channel B
RS-232 Serial Interface
(no connect)
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RIB#
OP2B#
UART_RESET
RESET
GND
Intel Data Bus Interconnections
D0
D1
D2
D3
D4
D5
D6
D7
D0
2.25 to 5.5 Volt VCC
VCC
D1
D2
D3
TXA
RXA
D4
D5
D6
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
D7
UART
Channel A
RS-232 Serial Interface
A0
A1
A2
A0
A1
A2
A3
CSB#
RIA#
OP2A#
(no connect)
VCC
IOR#
IOW#
R/W#
TXB
RXB
CSA#
UART_CS#
VCC
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
UART
Channel B
UART_IRQ#
INTA
INTB
RS-232 Serial Interface
(no connect)
(no connect)
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RIB#
OP2B#
GND
UART_RESET#
RESET#
Motorola Data Bus Interconnections
2.2
5-Volt Tolerant Inputs
The L2551 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2551 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
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2.3
Device Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see Table 14). An active high pulse of at least 40 ns duration will be required to activate the
reset function in the device.
2.4
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the user to
select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART.
Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do
not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA#
CSB#
FUNCTION
1
0
1
0
1
1
0
0
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the L2551 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode. See Table 2.
Channel A and B Internal Registers
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS#
A3
FUNCTION
1
0
0
N/A
0
UART de-selected
Channel A selected
Channel B selected
1
Each UART channel in the L2551 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.5
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the L2551 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see Figure 20 through Figure 25.
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TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
FCR BIT-0=0
PINS
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 1
(FIFO DISABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
(DMA Mode Enabled)
RXRDY# A/B 0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
1 = at least 1 byte in FIFO.
2.6
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and Table 5 summarize the operating behavior for the transmitter and receiver. Also see Figure 20
through Figure 25.
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
FCR BIT-0 = 1
(FIFO DISABLED)
(FIFO ENABLED)
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
FCR BIT-0 = 1
(FIFO DISABLED)
(FIFO ENABLED)
INTA/B Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
2.7
Crystal Oscillator or External Clock Input
The L2551 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see “Programmable Baud
Rate Generator.”
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FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
Ω
0-120
(Optional)
R2
Ω
Ω
500 K - 1 M
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47 pF
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.8
Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
External Clock
vcc
XTAL1
gnd
VCC
R1
2K
XTAL2
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To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR
ON XTAL2 PIN TO INCREASE OPERATING SPEED
Operating frequency for XR16L2551
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
80
-40oC
25oC
70
60
85oC
50
40
30
3.0 3.5 4.0 4.5 5.0 5.5
Suppy Voltage
The L2551 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
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TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
DATA RATE
ERROR (%)
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
400
2304
384
192
96
48
24
12
6
900
180
C0
60
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
30
18
0C
06
4
04
2
02
1
01
2.9
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock.
A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line
Status Register (LSR bit-5 and bit-6).
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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2.9.3
Transmitter Operation in FIFO Mode
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
FIFO
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
16X Clock
Transmit Data Shift Register
(TSR)
TXFIFO1
2.10 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
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2.10.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register.
It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16
bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is
enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read,
the next character byte is loaded into the RHR and the errors associated with the current data byte are
immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example
:
- RX FIFO trigger level selected at 8 bytes
16 bytes by 11-bit
wide
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO
Data falls to 4
FIFO Trigger=8
Data fills to 14
Receive
Data FIFO
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Receive
Data
Receive Data
Byte and Errors
RXFIFO1
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2.11 Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features
is enabled to fit specific application requirement (see Figure 11):
- Enable auto RTS flow control using EFR bit-6.
- The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
- Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
- Enable auto CTS flow control using EFR bit-7.
- Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted
(logic 0), indicating more data may be sent.
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FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
TXB
Receiver FIFO
Trigger Reached
Transmitter
RTSA#
TXA
CTSB#
Auto RTS
Auto CTS
Trigger Level
Monitor
RXB
Receiver FIFO
Trigger Reached
Transmitter
CTSA#
RTSB#
Auto CTS
Monitor
Auto RTS
Trigger Level
Assert RTS# to Begin
Transmission
1
10
ON
ON
ON
RTSA#
OFF
7
2
ON
11
OFF
CTSB#
TXB
8
3
Restart
Data Starts
6
Suspend
9
4
RXA FIFO
Receive
Data
RX FIFO
Trigger Level
RTS High
Threshold
RTS Low
Threshold
5
RX FIFO
Trigger Level
12
INTA
(RXA FIFO
Interrupt)
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
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2.13 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 13), the L2551 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L2551 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L2551 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L2551 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 13) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the L2551 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L2551 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L2551 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level. To clear this condition, the L2551 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed
trigger level. See Table 7 below.
TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
RX TRIGGER LEVEL
INT PIN ACTIVATION
1
4
1
4
1*
4*
0
1
4
8
8
8
8*
14
14
14*
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.14
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L2551 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
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2.15 Infrared Mode
The L2551 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
1
1
1
1
1
0
0
0
0
0
TX Data
Transm it
IR Pulse
(TX Pin)
1/2 Bit Tim e
Bit Tim e
3/16 Bit Tim e
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
1
1
1
1
0
0
0
0
0
RX Data
Data Bits
Character
IRdecoder-1
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2.16
Sleep Mode with Auto Wake-Up and PowerSave Feature
The L2551 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave
feature is included to reduce power consumption when the device is not actively used.
2.16.1 Sleep Mode
All of these conditions must be satisfied for the L2551 to enter sleep mode:
■ no interrupts pending for both channels of the L2551 (ISR bit-0 = 1)
■ divisor is a non-zero value (ie. DLL = 0x1)
■ sleep mode of both channels are enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pins are idling at a logic 1
The L2551 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The L2551 resumes normal operation by any of the following when PowerSave mode is disabled (pin 12 at
ground):
■ a receive data start bit transition (logic 1 to 0)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the L2551 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the L2551 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The L2551 will stay in the sleep mode of operation until it is
disabled by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling at logic 1 or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
2.16.2 PowerSave Feature
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
L2551 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 37. If the input lines are floating or are toggling while the L2551 is in sleep mode, the
current can be up to 100 times more. If not using the PowerSave feature, then an external buffer would be
required to keep the address and data bus lines from toggling or floating to achieve the low current. But if the
PowerSave feature is enabled (pin 12 of the 48-TQFP or pin 9 of the 32-QFN is connected to VCC), this will
eliminate the need for an external buffer by internally isolating the address, data and control signals (see Figure
1 on page 1) from other bus activities that could cause wasteful power drain. The L2551 enters PowerSave
mode when the PWRSAVE pin is connected to VCC and the L2551 is in sleep mode (see Sleep Mode section
above).
Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:
■ a receive data start bit transition (logic 1 to 0)
■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
The L2551 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem
inputs) and all interrupting conditions have been serviced and cleared. The L2551 will stay in the PowerSave
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to
GND.
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2.17
Internal Loopback
The L2551 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during
loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also,
Auto RTS/CTS is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
RXA/RXB
VCC
RTSA#/RTSB#
RTS#
CTS#
CTSA#/CTSB#
VCC
DTRA#/DTRB#
DTR#
DSR#
DSRA#/DSRB#
OP1#
RI#
RIA#/RIB#
VCC
OP2A#/OP2B#
OP2#
CD#
CDA#/CDB#
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3.0 UART INTERNAL REGISTERS
Each of the UART channel in the L2551 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete
register set is shown on Table 8 and Table 9....INTERNAL Register descriptions
TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
Read-only
Write-only
LCR[7] = 0
THR - Transmit Holding Register
0
0
0
0
0 0
0 1
0 1
1 0
DLL - Div Latch Low Byte
Read/Write
Read/Write
Read/Write
LCR[7] = 1, LCR ≠ 0xBF
DLM - Div Latch High Byte
IER - Interrupt Enable Register
LCR[7] = 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR ≠ 0xBF
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
LCR ≠ 0xBF
1
1
1 0
1 1
MSR - Modem Status Register
Reserved
Read-only
Write-only
SPR - Scratch Pad Register
Read/Write
ENHANCED REGISTERS
0
1
1
1
1
1 0
0 0
0 1
1 0
1 1
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
LCR = 0xBF
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
LCR[7] = 0
Stat.
Int.
CTS Int. RTS Int. Xoff Int. Sleep
Enable Enable Enable
Mode
Enable
Enable Enable Enable Enable
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TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
0 1 0
ISR
RD
FIFOs
FIFOs
0/
0/
INT
INT
INT
INT
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3
Bit-2
Bit-1
Bit-0
Source Source
Bit-5
Bit-4
LCR ≠ 0xBF
0 1 0
0 1 1
FCR
WR RXFIFO RXFIFO
Trigger Trigger
0
0
DMA
Mode
TX
FIFO
RX
FIFOs
FIFO Enable
Enable Reset Reset
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
Break
ity
1 0 0
1 0 1
MCR RD/WR
0/
0/
0/
Internal OP2#/ Rsvd
RTS# DTR#
Output Output
Control Control
Loop-
back
INT
Output
(OP1#)
BRG
Pres-
caler
IR Mode XonAny
ENable
Enable Enable
LSR
RD
RD
RXFIFO THR &
Global
Error
THR
Empty
RX
RX
RX
RX
Over-
run
RX
Data
Ready
TSR
Empty
Break
Fram- Parity
LCR ≠ 0xBF
ing
Error
Error
Error
1 1 0
1 1 1
MSR
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
Delta
DSR# CTS#
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
0 0 1
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
LCR ≠ 0xBF
Enhanced Registers
Enable
0 1 0
EFR RD/WR
Auto
CTS
Enable Enable
Auto
RTS
Special
Char
Select
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
LCR=0XBF
1 0 0
1 0 1
1 1 0
1 1 1
XON1 RD/WR
XON2 RD/WR
XOFF1 RD/WR
XOFF2 RD/WR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 14.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 13.
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4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A.
B.
C.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2551 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A.
B.
C.
D.
E.
F.
LSR BIT-0 indicates there is data in RHR or RX FIFO.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
LSR BIT-5 indicates Transmit FIFO is empty.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
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IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
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4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
• RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from FIFO).
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
]
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
6
7
-
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
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These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 10).
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ISR[4]: Xoff or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR or when an Xon
character is received. If it is a special character interrupt, it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from low to high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of theTXRDY# and RXRDY# pins. See DMA operation section for details.
• Logic 0 = Normal Operation (default).
• Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 11 shows the complete selections.
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TABLE 11: RECEIVE FIFO TRIGGER LEVEL SELECTION
RECEIVE
TRIGGER
LEVEL
FCR BIT-7
FCR BIT-6
COMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
4
8
14
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
WORD LENGTH
STOP BIT LENGTH (BIT TIME(S))
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 12 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
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LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 12: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, “1”
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the L2551. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
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MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output. This bit does not affect the IRQ# output during Motorola mode.
• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the L2551 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is
overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the
FIFO, therefore the data in the FIFO is not corrupted by the error. An interrupt will be generated immediately
if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
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LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or logic 1. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit
shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose
inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
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MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally this bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to
the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem
interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. See
“Programmable Baud Rate Generator” on page 11. for more details.
4.12 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 13). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
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EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 13: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
0
X
X
X
X
0
0
1
1
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
1
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 to be modified.
After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature
prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 are
saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, and MCR bits 5-7are set to a
logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5. Special character interrupts are cleared automatically after the next
received character.
EFR[6]: Auto RTS Flow Control Enable
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RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected,
an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-
asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls below the
next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take effect. RTS#
pin will function as a general purpose output when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.13 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters XOFF1, XOFF2, XON1, and
XON2. For more details, see Table 7.
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TABLE 14: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
DLM
DLL
RESET STATE
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 3-0 = Logic 0
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
Bits 7-4 = Logic levels of the inputs
inverted
SPR
EFR
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
RESET STATE
Logic 1
XON1
XON2
XOFF1
XOFF2
I/O SIGNALS
TX
OP2#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RXRDY#
TXRDY#
INT
Logic 1
Logic 0
Three-State Condition
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LOW VOLTAGE DUART WITH POWERSAVE
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ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
7 Volts
GND-0.3 V to VCC+0.3 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (48-TQFP)
theta-ja = oC/W, theta-jc = oC/W
Thermal Resistance (32-QFN)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC IS 2.25 TO 5.5V
2.5V LIMITS
MIN MAX
3.3V LIMITS
MIN MAX
5.0V LIMITS
MIN MAX
SYMBOL
PARAMETER
UNITS
CONDITIONS
VILCK
VIHCK
VIL
Clock Input Low Level
Clock Input High Level
Input Low Voltage
-0.3
0.2
-0.3
0.6
-0.5
0.6
V
V
V
V
2.0
-0.3
2.0
5.5
0.6
5.5
2.4
-0.3
2.0
5.5
0.8
5.5
3.0
-0.5
2.2
5.5
0.8
5.5
0.4
VIH
Input High Voltage
Output Low Voltage
VOL
V
V
V
IOL = 6 mA
IOL = 4 mA
0.4
I
OL = 2 mA
0.4
VOH
Output High Voltage
2.4
V
V
V
IOH = -6 mA
IOH = -1 mA
2.0
I
OH = -400 uA
1.8
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
±10
±10
5
±10
±10
5
±10
±10
5
uA
uA
pF
CIN
ICC
Power Supply Current
1
1.3
15
3
mA
uA
ISLEEP
Sleep Current/
6
30
See Test 1
Powersave Current
IPWRSV
Test 1: The following inputs must remain steady at VCC or GND state to minimize sleep current: A0-A2, D0-D7,
IOR#, IOW# (R/W#), CSA# (CS#), CSB# (A3) and all modem inputs. Also, RXA and RXB inputs must idle at
logic 1 state while asleep. Floating inputs may result in sleep currents in the mA range. For Powersave, the
UART internally isolates all of these inputs therefore not requiring them to remain steady.
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LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC IS 2.25V TO 5.5V,
70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
3.3
LIMITS
SYMBOL
PARAMETER
2.5
5.0
UNIT
MIN
MAX
MIN
MAX MIN
MAX
-
Crystal Frequency
16
20
24
MHz
ns
CLK
OSC
TAS
External Clock Low/High Time
External Clock Frequency
31
17
10
16
30
50
MHz
ns
Address Setup Time (16 Mode)
10
10
10
10
75
75
75
10
10
50
50
50
TAH
TCS
TRD
TDY
Address Hold Time (16 Mode)
Chip Select Width (16 Mode)
IOR# Strobe Width (16 Mode)
Read Cycle Delay (16 Mode)
Data Access Time (16 Mode)
Data Disable Time (16 Mode)
IOW# Strobe Width (16 Mode)
Write Cycle Delay (16 Mode)
Data Setup Time (16 Mode)
Data Hold Time (16 Mode)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
150
150
TRDV
TDD
TWR
TDY
125
45
80
30
50
30
0
0
0
150
150
25
75
75
20
10
50
50
15
10
TDS
TDH
TADS
TADH
TRWS
TRDA
TRDH
TWDS
TWDH
TRWH
TCSL
TCSD
15
Address Setup (68 Mode)
Address Hold (68 Mode)
R/W# Setup to CS# (68 Mode)
Read Data Access (68 mode)
Read Data Disable (68 mode)
Write Data Setup (68 mode)
Write Data Hold (68 Mode)
R/W# Hold (68 Mode)
10
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
60
175
100
45
30
30
25
15
20
10
15
10
15
10
75
10
50
150
CS# Width (68 Mode)
150
75
50
CS# Cycle Delay (68 Mode)
Delay From IOW# To Output
TWDO
TMOD
TRSI
150
150
150
75
75
75
50
50
50
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
ns
ns
38
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.0.0
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC IS 2.25V TO 5.5V,
70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
3.3
LIMITS
5.0
SYMBOL
PARAMETER
2.5
UNIT
MIN
MAX
MIN
MAX MIN
MAX
TSSI
TRRI
TSI
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Stop To Interrupt
Delay From Initial INT Reset To Transmit Start
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
Delay From Center of Start To Reset TXRDY#
Reset Pulse Width
1
1
1
Bclk
ns
150
150
24
75
75
50
50
24
50
1
ns
TINT
TWRI
TSSR
TRR
TWT
TSRT
TRST
N
8
8
24
75
1
8
Bclk
ns
150
1
Bclk
ns
150
150
8
75
75
8
50
50
8
ns
Bclk
ns
40
1
40
1
40
1
Baud Rate Divisor
-
2
16-1
216-1
216-1
Bclk
Baud Clock
16X of data rate
Hz
FIGURE 14. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW #
Active
TWDO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
Change of state
Change of state
DSR#
TMOD
TMOD
INT
Active
Active
Active
Active
Active
TRSI
IOR#
Active
TMOD
Change of state
RI#
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING
A0-A2
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TDD
TRDV
TRDV
D0-D7
Valid Data
Valid Data
RDTm
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LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.0.0
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING
A0-A2
Valid Address
TCS
Valid Address
TAS
TAS
TAH
TCS
TAH
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDH
TDH
TDS
Valid Data
TDS
Valid Data
D0-D7
16Write
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING
Valid
Address
Valid
Address
A0-A3
TADS
CSL
T
ADH
T
CS#
R/W#
D0-D7
TCSD
RWS
T
TRWH
TRDH
RDA
T
Valid
Data
Valid
Data
68Read
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LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
Valid
Address
Valid
Address
A0-A3
TADS
TCSL
TADH
CS#
R/W#
D0-D7
TCSD
TRWS
TRWH
T
WDH
TWDS
Valid
Data
Valid
Data
68Write
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Active
Data
Active
Data
RXRDY#
Ready
Ready
Ready
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
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LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.0.0
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S
S
S
S
S
T
S
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
T
T
T
D0:D7
D0:D7
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
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LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start
Bit
Stop
Bit
RX
S
S
S
S
T
D0:D7
T
T
S
T
S
T
D0:D7
D0:D7
D0:D7
D0:D7
TSSI
D0:D7
D0:D7
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
S
T
D0:D7
D0:D7
T
S
D0:D7
T
D0:D7
T
D0:D7
T
S
D0:D7
T
TSRT
IER[1]
enabled
ISR is read
TX FIFO no
longer empty
INT*
TSI
TWRI
TX FIFO
Empty
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
44
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.0.0
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
T
D0:D7
S
T
S
D0:D7
D0:D7
T
S D0:D7
T
D0:D7
T
D0:D7
T
IER[1]
enabled
ISR is read
TSRT
TX FIFO no
longer empty
TSI
INT*
TWRI
TX FIFO
Empty
At least 1
empty location
in FIFO
TX FIFO
Full
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA
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LOW VOLTAGE DUART WITH POWERSAVE
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REV. 1.0.0
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D1
36
25
37
24
D1
D
48
13
1
1
2
B
e
A2
C
A
Seating
Plane
α
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
MAX
1.20
0.15
1.05
0.27
0.20
9.20
7.10
A
0.039
0.002
0.037
0.007
0.004
0.346
0.272
0.047
0.006
0.041
0.011
0.008
0.362
0.280
1.00
0.05
0.95
0.17
0.09
8.80
6.90
1
A
A
2
B
C
D
1
D
e
L
α
0.020 BSC
0.50 BSC
0.018
0.030
0.45
0.75
°
0
°
7
°
°
7
0
46
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.0.0
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
D2
D
D
D2
L
b
e
A1
Steating Plane
A
A3
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
0.80
0.00
0.15
4.90
3.50
0.18
MAX
1.00
0.05
0.25
5.10
3.80
0.30
A
A1
A3
D
0.031
0.000
0.006
0.193
0.138
0.007
0.039
0.002
0.010
0.201
0.150
0.012
D2
b
e
0.0197 BSC
0.014 0.018
0.050 BSC
L
0.35
0.45
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XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
áç
REV. 1.0.0
REVISION HISTORY
Date
Revision
Description
Preliminary Datasheet.
November 2002 P1.0.0
Updated AC Electrical Characteristics. Updated register set with enhanced fea-
tures.
March 2003
P1.0.1
Added patent number to first page. Added 32 pin QFN package dimensions.
Added Device Status to Ordering Information.
May 2003
June 2003
July 2003
P1.0.2
P1.0.3
P1.0.4
Updated AC Electrical Characteristics.
Final Production Release. Updated 5V tolerance information.
September 2003 1.0.0
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet September 2003.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
48
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