XR16L570IL24-F [EXAR]
Serial I/O Controller, 1 Channel(s), 0.5MBps, CMOS, 4 X 4 MM, 0.90 MM HEIGHT, GREEN, QFN-24;型号: | XR16L570IL24-F |
厂家: | EXAR CORPORATION |
描述: | Serial I/O Controller, 1 Channel(s), 0.5MBps, CMOS, 4 X 4 MM, 0.90 MM HEIGHT, GREEN, QFN-24 微控制器和处理器 串行IO控制器 通信控制器 外围集成电路 先进先出芯片 数据传输 时钟 |
文件: | 总46页 (文件大小:1060K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
DECEMBER 2005
REV. 1.0.0
FEATURES
GENERAL DESCRIPTION
• Smallest Full Featured UART
• 1.62V to 5.5V Supply Voltage
• 5V Tolerant Inputs (except XTAL1/CLK)
• ’0 ns’ Address Hold Time (TAH and TADH
• Software Compatible to industry standard 16C450,
16C550, ST16C580, ST16C650A, XR16C850 and
XR16L580
The XR16L570 (L570) is a 1.62 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with 5 volt
tolerant inputs and a reduced pin count. It is software
compatible to industry standard 16C450, 16C550,
ST16C580, ST16C650A, XR16C850 and XR16L580
UARTs. It has 16 bytes of TX and RX FIFOs and is capable
of operating with a serial data rate of up to 4 Mbps at 5V, 3
Mbps at 3.3V,1 Mbps at 2.5V and 750 Kbps at 1.8V. The
internal registers are compatible to the 16C550 register set
plus enhanced registers for additional features to support
today’s high bandwidth data communication needs. The
)
• 16-byte Transmit FIFO
• 16-byte Receive FIFO with Errors Flags
• Selectable RX and TX FIFO Trigger Levels
• Automatic Hardware (RTS/CTS) Flow Control
• Automatic Software (Xon/Xoff) Flow Control
• Up to 4 Mbps data rate at 5.0V Operation
• Up to 3 Mbps data rate at 3.3V Operation
• Up to 1 Mbps data rate at 2.5V Operation
• Up to 750 Kbps data rate at 1.8V Operation
• Infrared (IrDA) Encoder/Decoder
enhanced features include
automatic hardware and
software flow control to prevent data loss, selectable RX
and TX trigger levels for more efficient interrupt service,
wireless infrared (IrDA) encoder/decoder for wireless
applications and a unique Power-Save mode to increase
battery operating time. The device comes in 32-QFN and
24-QFN packages in industrial temperature range.
APPLICATIONS
• Handheld Terminals and Tablets
• Handheld Computers
• Wireless Portable Point-of-Sale Terminals
• Cellular Phones DataPort
• GPS Devices
• Personal Digital Assistants Modules
• Battery Operated Instruments
• Complete Modem Interface
• Power-Save Mode to conserve battery power
• Sleep Mode with Wake-up Interrupt
• Very small packages: 24-QFN (4x4x0.9mm) and 32-QFN
(5x5x0.9mm)
• Industrial Temperature Grade(-40 to +85oC)
FIGURE 1. BLOCK DIAGRAM
VCC
(1.62 to 5.5 V)
*5 V Tolerant Inputs
(Except for CLK)
PwrSave
A2:A0
GND
D7:D0
IOR#
UART
TX
RX
IOW#
CS#
16 Byte TX FIFO
RTS#
CTS#
DTR#
DSR#
CD#
RI#
UART
Regs
IR
TX & RX
ENDEC
INT
Data Bus
Interface
RESET
16 Byte RX FIFO
Clock Buffer
BRG
XTAL1 (CLK)
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16L570
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
FIGURE 2. PACKAGE AND PIN OUT (24-PIN QFN PACKAGE)
24
23
22 21 20 19 18
32-pin QFN
17
NC
DSR# 25
16
15
14
13
12
11
10
9
18 17 16 15 14 13
CD#
RI#
VCC
D0
26
27
28
29
30
31
NC
VCC
D0
A2
19
12
IOR#
GND
IOW#
XTAL2
XTAL1
NC
IOR#
20
11
D1 21
D2 22
10 GND
24-pin QFN
9
8
7
IOW#
D1
D2
23
24
D3
D4
CLK
PwrSave
32
D3
1
2
3
4
5
6
7
3 4 5 6
8
2
1
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XR16L570IL24
24-pin QFN
32-pin QFN
XR16L570IL32
-40°C to +85°C
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Descriptions
24-QFN 32-QFN
NAME
TYPE
DESCRIPTION
PIN#
PIN#
DATA BUS INTERFACE
A2
A1
A0
12
13
14
17
18
19
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
the UART during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
3
5
4
I/O
Data bus lines [7:0] (bidirectional).
2
1
3
24
23
22
21
20
1
32
31
30
29
IOR#
11
14
I
I
This input is the read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it
on the rising edge.
IOW#
9
12
This input is the write strobe (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
INT
6
8
I
This input is chip select (active low) to enable the device.
15
20
O
This output is the active high device interrupt output. The output state is defined by
the user through the software setting of MCR[3]. INT is set to the active mode when
MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a
logic 0. See MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX
5
7
O
UART Transmit Data or infrared encoder data. Standard transmit and receive inter-
face is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during
reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when
MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it unconnected.
RX
4
6
I
O
I
UART Receive Data or infrared receive data. Normal receive data input must idle at
logic 1 condition. The infrared receiver idles at logic 0.
RTS#
CTS#
16
18
21
24
UART Request-to-Send (active low) or general purpose output. This output must be
asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can be used for auto
CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to
VCC when not used.
DTR#
DSR#
-
-
22
25
O
I
UART Data-Terminal-Ready (active low) or general purpose output. This pin is not
available in the 24-QFN package.
UART Data-Set-Ready (active low) or general purpose input. This input should be
connected to VCC when not used. This input has no effect on the UART. This pin is
not available in the 24-QFN package.
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XR16L570
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
Pin Descriptions
24-QFN 32-QFN
NAME
TYPE
DESCRIPTION
PIN#
PIN#
CD#
-
26
I
UART Carrier-Detect (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART. This pin is not
available in the 24-QFN package.
RI#
-
27
I
UART Ring-Indicator (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART. This pin is not
available in the 24-QFN package.
ANCILLARY SIGNALS
XTAL1
(CLK)
8
10
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
-
11
O
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s). This pin is not available in the 24-QFN package.
PwrSave
7
-
I
Power-Save (active high). This feature isolates the L570’s data bus interface from
the host preventing other bus activities that cause higher power drain during sleep
mode. See Sleep Mode with Auto Wake-up and Power-Save Feature section for
details. This pin is not available in the 28-QFN package.
RESET
17
23
I
This input is the active high RESET signal.
A 40 ns minimum active pulse on this pin will reset the internal registers and all out-
puts of the UART. The UART transmitter output will be held at logic 1, the receiver
input will be ignored and outputs are reset during reset period (see UART Reset Con-
ditions).
VCC
GND
GND
19
10
28
13
Pwr
Pwr
1.62V to 5.5V power supply. All input pins, except CLK, are 5V tolerant.
Power supply common, ground.
Center Center Pwr
Pad Pad
The center pad on the backside of the QFN packages is metallic and should be con-
nected to GND on the PCB. The thermal pad size on the PCB should be the approxi-
mate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
1.0 PRODUCT DESCRIPTION
The XR16L570 (L570) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its
features set is compatible to the ST16C580 device and additionally offers Power-Save to isolate the data bus
interface during Sleep mode. The XR16L570 can operate from 1.62V to 5.5V with 5 volt tolerant inputs. The
configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L570 has
16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L570 is fabricated
using an advanced CMOS process.
Enhanced Features
The L570 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L570 is
designed to work with low supply voltage and high performance data communication systems, that require fast
data processing time. Increased performance is realized in the L570 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time. In addition, the L570 provides the
Power-Save mode that drastically reduces the power consumption when the device is not used. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface
The L570 provides a host interface that supports a microprocessor (CPU) data bus interface. The interface
allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CS# inputs for data bus
operation. See pin description section for details on all the control signals.
Data Rate
The L570 is capable of operation up to 4 Mbps at 5V, 3 Mbps at 3.3V, 1 Mbps at 2.5V and 750 Kbps at 1.8V
with 16X internal sampling clock rate by using an external clock source on the XTAL1 (CLK) pin.
Internal Enhanced Register Sets
The L570 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable,
modem interface controls and status, sleep mode and Power-Save mode (in the 24-QFN package) are all
standard features. Following a power on reset or an external reset, the registers defaults to the reset condition
and it is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16L580, 16C650A and
16C850.
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L570 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# inputs. A typical data bus
interconnection is shown in Figure 3.
FIGURE 3. XR16L570 TYPICAL DATA BUS INTERCONNECTIONS
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TX
RX
Serial Interface of
RS-232 or RS-422
A0
A1
A2
A0
A1
A2
RTS#
CTS#
IOR#
IOW#
IOR#
IOW#
CS#
UART_CS#
UART_INT
INT
PwrSave
GND
UART_RESET
RESET
Data Bus Interconnections
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REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.2
5-Volt Tolerant Inputs
The L570 can accept up to 5V inputs when operating at 3.3V, 2.5V or 1.8V. But note that if the L570 is
operating at 2.5V or below, its V may not be high enough to meet the requirements of the V of a CPU or a
OH
IH
serial transceiver that is operating at 5V. Note that the XTAL1 (CLK) pin is not 5V tolerant.
2.3
Device Hardware Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 11). An active pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.4
Device Identification and Revision
The XR16L570 provides a Device Identification code and a Device Revision code. To read the identification
code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now
reading the content of the DLM will provide 0x01 to indicate XR16L570 and reading the content of DLL will
provide the revision of the part; for example, a reading of 0x01 means revision A.
2.5
Internal Registers
The L570 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad
register (SPR).
Beyond the general 16C550 features and capabilities, the L570 offers enhanced feature registers (EFR, Xon1,
Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
REGISTERS” on page 19.
2.6
DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR16L570. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.7
INT Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and
Table 2 below summarize the operating behavior for the transmitter and receiver. Also see Figures 18
through 21.
TABLE 1: INT PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
0 = one byte in THR
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
1 = THR empty
TABLE 2: INT PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
FCR BIT-0 = 1
(FIFO DISABLED)
(FIFO ENABLED)
INT Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
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XR16L570
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
2.8
Crystal or External Clock Input
The L570 includes an on-chip oscillator in the 32-QFN package (XTAL1 and XTAL2) to generate a clock when
a crystal is connected between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be
supplied through the XTAL1 or CLK pin. The CPU data bus does not require this clock for bus operation. The
crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the XTAL1 input is not 5V tolerant and therefore, the maximum
voltage at that pin should be VCC when an external clock is supplied. For programming details, see “Section
2.9, Programmable Baud Rate Generator” on page 9.
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2
R1
0-120
(Optional)
R2
500K - 1M
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47pF
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). When VCC = 5V, the on-
chip oscillator can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the
L570 can accept an external clock of up to 64MHz at XTAL1 pin, with a 2K ohms pull-up resistor on XTAL2 pin
(as shown in Figure 5). The 2K ohms pull-up resistor may be required for external clock frequencies of greater
than 24MHz. This translates to a maximum of 4Mbps serial data rate at 5V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
E xternal C lock
vcc
XTA L1
gnd
V C C
R 1
2K
XTA L2
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.9
Programmable Baud Rate Generator
The L570 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input external clock by a
factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
16
programmable divisor (via DLL and DLM registers) between 1 and (2 -1) to obtain a 16X sampling rate clock
of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for
data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power
up.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
DLL and DLM
Registers
MCR Bit-7=0
(default)
Prescaler
Divide by 1
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
Clock
Buffer
CLK
Prescaler
Divide by 4
MCR Bit-7=1
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz external clock at 16X
sampling rate clock rate. When using a non-standard data rate external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
divisor (decimal) = (clock frequency / prescaler) / (serial data rate x 16)
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XR16L570
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
DLM
PROGRAM
VALUE (HEX) VALUE (HEX)
DLL
PROGRAM
DATA RATE
ERROR (%)
DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
MCR Bit-7=1
MCR Bit-7=0
(DEFAULT)
100
600
400
2304
384
192
96
48
24
12
6
900
180
C0
60
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
2400
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
30
18
0C
06
4
04
2
02
1
01
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
2.10.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
THR Interrupt (ISR bit-1):
Transmit
FIFO
Transmit
Data Byte
- When the TX FIFO falls below the
programmed Trigger Level, and
- When the TX FIFO becomes empty.
Auto CTS Flow Control (CTS# pin)
FIFO is Enabled by FCR bit-0=1
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
Auto Software Flow Control
16X Clock
Transmit Data Shift Register
(TSR)
TXFIFO1
2.11 RECEIVER
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the falling edge of a
start or a false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated as a start bit. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Each of the data, parity and stop bits is sampled at the middle of the bit to prevent false framing. If
there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
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2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example
:
RX FIFO trigger level selected at 8 bytes
16 bytes by 11-bit
wide
Data falls to
RTS# re-asserts when data falls below the flow
FIFO
4
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
Data FIFO
FIFO Trigger=8
FIFO is Enabled by FCR bit-0=1
Data fills to
14
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data
Receive Data
Byte and Errors
RXFIFO1
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2.12
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.13
Auto RTS Hysteresis
The L570 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the ST16C550 UART. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed RX trigger level. The RTS# pin will not be forced to a logic 1 (RTS off), until the
receive FIFO reaches one trigger level above the programmed trigger level in the trigger table (Table 8). The
RTS# pin will return to a logic 0 after the RX FIFO is unloaded to one trigger level lower than the programmed
trigger level. This is described in Figure 11. Under the above described conditions, the L570 will continue to
accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is
asserted to a logic 0 (RTS On).
2.14
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
• Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
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FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
TXB
Receiver FIFO
Trigger Reached
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto RTS
Trigger Level
Auto CTS
Monitor
Receiver FIFO
Trigger Reached
Transmitter
CTSA#
RTSB#
Auto CTS
Monitor
Auto RTS
Trigger Level
Assert RTS# to Begin
Transmission
1
10
11
ON
ON
ON
RTSA#
OFF
OFF
7
2
ON
3
CTSB#
TXB
8
Restart
9
Data Starts
6
Suspend
4
RXA FIFO
Receive
Data
RX FIFO
Trigger Level
RTS High
Threshold
RTS Low
Threshold
5
RX FIFO
Trigger Level
12
INTA
(RXA FIFO
Interrupt)
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
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2.15
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 10), the L570 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L570 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L570 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L570 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 10) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the L570 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L570 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L570 sends the
Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level. To clear this condition, the L570 will transmit the
programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed
trigger level (see Table 8). The table below describes this.
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
RX TRIGGER LEVEL
INT PIN ACTIVATION
1
4
1
4
1*
4*
0
1
4
8
8
8
8*
14
14
14*
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.16
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L570 compares each incoming receive character with the programmed Xoff-2 data. If a match exists, the
received data will be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special
character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character
information, the actual number of bits is dependent on the programmed word length. Line Control Register
(LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length
selected by LCR bits 0-1 also determines the number of bits that will be used for the special character
comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.
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2.17 Infrared Mode
The L570 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the L570 has a provision to invert
the input polarity to accommodate this. In this case, the user can enable MCR bit-2 to invert the IR signal at the
RX pin.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
1
1
1
1
1
0
0
0
0
0
TX Data
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
1
1 1
1
0
0
0
0
0
RX Data
Data Bits
Character
IRdecoder-
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2.18
Sleep Mode with Wake-Up Interrupt and Power-Save Feature
The L570 supports low voltage system designs, hence, a sleep mode with wake-up interrupt and Power-Save
feature is included to reduce power consumption when the device is not actively used.
2.18.1 Sleep Mode
All of these conditions must be satisfied for the L570 to enter sleep mode:
■ no interrupts pending (ISR bit-0 = 1)
■ the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pin is idling at a logic 1
The L570 resumes normal operation by any of the following:
■ a receive data start bit transition (HIGH to LOW)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on the modem or general purpose serial input CTS#
If the L570 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator
circuit is up and running and the device is ready to transmit/receive. This interrupt has the same encoding (bit-
0 of ISR register = 1) as "no interrupt pending" and will clear when the ISR register is read. This will show up in
the ISR register only if no other interrupts are enabled. The L570 will return to the sleep mode automatically
after all interrupting conditions have been serviced and cleared. If the L570 is awakened by the modem input
CTS#, a read to the MSR is required to reset the modem input. In any case, the sleep mode will not be entered
while an interrupt is pending. The L570 will stay in the sleep mode of operation until it is disabled by setting IER
bit-4 to a logic 0.
2.18.2 Power-Save Feature
If the address lines, data bus lines, IOW#, IOR#, CS# and modem input lines remain steady when the L570 is
in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 34. If the input lines are floating or are toggling while the L570 is in sleep mode, the
current can be up to 100 times more. If not using the Power-Save feature, an external buffer would be required
to keep the address and data bus lines from toggling or floating to achieve the low current. But if the Power-
Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by
internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that
could cause wasteful power drain. The L570 enters Power-Save mode when this pin is connected to VCC and
the L570 is in sleep mode (see Sleep Mode section above).
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■ a receive data start bit transition (HIGH to LOW) at the RX input or
■ a change of logic state on the modem or general purpose serial input CTS#
The L570 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem input
CTS#) and all interrupting conditions have been serviced and cleared. The L570 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND. The Power-Save feature is only available in the 24-QFN package only.
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2.19
Internal Loopback
The L570 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally
including automatic hardware and software flow control. Figure 13 shows how the modem port signals are re-
configured. The general purpose outputs OP1#, OP2#, the modem output DTR# and the modem inputs DSR#,
RI# and CD# are not available in the 24-QFN package of the L570. However, in internal loopback mode, the
DTR#, OP1# and OP2# bits in the MCR register, control the DSR#, RI# and CD# bits in the MSR register
respectively. Transmit data from the transmit shift register output is internally routed to the receive shift register
input allowing the system to receive the same data that it was sending. The TX pin is held HIGH while RTS# is
de-asserted, and CTS# input is ignored. Caution: the RX input pins must be held HIGH during loopback test
else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 13. INTERNAL LOOP BACK
VCC
TX
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
RX
VCC
RTS#
RTS#
CTS#
CTS#
VCC
DTR#
DTR#
DSR#
DSR#
OP1#
RI#
RI#
OP2#
CD#
CD#
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3.0 UART INTERNAL REGISTERS
The L570 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The
complete register set is shown on Table 5 and Table 6.
TABLE 5: UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
Read-only
Write-only
LCR[7] = 0
LCR[7] = 1
THR - Transmit Holding Register
0
0 0
0 1
0 0
0 1
0 1
1 0
DLL - Div Latch Low Byte
Read/Write
Read/Write
Read-only
Read-only
Read/Write
0
0
0
0
0
DLM - Div Latch High Byte
DREV - Device Revision Code
DVID - Device Identification Code
IER - Interrupt Enable Register
DLL, DLM = 0x00,
LCR[7] = 1
LCR[7] = 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR ≠ 0xBF
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
LCR ≠ 0xBF
LCR ≠ 0xBF
1
1
1 0
1 1
MSR - Modem Status Register
Reserved
Read-only
Write-only
SPR - Scratchpad Register
Read/Write
ENHANCED REGISTERS
0
1
1
1
1
1 0
0 0
0 1
1 0
1 1
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
LCR = 0xBF
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.
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat. Int.
Enable
TX
Empty
Int
RX
Data
Int.
LCR[7]=0
Stat.
Int.
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Enable Enable Enable
0 1 0
ISR
RD
FIFOs
FIFOs
0/
0/
INT
INT
INT
INT
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3
Bit-2
Bit-1
Bit-0
Source Source
Bit-5
Bit-4
LCR ≠ 0xBF
0 1 0
FCR
WR RXFIFO RXFIFO
Trigger Trigger
0/
0/
DMA
Mode
Enable
TX
FIFO
Reset Reset
RX
FIFOs
FIFO Enable
TXFIFO TXFIFO
Trigger Trigger
0 1 1
1 0 0
LCR RD/WR Divisor Set TX Set Par-
Even
Parity
Parity
Enable
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
Break
ity
MCR RD/WR
0/
0/
0/
Internal INT Out- (OP1#) RTS# DTR#
Loop-
back
Enable
put
Enable
Output Output
Control Control
BRG
Pres-
caler
IR Mode XonAny
ENable
Invert
IR RX
(OP2#)
1 0 1
LSR
RD
RD
RX FIFO THR &
THR
Empty
RX
Break
RX Fram-
ing Error Parity Over-
RX
RX
RX
Data
Ready
LCR ≠ 0xBF
Global
Error
TSR
Empty
Error
run
Error
1 1 0
1 1 1
MSR
CD#
RI#
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
Input
Input
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR ≠ 0xBF
Baud Rate Generator Divisor
LCR[7]=1
0 0 0
0 0 1
0 0 0
0 0 1
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-7
0
Bit-6
Bit-6
Bit-6
0
Bit-5
Bit-5
Bit-5
0
Bit-4
Bit-4
Bit-4
0
Bit-3
Bit-3
Bit-3
0
Bit-2
Bit-2
Bit-2
0
Bit-1
Bit-1
Bit-1
0
Bit-0
Bit-0
Bit-0
1
DREV
DVID
RD
RD
LCR[7]=1
DLL=0x00
DLM=0x00
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TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
Enhanced Registers
Enable
0 1 0
EFR RD/WR
Auto
CTS
Enable Enable
Auto
RTS
Special
Char
Select
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
MCR[2]
Bit-2
Bit-1
Bit-0
Bit-3
LCR=0XBF
1 0 0
1 0 1
1 1 0
1 1 1
XON1
XON2
WR
WR
WR
WR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
XOFF1
XOFF2
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 11.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 10.
4.3 Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 9.
4.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
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4.4.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L570 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is ready to be
read out of the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
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IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
• RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
• Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
4.5.2
Interrupt Clearing:
• LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s)
that generated the interrupt(s) is (are) read from the FIFO).
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading the RHR register.
• TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
• MSR interrupt is cleared by reading the MSR register.
• Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
• Special character interrupt is cleared by reading the ISR or after the next character is received.
• RTS# and CTS# flow control interrupts are cleared by reading the MSR register.
• Wake-up interrupt is cleared by reading the ISR register.
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TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
6
7
-
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default) or Wake-up Interrupt
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition) or wake-up interrupt. The wake-up interrupt is issued when
the L570 has been awakened from sleep mode.
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
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FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select (Legacy)
This bit has no function and should be left at ’0’.
FCR[5:4]: Transmit FIFO Trigger Select
(’00’ = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 8 below shows the selections. EFR bit-4 must
be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(’00’ = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 8 shows the selections.
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
RECEIVE
TRANSMIT
COMPATIBILITY
BIT-4 TRIGGER LEVEL TRIGGER LEVEL
0
0
1
1
0
1
0
1
1 (default)
16C580 and 16L580 compati-
ble.
4
8
14
0
0
1
1
0
1
0
1
1 (default)
16C550, 16C580, 16L580,
16C554, 16C2550 and 16C2552
compatible
4
8
14
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
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LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
STOP BIT LENGTH
(BIT TIME(S))
WORD
LENGTH
BIT-2
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 9 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 9: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, “1”
Forced parity to space, “0”
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LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is not available in the 24-QFN package of the L570. This bit is used to control the status of the
DSR bit in the MSR register in the internal loopback mode.
• Logic 0 = Set DTR bit to be 0 (default)
• Logic 1 = Set DTR bit to be 1.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Invert Infrared RX Data or OP1# (legacy term)
If IrDA mode is enabled by setting MCR[6]=1 and if EFR[4] = 1, this bit acts as ’Invert Infrared RX data’
command. If EFR[4] = 0 or in internal loopback mode, this bit functions like the OP1# in the 16C550.
• Logic 0 = Select RX input as active-low encoded IrDA data (if IrDA Mode is enabled by setting MCR[6] = 1
and EFR[4] = 1) (default).
• Logic 1 = Select RX input as active-high encoded IrDA data (if MCR[6] = 1 and EFR[4] = 1). In this mode, this
bit is write-only.
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in Figure 13.
MCR[3]: INT Output Enable or OP2# (legacy term)
This bit enables and disables the operation of interrupt output.
• Logic 0 = INT output disabled (three state mode) (default).
• Logic 1 = INT output enabled (active mode).
In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the
modem input CD# bit in the MSR register.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
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MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the L570 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
MCR[7]: BRG Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the external clock is fed directly to the Programmable Baud
Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the external clock by four and feeds it to
the Programmable Baud Rate Generator, hence, data rates get reduced 4 times.
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
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LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.10 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Since the 24-QFN package of the L570 does not have the DSR# modem input, this bit has functionality only in
internal loopback mode when the DSR bit (MSR[4]) can be controlled via the DTR bit (MCR[0]).
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Since the 24-QFN package of the L570 does not have the RI# modem input, this bit has functionality only in
internal loopback mode when the RI bit (MSR[6]) can be controlled via the OP1# bit (MCR[2]).
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Since the 24-QFN package of the L570 does not have the CD# modem input, this bit has functionality only in
internal loopback mode when the CD bit (MSR[7]) can be controlled via the OP2# bit (MCR[3]).
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the
MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.
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MSR[5]: DSR Input Status
Normally MSR bit-5 is the complement of the DSR# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the DTR# bit (MCR[0]). The 24-QFN package of the L570 does not have the DSR#
modem input.
MSR[6]: RI Input Status
Normally MSR bit-6 is the complement of the RI# input in the 32-QFN package. In internal loopback mode, this
bit is equivalent to the OP1# bit (MCR[2]). The 24-QFN package of the L570 does not have the RI# modem
input.
MSR[7]: CD Input Status
Normally MSR bit-5 is the complement of the CD# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the OP2# bit (MCR[3]). The 24-QFN package of the L570 does not have the CD#
modem input.
4.11 Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x01 for XR16L570). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.14 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.15
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 10). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
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TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
1
0
1
0
X
X
X
X
0
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
0
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
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EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at one trigger level above the programmed trigger level. RTS# will return to a logic
0 when FIFO data falls below one trigger level below the programmed trigger level. The RTS# output must be
asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output
when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.16 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, refer to “Section 2.15, Auto Xon/Xoff (Software) Flow Control” on page 15.
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TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
RESET STATE
DLM and DLL
Bits 15-0 = 0x0001. Resets upon power up only and not when only
the Reset Pin is asserted.
RHR
THR
IER
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
FCR
ISR
LCR
MCR
LSR
MSR
Bits 7-5, 3-0 = Logic 0
Bits 4 = Logic level of the CTS# input inverted
SPR
EFR
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
RESET STATE
HIGH
XON1
XON2
XOFF1
XOFF2
I/O SIGNALS
TX
RTS#
HIGH
DTR#
HIGH
INT
Three-State Condition
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
7 Volts
GND-0.3 V to 7 V
o
o
Operating Temperature
-40 to +85 C
o
o
Storage Temperature
Package Dissipation
-65 to +150 C
500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
o
o
Thermal Resistance (24-QFN)
Thermal Resistance (32-QFN)
theta-ja = 38 C/W, theta-jc = 26 C/W
o
o
theta-ja = 33 C/W, theta-jc = 22 C/W
33
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= -40O TO +85OC, VCC=2.97 - 5.5V
LIMITS
LIMITS
5.0V
SYMBOL
PARAMETER
3.3V
UNITS
CONDITIONS
MIN
MAX
MIN
MAX
V
Clock Input Low Level
-0.3
0.6
-0.5
0.6
VCC
0.8
V
V
V
V
ILCK
V
Clock Input High Level
Input Low Voltage
Input High Voltage
Output Low Voltage
2.4
-0.3
2.0
VCC
0.8
3.0
-0.5
2.2
IHCK
V
IL
V
5.5
5.5
IH
V
0.4
V
V
I
I
= 6 mA
= 4 mA
OL
OL
OL
0.4
V
Output High Voltage
2.4
V
V
I
I
= -6 mA
= -1 mA
OH
OH
OH
2.0
I
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
±10
±10
5
±10
±10
5
uA
uA
pF
IL
I
IH
C
IN
I
Power Supply Current
2
3
mA
uA
CC
I
/I
Sleep / Power-Save Current
15
30
See Test
SLEEP PWRSV
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= -40O TO +85OC, VCC=1.62 - 2.75V
LIMITS
1.8V
LIMITS
SYMBOL
PARAMETER
2.5V
UNITS
CONDITIONS
MIN
-0.3
1.4
MAX
MIN
MAX
V
Clock Input Low Level
0.3
VCC
0.2
-0.3
0.6
V
V
V
V
ILCK
V
Clock Input High Level
Input Low Voltage
Input High Voltage
Output Low Voltage
1.8
-0.3
1.8
VCC
0.5
IHCK
V
-0.3
1.4
IL
V
5.5
5.5
IH
V
0.4
V
V
I
I
= 2 mA
OL
OL
OL
0.4
= 1.5 mA
V
Output High Voltage
1.8
V
V
I
I
= -400 uA
= -200 uA
OH
OH
OH
1.4
I
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
Power Supply Current
Sleep Current
±10
±10
5
±10
±10
5
uA
uA
pF
IL
I
IH
C
IN
I
0.5
3
1
mA
uA
CC
I
/I
6
See Test
SLEEP PWRSV
Test: The following inputs must remain steady at VCC or GND state to minimize sleep current: A0-A2, D0-D7, IOR#, IOW#,
CS# and all modem inputs. Also, RX input must idle at logic 1 state while asleep. Floating inputs may result in sleep
currents in the mA range.
For PowerSave, the UART internally isolates all of these inputs (except the modem input CTS# and Reset pins) therefore
eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWER-SAVE FEATURE” ON PAGE 17. To
achieve minimum power drain, the voltage at any of the inputs of the L570 should NOT be lower than its VCC supply.
34
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= -40O TO +85OC, VCC=2.97 - 5.5V, 70 PF LOAD WHERE APPLICABLE
LIMITS
3.3
LIMITS
SYMBOL
PARAMETER
5.0
UNIT
MIN
MAX MIN
MAX
24
-
Crystal Oscillator Frequency
20
33
MHz
MHz
ns
OSC
CLK
External Clock Frequency*
External Clock Low/High Time*
Address Setup Time
50
15
5
10
T
10
0
ns
AS
T
Address Hold Time
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bclk
ns
ns
Bclk
ns
ns
-
AH
T
T
T
Chip Select Width
50
50
50
30
30
30
CS
RD
DY
IOR# Strobe Width
Read Cycle Delay
T
Data Access Time
50
20
25
20
RDV
T
Data Disable Time
0
0
DD
T
IOW# Strobe Width
50
50
15
3
30
30
12
5
WR
T
T
T
Write Cycle Delay
DY
DS
DH
Data Setup Time
Data Hold Time
T
Delay From IOW# To Output
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Stop To Interrupt
Delay From Initial INT Reset To Transmit Start
Delay From IOW# To Reset Interrupt
Reset Pulse Width
75
75
75
1
50
50
50
1
WDO
T
MOD
T
RSI
SSI
RRI
T
T
75
75
24
75
50
50
24
50
T
SI
T
8
8
INT
WRI
T
T
40
1
40
1
RST
16
16
N
Baud Rate Divisor
2
-1
2
-1
Bclk
Baud Clock
16X of data rate
Hz
NOTE: * For faster data rates, see the data rate characterization data on page 37.
35
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= -40O TO +85OC, VCC=1.62 - 2.75V, 70 PF LOAD WHERE APPLICABLE
LIMITS
1.8
LIMITS
2.5
SYMBOL
PARAMETER
UNIT
MIN
MAX MIN
MAX
18
-
Crystal Oscillator Frequency
12
12
MHz
MHz
ns
OSC
CLK
External Clock Frequency*
External Clock Low/High Time*
Address Setup Time
24
40
5
20
T
5
0
ns
AS
T
Address Hold Time
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bclk
ns
ns
Bclk
ns
ns
-
AH
T
T
T
Chip Select Width
250
250
250
100
100
100
CS
RD
DY
IOR# Strobe Width
Read Cycle Delay
T
Data Access Time
175
30
75
30
RDV
T
Data Disable Time
0
0
DD
T
IOW# Strobe Width
250
250
75
100
100
25
WR
T
T
T
Write Cycle Delay
DY
DS
DH
Data Setup Time
Data Hold Time
3
3
T
Delay From IOW# To Output
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Stop To Interrupt
Delay From Initial INT Reset To Transmit Start
Delay From IOW# To Reset Interrupt
Reset Pulse Width
200
200
200
1
150
150
150
1
WDO
T
MOD
T
RSI
SSI
RRI
T
T
200
200
24
150
150
24
T
SI
T
8
8
INT
WRI
T
T
200
150
40
1
40
1
RST
16
16
N
Baud Rate Divisor
2
-1
2 -1
Bclk
Baud Clock
16X of data rate
Hz
NOTE: * For faster data rates, see the data rate characterization data on page 37.
36
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
DATA RATE CHARACTERIZATION AT 5V
OPERATING TEMPERATURE RANGE = -40O TO +85OC
PARAMETER
MIN
4.5
TYP
MAX
UNIT
V
Supply Voltage, VCC
5
5.5
Input High Voltage, V
0.6*VCC
V
IH
Input Low Voltage, V
0.6
64
V
IL
External Clock/Oscillator Frequency
External Clock Low/High Time
Serial Data Rate
MHz
ns
8
4
Mbps
DATA RATE CHARACTERIZATION AT 3.3V
OPERATING TEMPERATURE RANGE = -40O TO +85OC
PARAMETER
MIN
2.97
2.4
TYP
MAX
UNIT
V
Supply Voltage
3.3
3.63
Input High Voltage, V
V
IH
Input Low Voltage, V
0.6
48
V
IL
External Clock/Oscillator Frequency
External Clock Low/High Time
Serial Data Rate
MHz
ns
10
3
Mbps
DATA RATE CHARACTERIZATION AT 2.5V
OPERATING TEMPERATURE RANGE = -40O TO +85OC
PARAMETER
MIN
2.25
2.0
TYP
MAX
UNIT
V
Supply Voltage
2.5
2.75
Input High Voltage, V
V
IH
Input Low Voltage, V
0.6
16
V
IL
External Clock/Oscillator Frequency
External Clock Low/High Time
Serial Data Rate
MHz
ns
30
1
Mbps
DATA RATE CHARACTERIZATION AT 1.8V
OPERATING TEMPERATURE RANGE = -40O TO +85OC
PARAMETER
MIN
1.62
1.4
TYP
MAX
UNIT
V
Supply Voltage
1.8
1.98
Input High Voltage, V
V
IH
Input Low Voltage, V
0.4
12
V
IL
External Clock/Oscillator Frequency
External Clock Low/High Time
Serial Data Rate
MHz
ns
40
750
Kbps
37
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
FIGURE 14. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 15. MODEM INPUT/OUTPUT TIMING
IOW#
TWDO
Change of state
RTS#
Change of state
Change of state
Change of state
CTS#
TMOD
TMOD
Active
Active
Active
Active
INT
TRSI
Active
Active
IOR#
38
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FIGURE 16. DATA BUS READ TIMING
A0-
Valid
Valid
A2
Address
Address
TAS
TAS
TAH
TAH
TCS
TCS
CS#
TDY
TRD
TRD
IOR#
TDD
TDD
TRDV
TRDV
Valid
Data
Valid
Data
D0-D7
RDTm
FIGURE 17. DATA BUS WRITE TIMING
A0-
A2
Valid
Address
Valid
Address
TAS
TAS
TAH
TAH
TCS
TWR
TDS
TCS
CS#
IOW#
D0-D7
TDY
TWR
TDH
TDH
TDS
Valid
Valid
Data
Data
16Write
39
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
FIGURE 18. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE]
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 19. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE]
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
IOW#
(Loading data
into THR)
TXNonFIFO
*INT is cleared when the ISR is read or when data is loaded into the THR.
40
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FIGURE 20. RECEIVE READY INTERRUPT TIMING [FIFO MODE]
Start
Bit
RX
S
S
S
S
S
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
T
D0:D7 T
D0:D7 T
S
D0:D7
T
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TRRI
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 21. TRANSMIT READY INTERRUPT TIMING [FIFO MODE]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
T
S
S
D0:D7
S
S
T
S
D0:D7
D0:D7
T
S D0:D7
T
T
D0:D7
T
D0:D7
T
ISR is read
TSI
IER[1]
enabled
ISR is read
INT*
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
IOW#
(Loading data
into FIFO)
TX INT
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
41
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
D2
D
D
D2
L
b
e
Note: The actual center pad is
metallic and the size (D2) is
device-dependent with a typical
tolerance of 0.3mm
A1
A
Seating Plane
A3
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.039
0.002
0.010
0.201
0.150
0.012
MIN
0.80
0.00
0.15
4.90
3.50
0.18
MAX
1.00
0.05
0.25
5.10
3.80
0.30
A
A1
A3
D
0.031
0.000
0.006
0.193
0.138
0.007
D2
b
e
0.0197 BSC
0.012 0.020
0.50 BSC
L
0.30
0.50
42
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm)
Top
Bottom
Note: the actual center pad
is metallic and the size (D2 )
is devic-e dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
0.80
0.00
0.15
3.90
2.50
0.18
MAX
1.00
0.05
0.25
4.10
2.80
0.30
A
A1
A3
D
0.031
0.000
0.006
0.154
0.098
0.007
0.039
0.002
0.010
0.161
0.110
0.012
D2
b
e
0.0197 BSC
0.014 0.018
0.50 BSC
L
0.35
0.45
43
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
REVISION HISTORY
DATE
REVISION
P1.0.0
1.0.0
DESCRIPTION
December 2005
December 2005
Preliminary Datasheet.
Initial Datasheet Release. Updated 1.8V Electrical Characteristics.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet December 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
44
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XR16L570
REV. 1.0.0
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES..................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PACKAGE AND PIN OUT (24-PIN QFN PACKAGE).............................................................................................................. 2
ORDERING INFORMATION ................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 5
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 6
2.1 CPU INTERFACE ............................................................................................................................................. 6
FIGURE 3. XR16L570 TYPICAL DATA BUS INTERCONNECTIONS ........................................................................................................ 6
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7
2.3 DEVICE HARDWARE RESET .......................................................................................................................... 7
2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................... 7
2.5 INTERNAL REGISTERS ................................................................................................................................... 7
2.6 DMA MODE ...................................................................................................................................................... 7
2.7 INT OUTPUT ..................................................................................................................................................... 7
TABLE 1: INT PIN OPERATION FOR TRANSMITTER............................................................................................................................. 7
TABLE 2: INT PIN OPERATION FOR RECEIVER.................................................................................................................................. 7
2.8 CRYSTAL OR EXTERNAL CLOCK INPUT ..................................................................................................... 8
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS..................................................................................................................................... 8
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE............................................................................................ 8
2.9 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................ 9
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ....................................................................................................................... 9
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ EXTERNAL CLOCK.......................................................................................... 10
2.10 TRANSMITTER ............................................................................................................................................. 10
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 10
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 10
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 11
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 11
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 11
2.11 RECEIVER .................................................................................................................................................... 11
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 12
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 12
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 12
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................ 13
2.13 AUTO RTS HYSTERESIS ........................................................................................................................... 13
2.14 AUTO CTS FLOW CONTROL ..................................................................................................................... 13
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 14
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL .................................................................................. 15
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 15
2.16 SPECIAL CHARACTER DETECT ............................................................................................................... 15
2.17 INFRARED MODE ........................................................................................................................................ 16
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 16
2.18 SLEEP MODE WITH WAKE-UP INTERRUPT AND POWER-SAVE FEATURE ........................................ 17
2.18.1 SLEEP MODE ........................................................................................................................................................... 17
2.18.2 POWER-SAVE FEATURE ........................................................................................................................................ 17
2.19 INTERNAL LOOPBACK .............................................................................................................................. 18
FIGURE 13. INTERNAL LOOP BACK ................................................................................................................................................. 18
3.0 UART INTERNAL REGISTERS ........................................................................................................... 19
TABLE 5: UART INTERNAL REGISTERS.................................................................................................................................... 19
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1.......................................... 20
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 21
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 21
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 21
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................... 21
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 21
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 21
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 22
I
XR16L570
xr
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.0
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 23
4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 23
4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 23
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 24
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 24
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION .............................................................................................. 25
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 25
TABLE 9: PARITY SELECTION .......................................................................................................................................................... 26
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 27
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 28
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 29
4.11 SCRATCHPAD REGISTER (SPR) - READ/WRITE ..................................................................................... 30
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 30
4.13 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 30
4.14 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 30
4.15 ENHANCED FEATURE REGISTER (EFR) ................................................................................................. 30
TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS........................................................................................................................ 31
4.16 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - WRITE ONLY ................ 32
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 33
ABSOLUTE MAXIMUM RATINGS...................................................................................33
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)33
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................34
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................34
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................35
Unless otherwise noted: TA= -40o to +85oC, Vcc=2.97 - 5.5V, 70 pF load where applicable..................................35
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................36
Unless otherwise noted: TA= -40o to +85oC, Vcc=1.62 - 2.75V, 70 pF load where applicable................................36
DATA RATE CHARACTERIZATION AT 5V..........................................................................................................37
Operating Temperature Range = -40o to +85oC.......................................................................................................37
DATA RATE CHARACTERIZATION AT 3.3V.......................................................................................................37
Operating Temperature Range = -40o to +85oC.......................................................................................................37
DATA RATE CHARACTERIZATION AT 2.5V.......................................................................................................37
Operating Temperature Range = -40o to +85oC.......................................................................................................37
DATA RATE CHARACTERIZATION AT 1.8V.......................................................................................................37
Operating Temperature Range = -40o to +85oC.......................................................................................................37
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 38
FIGURE 15. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 38
FIGURE 16. DATA BUS READ TIMING.............................................................................................................................................. 39
FIGURE 17. DATA BUS WRITE TIMING............................................................................................................................................. 39
FIGURE 18. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................... 40
FIGURE 19. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................. 40
FIGURE 20. RECEIVE READY INTERRUPT TIMING [FIFO MODE] ....................................................................................................... 41
FIGURE 21. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] ..................................................................................................... 41
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 MM)..............................................42
PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 MM)..............................................43
REVISION HISTORY.......................................................................................................................................44
TABLE OF CONTENTS ............................................................................................................I
II
相关型号:
XR16L570IL32-F
Serial I/O Controller, 1 Channel(s), 0.5MBps, CMOS, 5 X 5 MM, 0.90 MM HEIGHT, GREEN, QFN-32
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Serial I/O Controller, 1 Channel(s), 0.390625MBps, CMOS, 5 X 5 MM, 0.90 MM HEIGHT, GREEN, QFN-32
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