XR16M564IJ-0A-EVB_技术文档

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

MAY 2008

REV. 1.0.0

FEATURES

GENERAL DESCRIPTION

•

Pin-to-pin compatible with ST16C454, ST16C554,

TI’s TL16C754B and NXP’s SC16C754B

1

The XR16M564 (M564) is an enhanced quad

Universal Asynchronous Receiver and Transmitter

(UART) with 32 bytes of transmit and receive FIFOs,

programmable transmit and receive FIFO trigger

levels, automatic hardware and software flow control,

and data rates of up to 16 Mbps at 4X sampling rate.

Each UART has a set of registers that provide the

user with operating status and control, receiver error

indications, and modem serial interface controls. An

internal loopback capability allows onboard

diagnostics. The M564 is available in a 48-pin QFN,

64-pin LQFP, 68-pin PLCC and 80-pin LQFP

packages. The 64-pin and 80-pin packages only offer

the 16 mode interface, but the 48 and 68 pin

packages offer an additional 68 mode interface which

allows easy integration with Motorola processors.

The XR16M564IV (64-pin) offers three state interrupt

output while the XR16M564DIV provides continuous

interrupt output. The XR16M564 is compatible with

the industry standard ST16C554 and ST16C654/

654D.

•

Intel or Motorola Data Bus Interface select

Four independent UART channels

■

Register Set Compatible to 16C550

Data rates of up to 16 Mbps

32 byte Transmit FIFO

32 byte Receive FIFO with error tags

4 Selectable TX and RX FIFO Trigger Levels

Automatic Hardware (RTS/CTS) Flow Control

Automatic Software (Xon/Xoff) Flow Control

Programmable Xon/Xoff characters

Wireless Infrared (IrDA 1.0) Encoder/Decoder

Full modem interface

•

1.62V to 3.63V supply operation

Sleep Mode with automatic wake-up

Crystal oscillator or external clock input

NOTE: 1 Covered by U.S. Patent #5,649,122.

APPLICATIONS

•

Portable Appliances

Telecommunication Network Routers

Ethernet Network Routers

Cellular Data Devices

Factory Automation and Process Controls

F

IGURE 1. XR16M564 BLOCK DIAGRAM

1.62V to 3.6V VCC

GND

A2:A0

D7:D0

UART Channel A

32 Byte TX FIFO

IOR#

IOW#

CSA#

CSB#

UART

Regs

TXA, RXA, DTRA#,

DSRA#, RTSA#, CTSA#,

CDA#, RIA#

IR

TX & RX

ENDEC

BRG

32 Byte RX FIFO

CSC#

CSD#

TXB, RXB, DTRB#,

DSRB#, RTSB#, CTSB#,

CDB#, RIB#

UART Channel B

(same as Channel A)

INTA

INTB

INTC

Data Bus

Interface

TXC, RXC, DTRC#,

DSRC#, RTSC#, CTSC#,

CDC#, RIC#

UART Channel C

(same as Channel A)

INTD

TXRDY# A-D

RXRDY# A-D

Reset

TXD, RXD, DTRD#,

DSRD#, RTSD#, CTSD#,

CDD#, RID#

UART Channel D

(same as Channel A)

16/68#

INTSEL

CLKSEL

XTAL1

XTAL2

Crystal Osc/Buffer

564 BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

F

IGURE 2. PIN

O

UT

A

SSIGNMENT

F

OR 68-PIN PLCC PACKAGES

IN

16 AND 68 MODE AND 64-PIN LQFP PACKAGES

DSRA# 10

60 DSRD#

60

59

58

DSRD#

CTSD#

DTRD#

DSRA# 10

CTSA# 11

DTRA# 12

VCC 13

CTSA# 11

59 CTSD#

DTRA# 12

58 DTRD#

VCC 13

57 GND

RTSA# 14

56 RTSD#

56

RTSD#

RTSA# 14

INTA 15

CSA# 16

TXA 17

IRQ# 15

55 INTD

55 N.C.

54 N.C.

53 TXD

52 N.C.

51 TXC

50 A4

49 N.C.

CS# 16

54 CSD#

XR16M564

68-pin PLCC

Motorola Mode

XR16M564

68-pin PLCC

Intel Mode

TXA 17

53 TXD

R/W# 18

52 IOR#

IOW# 18

TXB 19

51 TXC

(16/68# pin connected to GND)

(16/68# pin connected to VCC)

A3 20

N.C. 21

CSB# 20

INTB 21

RTSB# 22

GND 23

50 CSC#

49 INTC

RTSB# 22

GND 23

48

RTSC#

48 RTSC#

47 VCC

DTRB# 24

CTSB# 25

DSRB# 26

46

45

44

DTRC#

DTRB# 24

CTSB# 25

DSRB# 26

46 DTRC#

45 CTSC#

44 DSRC#

CTSC#

DSRC#

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DSRD#

CTSD#

DTRD#

GND

DSRA#

CTSA#

DTRA#

VCC

3

4

RTSA#

INTA

5

RTSD#

INTD

6

CSA#

TXA

7

CSD#

TXD

XR16M564

64-pin TQFP

Intel Mode Only

8

IOR#

IOW#

TXB

9

TXC

10

11

12

13

14

15

16

CSC#

INTC

CSB#

INTB

RTSC#

VCC

RTSB#

GND

DTRB#

CTSB#

DTRC#

CTSC#

2

XR16M564/564D

REV. 1.0.0

IGURE 3. PIN

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

F

O

UT

A

SSIGNMENT

F

OR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE

RXD

36

35

34

33

CTSA#

VCC

1

2

CTSD#

GND

RTSA#

INTA

CSA#

TXA

3

4

5

6

7

8

9

RTSD#

32 INTD

CSD#

XR16M564

48-pin QFN

31

IOW#

TXB

30 TXD

29 IOR#

CSB#

28

27

26

25

TXC

INTB

RTSB#

CTSB#

CSC#

INTC

10

11

12

RTSC#

NC

1

2

3

60

59

58

57

56

NC

CDD#

CDC#

RIC#

RID#

RXD

RXC

GND

4

5

6

7

8

VCC

INTSEL

55 TXRDY#

RXRDY#

D0

D1

54

53

52

51

RESET

NC

XR16M 564

D2

9

-

80 pin LQFP

XTAL2

NC

10

Intel Mode Only

50 XTAL1

D3

11

12

49

NC

A0

D4

D5

13

48

47

46

A1

A2

14

15

D6

D7

16

17

18

19

20

GND

RXA

45

44

43

42

41

VCC

RXB

RIA#

CDA#

NC

RIB#

CDB#

NC

3

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

ORDERING INFORMATION

REV. 1.0.0

O

PERATING

T

EMPERATURE

PART

N

UMBER

P

ACKAGE

DEVICE STATUS

RANGE

XR16M564IJ68

XR16M564IV64

68-Lead PLCC

64-Lead LQFP

-40°C to +85°C

Active

XR16M564DIV64

XR16M564IL48

XR16M564IV80

64-Lead LQFP

48-pin QFN

-40°C to +85°C

Active

80-Lead LQFP

PIN DESCRIPTIONS

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

P

IN

#

P

IN

#

P

IN

#

PIN #

DATA BUS INTERFACE

A2

A1

A0

15

16

17

22

23

24

32

33

34

46

47

48

I

Address data lines [2:0]. These 3 address lines select

one of the internal registers in UART channel A-D dur-

ing a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

46

45

44

43

42

41

40

39

60

59

58

57

56

55

54

53

5

4

15

14

13

12

11

9

I/O Data bus lines [7:0] (bidirectional).

3

2

1

68

67

66

8

7

IOR#

29

40

52

70

I

When 16/68# pin is HIGH, the Intel bus interface is

selected and this input becomes read strobe (active

low). The falling edge instigates an internal read cycle

and retrieves the data byte from an internal register

pointed by the address lines [A2:A0], puts the data

byte on the data bus to allow the host processor to

read it on the rising edge.

(VCC)

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input is not used and should be con-

nected to VCC.

IOW#

7

9

18

31

I

When 16/68# pin is HIGH, it selects Intel bus interface

and this input becomes write strobe (active low). The

falling edge instigates the internal write cycle and the

rising edge transfers the data byte on the data bus to

an internal register pointed by the address lines.

(R/W#)

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input becomes read (logic 1) and

write (LOW) signal.

CSA#

(CS#)

5

7

16

28

I

When 16/68# pin is HIGH, this input is chip select A

(active low) to enable channel A in the device.

When 16/68# pin is LOW, this input becomes the chip

select (active low) for the Motorola bus interface.

4

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

P

IN

#

P

IN

#

P

IN

#

PIN #

CSB#

(A3)

9

11

20

33

I

When 16/68# pin is HIGH, this input is chip select B

(active low) to enable channel B in the device.

When 16/68# pin is LOW, this input becomes address

line A3 which is used for channel selection in the

Motorola bus interface.

CSC#

(A4)

27

38

50

68

When 16/68# pin is HIGH, this input is chip select C

(active low) to enable channel C in the device.

When 16/68# pin is LOW, this input becomes address

line A4 which is used for channel selection in the

Motorola bus interface.

CSD#

(VCC)

31

4

42

6

54

15

73

27

When 16/68# pin is HIGH, this input is chip select D

(active low) to enable channel D in the device.

When 16/68# pin is LOW, this input is not used and

should be connected VCC.

INTA

O

When 16/68# pin is HIGH for Intel bus interface, this

ouput becomes channel A interrupt output. The output

state is defined by the user and through the software

setting of MCR[3]. INTA is set to the active mode when

MCR[3] is set to a logic 1. INTA is set to the three state

mode when MCR[3] is set to a logic 0 (default). See

MCR[3].

(IRQ#)

(OD)

When 16/68# pin is LOW for Motorola bus interface,

this output becomes device interrupt output (active

low, open drain). An external pull-up resistor is

required for proper operation.

INTB

INTC

INTD

(N.C.)

10

26

32

12

37

43

21

49

55

34

67

74

O

When 16/68# pin is HIGH for Intel bus interface, these

ouputs become the interrupt outputs for channels B, C,

and D. The output state is defined by the user through

the software setting of MCR[3]. The interrupt outputs

are set to the active mode when MCR[3] is set to a

logic 1 and are set to the three state mode when

MCR[3] is set to a logic 0 (default). See MCR[3].

When 16/68# pin is LOW for Motorola bus interface,

these outputs are unused and will stay at logic zero

level. Leave these outputs unconnected.

TXRDY#

RXRDY#

-

39

38

55

54

O

Transmitter Ready (active low). This output is a logi-

cally ANDed status of TXRDY# A-D. See Table 5. If

this output is unused, leave it unconnected.

Receiver Ready (active low). This output is a logically

ANDed status of RXRDY# A-D. See Table 5. If this

output is unused, leave it unconnected.

5

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

Pin Description

REV. 1.0.0

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

P

IN

#

P

IN

#

P

IN

#

P

IN

#

INTSEL

38

-

65

6

I

Interrupt Select (active high, input with internal pull-

down).

When 16/68# pin is HIGH for Intel bus interface, this

pin can be used in conjunction with MCR bit-3 to

enable or disable the INT A-D pins or override MCR

bit-3 and enable the interrupt outputs. Interrupt out-

puts are enabled continuously when this pin is HIGH.

MCR bit-3 enables and disables the interrupt output

pins. In this mode, MCR bit-3 is set to a logic 1 to

enable the continuous output. See MCR bit-3 descrip-

tion for full detail. This pin must be LOW in the Motor-

ola bus interface mode. For the 64 pin packages, this

pin is bonded to VCC internally in the XR16M564D so

the INT outputs operate in the continuous interrupt

mode. This pin is bonded to GND internally in the

XR16M564 and therefore requires setting MCR bit-3

for enabling the interrupt output pins.

MODEM OR SERIAL I/O INTERFACE

TXA

TXB

TXC

TXD

6

8

17

19

51

53

29

32

69

72

O

UART channels A-D Transmit Data and infrared trans-

mit data. Standard transmit and receive interface is

enabled when MCR[6] = 0. In this mode, the TX signal

will be a HIGH during reset, or idle (no data). Infrared

IrDA transmit and receive interface is enabled when

MCR[6] = 1. In the Infrared mode, the inactive state

(no data) for the Infrared encoder/decoder interface is

a logic 0.

10

39

41

28

30

RXA

RXB

RXC

RXD

48

13

22

36

62

20

29

51

7

17

44

57

4

I

UART channel A-D Receive Data or infrared receive

data. Normal receive data input must idle HIGH.

29

41

63

RTSA#

RTSB#

RTSC#

RTSD#

3

5

14

22

48

56

26

35

66

75

O

UART channels A-D Request-to-Send (active low) or

general purpose output. This output must be asserted

prior to using auto RTS flow control, see EFR[6],

MCR[1], and IER[6]. Also see Figure 11. If these

outputs are not used, leave them unconnected.

11

25

33

13

36

44

CTSA#

CTSB#

CTSC#

CTSD#

1

2

11

25

45

59

23

38

63

78

I

UART channels A-D Clear-to-Send (active low) or gen-

eral purpose input. It can be used for auto CTS flow

12

23

35

16

33

47

control, see EFR[7], and IER[7]. Also see Figure 11

These inputs should be connected to VCC when not

used.

.

DTRA#

DTRB#

DTRC#

DTRD#

-

3

12

24

46

58

24

37

64

77

O

I

UART channels A-D Data-Terminal-Ready (active low)

or general purpose output. If these outputs are not

used, leave them unconnected.

15

34

46

DSRA#

DSRB#

DSRC#

DSRD#

-

1

10

26

44

60

22

39

62

79

UART channels A-D Data-Set-Ready (active low) or

general purpose input. This input should be connected

to VCC when not used. This input has no effect on the

UART.

17

32

48

6

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

P

IN

#

P

IN

#

P

IN

#

PIN #

CDA#

CDB#

CDC#

CDD#

-

64

18

31

49

9

19

42

59

2

I

UART channels A-D Carrier-Detect (active low) or

general purpose input. This input should be connected

to VCC when not used. This input has no effect on the

UART.

27

43

61

RIA#

RIB#

RIC#

RID#

-

63

19

30

50

8

18

43

58

3

I

UART channels A-D Ring-Indicator (active low) or gen-

eral purpose input. This input should be connected to

VCC when not used. This input has no effect on the

UART.

28

42

62

ANCILLARY SIGNALS

XTAL1

XTAL2

16/68#

18

19

14

25

26

-

35

36

31

50

51

-

I

O

I

Crystal or external clock input.

Crystal or buffered clock output.

Intel or Motorola Bus Select (input with internal pull-

up).

When 16/68# pin is HIGH, 16 or Intel Mode, the device

will operate in the Intel bus type of interface.

When 16/68# pin is LOW, 68 or Motorola mode, the

device will operate in the Motorola bus type of inter-

face.

Motorola bus interface is not available on the 64 pin

package.

CLKSEL

-

21

27

30

37

-

I

Baud-Rate-Generator Input Clock Prescaler Select for

channels A-D. This input is only sampled during power

up or a reset. Connect to VCC for divide by 1 (default)

and GND for divide by 4. MCR[7] can override the

state of this pin following a reset or initialization. See

MCR bit-7 and Figure 6 in the Baud Rate Generator

section.

RESET

20

53

When 16/68# pin is HIGH for Intel bus interface, this

input becomes the Reset pin (active high). In this

case, a 40 ns minimum HIGH pulse on this pin will

reset the internal registers and all outputs. The UART

transmitter output will be held HIGH, the receiver input

will be ignored and outputs are reset during reset

period (Table 17). When 16/68# pin is at LOW for

Motorola bus interface, this input becomes Reset# pin

(active low). This pin functions similarly, but instead of

a HIGH pulse, a 40 ns minimum LOW pulse will reset

the internal registers and outputs.

(RESET#)

Motorola bus interface is not available on the 64 pin

package.

VCC

GND

2, 24, 37 4, 35, 52

13, 47, 5, 25, 45, Pwr 1.62V to 3.63V power supply.

64

65

21, 47

14, 28, 6, 23, 40,

16, 36,

56, 76

Pwr Power supply common, ground.

45, 61 57

7

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

Pin Description

REV. 1.0.0

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

P

IN

#

P

IN

#

P

IN

#

PIN #

GND

Center

Pad

N/A

Pwr

The center pad on the backside of the QFN package is

metallic and should be connected to GND on the PCB.

The thermal pad size on the PCB should be the

approximate size of this center pad and should be sol-

der mask defined. The solder mask opening should be

at least 0.0025" inwards from the edge of the PCB

thermal pad.

N.C.

-

1, 10, 20,

21, 30,

40, 41,

49, 52,

60, 61,

71, 80

No Connection. These pins are not used in either the

Intel or Motorola bus modes.

Pin type: I=Input, O=Output, I/O= Input/Output, OD=Output Open Drain.

8

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

1.0 PRODUCT DESCRIPTION

The XR16M564 (M564) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver

and Transmitter (UART). Each UART is independently controlled and has its own set of device configuration

registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.

Additionally, each UART channel has 32 bytes of transmit and receive FIFOs, automatic RTS/CTS hardware

flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder

(IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of dividing by 1 or 4, and data rate

up to 16 Mbps. The XR16M564 can operate from 1.62 to 3.63 volts. The M564 is fabricated with an advanced

CMOS process.

Enhanced FIFO

The M564 QUART provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of

16 bytes in the ST16C554, or one byte in the ST16C454. The M564 is designed to work with high performance

data communication systems, that require fast data processing time. Increased performance is realized in the

M564 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control

mechanism. This allows the external processor to handle more networking tasks within a given time. For

example, the ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses

a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to

service the receive FIFO at 1.53 ms intervals. However with the 32 byte FIFO in the M564, the data buffer will

not require unloading/loading for 3.1 ms. This increases the service interval giving the external CPU additional

time for other applications and reducing the overall UART interrupt servicing time. In addition, the

programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided

for maximum data throughput performance especially when operating in a multi-channel system. The

combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and

reduces power consumption.

Data Rate

The M564 is capable of operation up to 16 Mbps at 3.3V with 4Xinternal sampling clock rate. The device can

operate at 3.3V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock

source of 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user

can set the prescaler bit and sampling rate for data rates of up to 3.68 Mbps.

Enhanced Features

The rich feature set of the M564 is available through the internal registers. Automatic hardware/software flow

control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder

interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility

for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR

bit-3 can be configured to provide a software controlled or continuous interrupt capability. For backward

compatibility to the ST16C654, the 64-pin LQFP does not have the INTSEL pin. Instead, two different LQFP

packages are offered. The XR16M564DIV operates in the continuous interrupt enable mode by internally

bonding INTSEL to VCC. The XR16M564IV operates in conjunction with MCR bit-3 by internally bonding

INTSEL to GND.

The XR16M564 offers a clock prescaler select pin to allow system/board designers to preset the default baud

rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.

It can then be overridden following initialization by MCR bit-7.

9

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

REV. 1.0.0

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The M564 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required for a data bus

transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.

All four UART channels share the same data bus for host operations. A typical data bus interconnection for

Intel and Motorola mode is shown in Figure 4.

F

IGURE 4. XR16M564 TYPICAL

INTEL/MOTOROLA

DATA

B

US

I

NTERCONNECTIONS

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

VCC

TXA

RXA

DTRA#

RTSA#

UART

Serial Interface of

CTSA#

DSRA#

CDA#

RIA#

Channel A

RS-232

A0

A1

A2

A0

A1

A2

IOR#

IOW#

UART

IOW#

Channel B

Similar

CSA#

CSB#

CSC#

CSD#

UART_CSA#

UART_CSB#

UART_CSC#

UART_CSD#

to Ch A

UART

Channel C

Serial Interface of

RS-232

Similar

to Ch A

UART_INTA

UART_INTB

UART_INTC

UART_INTD

INTA

INTB

INTC

INTD

UART

Channel D

Similar

to Ch A

UART_RESET

VCC

RESET

16/68#

GND

Intel Data Bus (16 Mode) Interconnections

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

D6

UART

Channel A

Serial Interface of

RS-232

D7

A0

A1

A0

A1

A2

A3

A4

CSB#

CSC#

CSD#

UART

Channel B

VCC

Similar

to Ch A

IOR#

IOW#

R/W#

UART

Channel C

CSA#

UART_CS#

Similar

to Ch A

Serial Interface of

RS-232

VCC

UART_IRQ#

INTA

UART

Channel D

INTB

INTC

INTD

(no connect)

Similar

to Ch A

UART_RESET#

RESET#

16/68#

GND

Motorola Data Bus (68 Mode) Interconnections

10

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.2

Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 17). An active high pulse of longer than 40 ns duration will be required to activate the reset

function in the device. Following a power-on reset or an external reset, the M564 is software compatible with

previous generation of UARTs, 16C454 and 16C554.

2.3

Channel Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a

LOW on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D to

configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be

useful during power up initialization to write to the same internal registers, but do not attempt to read from all

four uarts simultaneously. Individual channel select functions are shown in Table 1.

TABLE 1: CHANNEL A-D SELECT IN 16 MODE

CSA# CSB# CSC# CSD#

FUNCTION

1

0

1

0

1

0

1

0

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

Channels A-D selected

During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for

connection with Motorola, and other popular microprocessor bus types. In this mode the M564 decodes two

additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode

function is used only when in the Motorola Bus Mode. See Table 2.

TABLE 2: CHANNEL A-D SELECT IN 68 MODE

CS#

A4

A3

X

0

FUNCTION

1

0

X

0

1

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

1

0

1

11

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

2.4

Channels A-D Internal Registers

Each UART channel in the M564 has a set of enhanced registers for controlling, monitoring and data loading

and unloading. The configuration register set is compatible to those already available in the standard single

16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers

(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status

and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a

user accessible scratchpad register (SPR).

Beyond the general 16C550 features and capabilities, the M564 offers enhanced feature registers (EFR, Xon/

Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff

software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART

INTERNAL REGISTERS” on page 24.

2.5

INT Ouputs for Channels A-D

The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4

summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through 25.

TABLE 3: INT PIN

O

PERATION FOR

TRANSMITTER FOR

CHANNELS A-D

FCR BIT-0 = 1 (FIFO ENABLED

)

FCR BIT-0 = 0

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(FIFO DISABLED

)

(DMA Mode Enabled)

INT Pin

LOW = a byte in THR

HIGH = THR empty

LOW = FIFO above trigger level

HIGH = FIFO below trigger level or

FIFO empty

HIGH = FIFO below trigger level or

FIFO empty

TABLE 4: INT PIN

O

PERATION FOR

R

ECEIVER FOR

C

HANNELS A-D

FCR BIT-0 = 0

FCR BIT-0 = 1 (FIFO ENABLED

)

(FIFO DISABLED

)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

INT Pin

LOW = no data

HIGH = 1 byte

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

2.6

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide

additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the

transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit

and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the

DMA mode is disabled (FCR bit-3 = 0), the M564 is placed in single-character mode for data transmit or

receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode

12

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level.

The following table show their behavior. Also see Figure 20 through 25.

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D

FCR BIT-0=0

P

INS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED

)

FCR BIT-3 = 0

(DMA MODE

FCR BIT-3 = 1

(DMA MODE ENABLED)

D

ISABLED

)

RXRDY#

TXRDY#

LOW = 1 byte

LOW = at least 1 byte in FIFO

HIGH = FIFO empty

HIGH to LOW transition when FIFO reaches the

trigger level, or timeout occurs

HIGH = no data

LOW to HIGH transition when FIFO empties

LOW = THR empty

LOW = FIFO empty

LOW = FIFO has at least 1 empty location

HIGH = FIFO is full

HIGH = byte in THR HIGH = at least 1 byte in FIFO

2.7

Crystal Oscillator or External Clock Input

The M564 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see

“Section 2.8, Programmable Baud Rate Generator with Fractional Divisor” on page 13.

F

IGURE 5. TYPICAL CRYSTAL CONNECTIONS

R=300K to 400K

14.7456

MHz

XTAL2

XTAL1

C1

C2

22-47pF

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown

in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate

generator for standard or custom rates. For further reading on oscillator circuit please see application note

DAN108 on EXAR’s web site.

2.8

Programmable Baud Rate Generator with Fractional Divisor

Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The

prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide

the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further

16

divides this clock by a programmable divisor between 1 and (2 - 0.0625) in increments of 0.0625 (1/16) to

obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter

for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to

the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be

13

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part

of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD

are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting

1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for

selecting the operating data rate. Table 6 shows the standard data rates available with a 24MHz crystal or

external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times

less than that shown in Table 6. At 8X sampling rate, these data rates would double. And at 4X sampling rate,

they would quadruple. Also, when using 8X sampling mode, please note that the bit-time will have a jitter (+/- 1/

16) whenever the DLD is non-zero and is an odd number. When using a non-standard data rate crystal or

external clock, the divisor value can be calculated with the following equation(s):

Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’

The closest divisor that is obtainable in the M564 can be calculated using the following formula:

ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where

DLM = TRUNC(Required Divisor) >> 8

DLL = TRUNC(Required Divisor) & 0xFF

DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)

In the formulas above, please note that:

TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.

ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.

A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.

FIGURE 6. BAUD

R

ATE

G

ENERATOR

To Other

Channels

DLL, DLM and DLD

Registers

MCR Bit-7=0

(default)

Prescaler

Divide by 1

16X or 8X or 4X

Sampling

Rate Clock

to Transmitter

and Receiver

Crystal

Osc/

Buffer

XTAL1

XTAL2

Fractional Baud

Rate Generator

Logic

Prescaler

Divide by 4

MCR Bit-7=1

14

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING

Required

Output Data

Rate

D

IVISOR FOR 16x

Clock

(Decimal)

DIVISOR

BTAINABLE IN

DLM PROGRAM DLL PROGRAM DLD PROGRAM

ALUE (HEX) ALUE (HEX) ALUE (HEX)

DATA ERROR

O

V

RATE (%)

V2550

400

2400

3750

625

3750

625

E

2

1

0

A6

71

38

9C

96

4E

3C

34

27

1E

1A

14

F

0

8

4

0

2

0

1

0

1

0

C

8

B

8

0

C

4

0

A

8

0

4800

312.5

156.25

150

312 8/16

156 4/16

150

0

9600

0

10000

19200

25000

28800

38400

50000

57600

75000

100000

115200

153600

200000

225000

230400

250000

300000

400000

460800

500000

750000

921600

1000000

0

78.125

60

78 2/16

60

0

52.0833

39.0625

30

52 1/16

39 1/16

30

0.04

0

26.0417

20

26 1/16

20

0.08

0

15

0

13.0208

9.7656

7.5

13

D

0.16

0

9 12/16

7 8/16

6 11/16

6 8/16

6

9

7

6.6667

6.5104

6

0.31

0.16

0

6

5

0

3.75

3 12/16

3 4/16

3

0

3.2552

3

0.16

0

3

2

0

1.6276

1.5

1 10/16

1 8/16

1

0.16

0

1

2.9

Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X

internal clock. A bit time is 16/8/4 clock periods. The transmitter sends the start-bit followed by the number of

data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are

reported in the Line Status Register (LSR bit-5 and bit-6).

2.9.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

15

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

2.9.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

F

IGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Data

Byte

Transmit

Holding

Register

(THR)

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X or 8X or 4X

Clock

( DLD[5:4] )

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.9.3

Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set

when TSR/FIFO becomes empty.

F

IGURE 8. TRANSMITTER

O

PERATION IN FIFO AND

F

LOW

C

ONTROL

M

ODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.)

Auto Software Flow Control

16X or 8X or 4X Clock

(DLD[5:4])

Transmit Data Shift Register

(TSR)

TXFIFO1

16

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.10 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It

verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of

a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks

(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is

sampled and if it is still LOW it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same

manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon

unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are

immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data

ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data

delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4

word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR

interrupt is enabled by IER bit-0. See Figure 9 and Figure 10 below.

2.10.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

F

IGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X or 8X or 4X Clock

( DLD[5:4] )

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Error

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

Tags in

LSR bits

4:2

RHR Interrupt (ISR bit-2)

RXFIFO1

17

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

F

IGURE 10. RECEIVER

O

PERATION IN FIFO AND

A

UTO RTS FLOW CONTROL MODE

16X or 8X or 4X Clock

( DLD[5:4] )

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example

- RX FIFO trigger level selected at 16 bytes

:

(See Note Below)

32 bytes by 11-bit wide

FIFO

Data falls to

8

RTS# re-asserts when data falls below the flow

control trigger level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data FIFO

FIFO

Trigger=16

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

Data fills to

24

RTS# de-asserts when data fills above the flow

control trigger level to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

2.11 Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enabled to fit specific application requirement (see Figure 11):

•

Enable auto RTS flow control using EFR bit-6.

The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS#

pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.12 Auto RTS Hysteresis

The M564 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with

the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt

is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced

HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger

table (Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected

trigger level. Under the above described conditions, the M564 will continue to accept data until the receive

FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).

TABLE 7: AUTO RTS (HARDWARE) FLOW

CONTROL

RTS# D

E

-

ASSERTED (HIGH

)

RTS# ASSERTED (LOW)

R

X

TRIGGER

LEVEL

INT PIN ACTIVATION

(CHARACTERS IN

RX

F

IFO

)

(CHARACTERS IN RX FIFO)

8

16

24

30

0

8

16

24

30

16

24

30

16

24

18

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.13 Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 11):

•

Enable auto CTS flow control using EFR bit-7.

If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an

interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend

transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after

the CTS# input is re-asserted (LOW), indicating more data may be sent.

F

IGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

RXB

Auto RTS

Auto CTS

Monitor

Trigger Level

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

ON

RTSA#

OFF

7

2

ON

3

11

OFF

CTSB#

TXB

8

Restart

9

Data Starts

6

Suspend

4

RXA FIFO

Receive

Data

RX FIFO

12

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

19

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.14 Auto Xon/Xoff (Software) Flow Control

REV. 1.0.0

When software flow control is enabled (See Table 16), the M564 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the M564 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the M564 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the M564 will resume operation

and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to LOW. Following reset the user can

write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff

characters (See Table 16) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are

selected, the M564 compares two consecutive receive characters with two software flow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control

mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the M564 automatically

sends an Xoff message (when enabled) via the serial TX output to the remote modem. The M564 sends the

Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)

after the receive FIFO crosses the programmed trigger level. To clear this condition, the M564 will transmit the

programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed

trigger level. Table 8 below explains this.

TABLE 8: AUTO

X

ON/XOFF (SOFTWARE) FLOW

C

ONTROL

X

(

OFF

C

HARACTER

(

S

) SENT

X

ON CHARACTER(S) SENT

RX TRIGGER

L

EVEL

INT PIN

ACTIVATION

CHARACTERS IN RX FIFO

)

(

CHARACTERS IN RX FIFO)

8

8*

0

8

16

24

30

16

24

30

16*

24*

30*

16

24

* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);

for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

2.15

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal

incoming RX data.

The M564 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the

Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of

bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff

Registers corresponds with the LSB bit for the receive character.

20

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.16 Infrared Mode

The M564 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)

version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-

pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,

hence reduces the power consumption. See Figure 12 below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature

is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level

of logic zero from a reset and power up, see Figure 12.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.

Each time it senses a light pulse, it returns HIGH to the data bit stream.

F

IGURE 12. INFRARED

TRANSMIT

D

ATA

E

NCODING AND

R

ECEIVE

D

ATA

D

ECODING

Character

Data Bits

1

0

TX Data

Transmit

IR Pulse

(TX Pin)

1/2 Bit Time

Bit Time

3/16 Bit Time

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

0

RX Data

Data Bits

Character

IRdecoder-1

21

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

2.17 Sleep Mode with Auto Wake-Up

REV. 1.0.0

The M564 supports low voltage system designs, hence, a sleep mode is included to reduce its power

consumption when the chip is not actively used.

All of these conditions must be satisfied for the M564 to enter sleep mode:

■

no interrupts pending for all four channels of the M564 (ISR bit-0 = 1)

sleep mode of all channels are enabled (IER bit-4 = 1)

modem inputs are not toggling (MSR bits 0-3 = 0)

RX input pins are idling HIGH

The M564 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The M564 resumes normal operation by any of the following:

■

a receive data start bit transition (HIGH to LOW)

a data byte is loaded to the transmitter, THR or FIFO

a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the M564 is awakened by any one of the above conditions, it will return to the sleep mode automatically after

all interrupting conditions have been serviced and cleared. If the M564 is awakened by the modem inputs, a

read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while

an interrupt is pending from any channel. The M564 will stay in the sleep mode of operation until it is disabled

by setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain

steady when the M564 is in sleep mode, the maximum current will be in the microamp range as specified in the

DC Electrical Characteristics on page 40. If the input lines are floating or are toggling while the M564 is in

sleep mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an

external buffer would be required to keep the address, data and control lines steady to achieve the low current.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the

first few receive characters may be lost. Also, make sure the RX A-D pins are idling HIGH or “marking”

condition during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or

another type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the

system design engineer can use a 47k ohm pull-up resistor on each of the RX A-D inputs.

2.18

Internal Loopback

The M564 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,

DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else

upon exiting the loopback test the UART may detect and report a false “break” signal.

22

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

F

IGURE 13. INTERNAL LOOP BACK IN CHANNELS A - D

VCC

TX A-D

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RX A-D

VCC

RTS# A-D

RTS#

CTS#

CTS# A-D

VCC

DTR# A-D

DTR#

DSR#

RI#

DSR# A-D

OP1#

RI# A-D

OP2#

CD#

CD# A-D

23

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

3.0 UART INTERNAL REGISTERS

REV. 1.0.0

Each UART channel in the M564 has its own set of configuration registers selected by address lines A0, A1

and A2 with a specific channel selected (See Table 1 and Table 2). The complete register set is shown on

Table 9 and Table 10.

TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS

A2,A1,A0 ADDRESSES

R

EGISTER

READ/WRITE

COMMENTS

16C550 COMPATIBLE

REGISTERS

0

0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

0

0 0

0 1

1 0

0 1

1 0

DLL - Divisor LSB

Read/Write

0

DLM - Divisor MSB

LCR[7] = 1, LCR ≠ 0xBF

DLD - Divisor Fractional

IER - Interrupt Enable Register

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

0

1

1 1

0 0

0 1

1 0

1 1

LCR - Line Control Register

MCR - Modem Control Register

LSR - Line Status Register

MSR - Modem Status Register

SPR - Scratch Pad Register

Read/Write

LCR[7] = 0

E

NHANCED REGISTERS

0

1

1 0

0 0

0 1

1 0

1 1

EFR - Enhanced Function Reg

Xon-1 - Xon Character 1

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

Read/Write

LCR = 0xBF

24

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

TABLE 10: INTERNAL REGISTERS DESCRIPTION.

S

HADED BITS ARE ENABLED WHEN EFR BIT-4=1

A

DDRESS

R

EG

R

EAD

/

BIT-7

BIT-6

B

IT-5

BIT-4

B

IT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

W

RITE

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

Bit-0

WR

IER RD/WR

Modem RXLine

Stat. Int.

Enable

TX

Empty

Int

RX

Data

Int.

Stat.

Int.

CTS#

Int.

Enable Enable

RTS# Xoff Int.

Int.

Sleep

Mode

Enable

Enable Enable Enable

LCR[7] = 0

0 1 0

ISR

RD

FIFOs

Enabled Enabled

FIFOs

0/

INT

Source Source Source Source

Bit-3

RTS

CTS

Int

Xoff

Int

Bit-2

Bit-1

Bit-0

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0/

DMA

Mode

Enable

TX

FIFO

Reset Reset

RX

FIFOs

FIFO Enable

TXFIFO TXFIFO

Trigger

0 1 1

1 0 0

LCR RD/WR Divisor Set TX

Set

Even

Parity

Enable

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

Parity

MCR RD/WR

0/

Internal INT Out- Rsvd

Lopback

Enable

RTS# DTR#

Output Output

Control Control

put

Enable

(OP1#)

BRG

Pres-

caler

IR Mode Xon Any

ENable

(OP2#)

1 0 1

LSR RD/WR RXFIFO THR &

THR

RX Break

RX

Global

Error

TSR

Empty

Parity Over-

Data LCR[7] = 0

Ready

Framing

Error

run

Error

1 1 0

1 1 1

MSR RD/WR

SPR RD/WR

CD#

Input

RI#

Input

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

Delta

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

Baud Rate Generator Divisor

0 0 0

0 0 1

0 1 0

DLL RD/WR

DLM RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7]=1

LCR≠0xBF

DLD RD/WR Rsvd

Rsvd 4X Mode 8X Mode

Bit-0 LCR[7] = 1

LCR≠0xBF

EFR[4] = 1

25

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

A

DDRESS

R

EG

R

EAD

/

BIT-7

BIT-6

B

IT-5

BIT-4

B

IT-3

BIT-2

B

IT-1

BIT-0

COMMENT

A2-A0

NAME

W

RITE

Enhanced Registers

0 1 0

EFR RD/WR

Auto

CTS#

Enable Enable

Auto

RTS#

Special

Char

Select

Enable

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

IER [7:4],

ISR [5:4],

FCR[5:4],

MCR[7:5],

DLD

Bit-2

Bit-1

Bit-0

Bit-3

LCR=0XBF

1 0 0

1 0 1

1 1 0

1 1 1

XON1 RD/WR

XON2 RD/WR

XOFF1 RD/WR

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 17.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 15.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

26

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M564 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

Logic 0 = Disable the receive data ready interrupt (default).

Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

Logic 0 = Disable Transmit Ready interrupt (default).

Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an

overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.

•

Logic 0 = Disable the receiver line status interrupt (default).

Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

•

Logic 0 = Disable the modem status register interrupt (default).

Logic 1 = Enable the modem status register interrupt.

IER[4]: Sleep Mode Enable (requires EFR[4] = 1)

•

Logic 0 = Disable Sleep Mode (default).

Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)

•

Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)

Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for

details.

27

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)

REV. 1.0.0

•

Logic 0 = Disable the RTS# interrupt (default).

Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from LOW to HIGH (if enabled by EFR bit-6).

IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)

•

Logic 0 = Disable the CTS# interrupt (default).

Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

LOW to HIGH (if enabled by EFR bit-7).

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table, Table 11, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

•

LSR is by any of the LSR bits 1, 2, 3 and 4.

RXRDY is by RX trigger level.

RXRDY Time-out is by a 4-char plus 12 bits delay timer.

TXRDY is by TX trigger level or TX FIFO empty.

MSR is by any of the MSR bits 0, 1, 2 and 3.

Receive Xoff/Special character is by detection of a Xoff or Special character.

CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.

RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

4.4.2

Interrupt Clearing:

•

LSR interrupt is cleared by a read to the LSR register.

RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

RXRDY Time-out interrupt is cleared by reading RHR.

TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

MSR interrupt is cleared by a read to the MSR register.

Xoff interrupt is cleared by a read to the ISR register or when XON character(s) is received.

Special character interrupt is cleared by a read to ISR register or after next character is received.

RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

28

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

]

T

ABLE 11: INTERRUPT

S

OURCE AND

P

RIORITY

L

EVEL

OURCE OF INTERRUPT

P

RIORITY

ISR REGISTER

STATUS

BITS

S

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

0

1

0

1

0

1

0

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

0

1

0

1

0

1

ISR[0]: Interrupt Status

•

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

•

Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source

Table 11).

ISR[4]: Interrupt Status (requires EFR bit-4 = 1)

This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match

of the Xoff character(s) or a special character.

ISR[5]: Interrupt Status (requires EFR bit-4 = 1)

ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

•

Logic 0 = Disable the transmit and receive FIFO (default).

Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

29

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

FCR[1]: RX FIFO Reset

REV. 1.0.0

This bit is only active when FCR bit-0 is a ‘1’.

•

Logic 0 = No receive FIFO reset (default)

Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

•

Logic 0 = No transmit FIFO reset (default).

Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.

•

Logic 0 = Normal Operation (default).

Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)

(logic 0 = default, TX trigger level = one)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the

FIFO did not get filled over the trigger level on last re-load. Table 12 below shows the selections.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when

the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections.

TABLE 12: TRANSMIT AND

RECEIVE FIFO TRIGGER LEVEL SELECTION

R

ECEIVE

T

RANSMIT

FCR FCR FCR

FCR

BIT-4

TRIGGER

BIT-7

BIT-6

BIT-5

L

EVEL

LEVEL

0

1

0

1

0

1

16

8

24

30

0

1

0

1

0

1

8

16

24

30

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5 (default)

6

7

8

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

S

TOP BIT LENGTH

W

ORD

BIT-2

LENGTH

5,6,7,8

5

(BIT TIME

(S))

0

1

1 (default)

1-1/2

2

6,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 13 for parity selection summary below.

•

Logic 0 = No parity.

Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

•

Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

31

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

LCR[5]: TX and RX Parity Select

REV. 1.0.0

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

•

LCR BIT-5 = LOW, parity is not forced (default).

LCR BIT-5 = HIGH and LCR BIT-4 = LOW, parity bit is forced to a logical 1 for the transmit and receive data.

LCR BIT-5 = HIGH and LCR BIT-4 = LOW, parity bit is forced to a logical 0 for the transmit and receive data.

TABLE 13: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

P

ARITY SELECTION

No parity

X

0

1

X

0

1

0

1

0

1

Odd parity

Even parity

Force parity to mark, HIGH

Forced parity to space, LOW

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space’, LOW, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

•

Logic 0 = No TX break condition. (default)

Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM/DLD) enable.

•

Logic 0 = Data registers are selected. (default)

Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

•

Logic 0 = Force DTR# output HIGH (default).

Logic 1 = Force DTR# output LOW.

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by

EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.

•

Logic 0 = Force RTS# output HIGH (default).

Logic 1 = Force RTS# output LOW.

MCR[2]: Reserved

OP1# is not available as an output pin on the M564. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

32

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

MCR[3]: INT Output Enable

Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL

input, see below table for details. This bit is also used to control the OP2# signal during internal loopback

mode. INTSEL pin must be LOW during 68 mode.

•

Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode,

OP2# is HIGH.

Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.

TABLE 14: INT OUTPUT MODES

INTSEL MCR

INT A-D OUTPUTS IN 16 MODE

P

IN

BIT-3

0

Three-State

Active

0

1

X

Active

MCR[4]: Internal Loopback Enable

•

Logic 0 = Disable loopback mode (default).

Logic 1 = Enable local loopback mode, see loopback section and Figure 13.

MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)

•

Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and

the M564 is programmed to use the Xon/Xoff flow control.

MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)

•

Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output

will be LOW during idle data conditions.

MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)

•

Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

Baud Rate Generator without further modification, i.e., divide by one (default).

Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

33

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

4.8

Line Status Register (LSR) - Read/Write

This register is writeable but it is not recommended. The LSR provides the status of data transfers between the

UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits 2-4

will generate an interrupt when a character with an error is in the RHR.

LSR[0]: Receive Data Ready Indicator

•

Logic 0 = No data in receive holding register or FIFO (default).

Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Flag

•

Logic 0 = No overrun error (default).

Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Tag

•

Logic 0 = No parity error (default).

Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

•

Logic 0 = No framing error (default).

Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

LSR[4]: Receive Break Tag

•

Logic 0 = No break condition (default).

Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX

input returns to the idle condition, “mark” or HIGH.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to HIGH when the last data byte is

transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently

with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the

transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to HIGH whenever the transmitter goes idle. It is set to LOW whenever either the THR or TSR

contains a data character. In the FIFO mode this bit is set to HIGH whenever the transmit FIFO and transmit

shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

•

Logic 0 = No FIFO error (default).

Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

34

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

4.9

Modem Status Register (MSR) - Read/Write

This register is writeable but it is not recommended. The MSR provides the current state of the modem

interface input signals. Lower four bits of this register are used to indicate the changed information. These bits

are set to a HIGH whenever a signal from the modem changes state. These bits may be used for general

purpose inputs when they are not used with modem signals.

MSR[0]: Delta CTS# Input Flag

•

Logic 0 = No change on CTS# input (default).

Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

•

Logic 0 = No change on DSR# input (default).

Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

•

Logic 0 = No change on RI# input (default).

Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

•

Logic 0 = No change on CD# input (default).

Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto

CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the

modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has

finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the compliment of

the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The

CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.10 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

35

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write

REV. 1.0.0

These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL

gives the 16-bit divisor value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate

divisor. DLD must be enabled via EFR bit-4 before it can be accessed. See Table 15 below and See ”Section

2.8, Programmable Baud Rate Generator with Fractional Divisor” on page 13.

DLD[5:4]: Sampling Rate Select

These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will

double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 15 below.

TABLE 15: SAMPLING RATE SELECT

DLD[5]

DLD[4]

S

AMPLING

16X

RATE

0

1

0

1

X

8X

4X

DLD[7:6]: Reserved

4.12 Enhanced Feature Register (EFR) - Read/Write

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 16). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

36

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

TABLE 16: SOFTWARE

FLOW CONTROL FUNCTIONS

EFR BIT-3

EFR BIT-2

EFR BIT-1 EFR BIT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

CONT-1

CONT-0

CONT-3

CONT-2

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

0

X

0

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

0

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

1

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD

to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a LOW to latch the new values. This

feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is

recommended to leave it enabled, HIGH.

•

Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-

7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,

and MCR bits 5-7, and DLD are set to a LOW to be compatible with ST16C550 mode (default).

•

Logic 1 = Enables the above-mentioned register bits to be modified by the user.

EFR[5]: Special Character Detect Enable

•

Logic 0 = Special Character Detect Disabled (default).

Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

37

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

EFR[6]: Auto RTS Flow Control Enable

REV. 1.0.0

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and

RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data

falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the

auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is

disabled.

•

Logic 0 = Automatic RTS flow control is disabled (default).

Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

•

Logic 0 = Automatic CTS flow control is disabled (default).

Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic

1. Data transmission resumes when CTS# returns to a LOW.

4.13 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.

For more details, see Table 8.

38

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

TABLE 17: UART RESET CONDITIONS FOR CHANNELS A-D

REGISTERS

RESET STATE

DLM, DLL

DLM = 0x00 and DLL = 0x01. Only resets to these val-

ues during a power up. They do not reset when the

Reset Pin is asserted.

DLD

RHR

THR

IER

Bits 7-0 = 0x00

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

SPR

EFR

Bits 7-0 = 0xFF

Bits 7-0 = 0x00

RESET STATE

HIGH

XON1

XON2

XOFF1

XOFF2

I/O SIGNALS

TX

RTS#

HIGH

DTR#

HIGH

RXRDY#

TXRDY#

HIGH

LOW

INT

XR16M564 = Three-State Condition (INTSEL = LOW)

XR16M564 = LOW (INTSEL = HIGH)

XR16M564D = LOW

(16 Mode)

IRQ#

Three-State Condition (INTSEL = LOW)

(68 Mode)

39

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

4 Volts

GND-0.3 V to 4 V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja = 28^oC/W, theta-jc = 10.5^oC/W

Thermal Resistance (48-QFN)

theta-ja = 49^oC/W, theta-jc = 10^oC/W

Thermal Resistance (64-LQFP)

theta-ja = 39^oC/W, theta-jc = 17^oC/W

Thermal Resistance (68-PLCC)

theta-ja = 37^oC/W, theta-jc = 7^oC/W

Thermal Resistance (80-LQFP)

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

U

NLESS OTHERWISE NOTED: TA = -40^OTO +85^OC, VCC IS 1.62 TO 3.63V

L

IMITS

L

IMITS

LIMITS

S

OL

YMB

P

ARAMETER

1.8V

2.5V

3.3V

UNITS

CONDITIONS

M

IN

M

AX

M

IN

M

AX

M

IN

MAX

V_ILCKClock Input Low Level

V_IHCKClock Input High Level

-0.3

1.4

0.3

VCC

0.2

-0.3

2.0

0.2

VCC

0.6

-0.3

2.4

0.6

VCC

0.8

V

V_IL

V_IH

V_OL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.3

1.4

-0.3

2.0

-0.3

2.2

VCC

0.4

V

I_OL= 4 mA

I_OL= 2 mA

I_OL= 1.5 mA

0.4

V_OHOutput High Voltage

2.0

V

I_OH= -1 mA

1.8

I_OH= -400 uA

I_OH= -200 uA

1.4

I_IL

I_IH

Input Low Leakage Current

±15

5

±15

5

±15

5

uA

pF

Input High Leakage Current

Input Pin Capacitance

Power Supply Current

C_IN

I_CC

1

1.5

200

2

mA Ext Clk = 2MHz

uA See Test 1

I_SLEEPSleep Current

150

250

Test 1: The following inputs remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-D7, IOR#, IOW#,

CSA#, CSB#, CSC#, and CSD#. Also, RXA, RXB, RXC, and RXD inputs must idle at HIGH while asleep.

40

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

TA = -40^OTO +85^OC, VCC IS 1.62 TO 3.63V, 70

P

F

LOAD WHERE APPLICABLE

IMITS IMITS

L

LIMITS

S

YMBOL

P

ARAMETER

1.8V ± 10%

2.5V ± 10%

3.3V ± 10%

UNIT

M

IN

MAX

M

IN

MAX

M

IN

MAX

XTAL1

ECLK

T_ECLK

UART Crystal Frequency

External Clock Frequency

External Clock Time Period

24

MHz

ns

32

50

64

15

0

10

0

7

0

T_AS

T_AH

Address Setup Time (16 Mode)

Address Hold Time (16 Mode)

Chip Select Width (16 Mode)

IOR# Strobe Width (16 Mode)

Read Cycle Delay (16 Mode)

Data Access Time (16 Mode)

Data Disable Time (16 Mode)

IOW# Strobe Width (16 Mode)

Write Cycle Delay (16 Mode)

Data Setup Time (16 Mode)

Data Hold Time (16 Mode)

Address Setup (68 Mode)

ns

0

T_CS

100

65

50

T_RD

T_DY

T_RDV

T_DD

95

15

60

15

45

15

T_WR

T_DY

100

15

3

65

10

3

50

10

3

T_DS

T_DH

T_ADS

T_ADH

T_RWS

T_RDA

T_RDH

T_WDS

T_WDH

T_RWH

0

Address Hold (68 Mode)

0

R/W# Setup to CS# (68 Mode)

Data Access Time (68 mode)

Data Disable Time (68 mode)

Write Data Setup (68 mode)

Write Data Hold (68 Mode)

0

95

15

60

15

45

15

3

10

5

10

5

CS# De-asserted to R/W# De-

asserted (68 Mode)

3

T_CSL

T_CSD

T_WDO

T_MOD

CS# Strobe Width (68 Mode)

CS# Cycle Delay (68 Mode)

Delay From IOW# To Output

100

65

50

ns

50

Delay To Set Interrupt From MODEM

Input

41

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

REV. 1.0.0

TA = -40^OTO +85^OC, VCC IS 1.62 TO 3.63V, 70

P

F

LOAD WHERE APPLICABLE

IMITS IMITS

L

LIMITS

S

YMBOL

P

ARAMETER

1.8V ± 10%

2.5V ± 10%

3.3V ± 10%

UNIT

M

IN

MAX

M

IN

MAX

M

IN

MAX

T_RSI

T_SSI

T_RRI

T_SI

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

Delay From IOR# To Reset Interrupt

Delay From Start To Interrupt

50

ns

Bclk

ns

1

45

24

45

24

45

24

ns

T_INT

Delay From Initial INT Reset To

Transmit Start

8

Bclk

T_WRI

T_SSR

T_RR

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

45

1

45

1

45

1

ns

Bclk

ns

45

8

45

8

45

8

T_WT

ns

T_SRT

Delay From Center of Start To Reset

TXRDY#

Bclk

T_RST

Bclk

Reset Pulse Width

Baud Clock

40

ns

16X or 8X or 4X of data rate

Hz

F

IGURE 14. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

42

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

F

IGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D

IO W #

IO W

A c tiv e

T _W

D O

R T S #

D T R #

C h a n g e o f s ta te

C D #

C T S #

D S R #

C h a n g e o f s ta te

T _{M O D}

IN T

A c tiv e

T _{R S I}

IO R #

A c tiv e

T _{M O D}

C h a n g e o f s ta te

R I#

F

IGURE 16. 16 MODE (INTEL) DATA

B

US

R

EAD

TIMING FOR

C

HANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_RD

IOR#

D0-D7

T_DD

T_RDV

Valid Data

RDTm

43

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

F

IGURE 17. 16 MODE (INTEL) DATA

B

US

WRITE

TIMING FOR

C

HANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_WR

IOW#

D0-D7

T_DH

T_DS

Valid Data

T_DS

Valid Data

16Write

F

IGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

TADS

TCSL

TADH

T

CSD

T

RWS

T

RWH

R/W#

D0-D7

T

RDH

TRDA

Valid Data

68Read

44

XR16M564/564D

REV. 1.0.0

IGURE 19. 68 MODE (MOTOROLA) DATA

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

F

B

US

WRITE

T

IMING FOR

C

HANNELS A-D

A0-A7

CS#

Valid Address

TADS

TCSL

T

ADH

T

CSD

T

RWS

T

RWH

T

R/W#

D0-D7

WDH

T

WDS

Valid Data

68Write

F

IGURE 20. RECEIVE

R

EADY & INTERRUPT

TIMING [NON-FIFO MODE] FOR CHANNELS A-D

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

45

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

F

IGURE 21. TRANSMIT

R

EADY & INTERRUPT

TIMING [NON-FIFO MODE] FOR CHANNELS A-D

TX

(Unloading)

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

F

IGURE 22. RECEIVE

R

EADY & INTERRUPT

TIMING [FIFO MODE, DMA DISABLED

]

FOR CHANNELS A-D

Start

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

46

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

F

IGURE 23. RECEIVE

R

EADY & INTERRUPT

TIMING [FIFO MODE, DMA ENABLED

]

FOR

C

HANNELS A-D

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

T_SSI

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

F

IGURE 24. TRANSMIT

R

EADY & INTERRUPT

TIMING [FIFO MODE, DMA MODE

D

ISABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

S

D0:D7

T

S

D0:D7

T

D0:D7

T

D0:D7

T

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

47

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

F

IGURE 25. TRANSMIT

R

EADY & INTERRUPT

TIMING [FIFO MODE, DMA MODE

E

NABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

S

D0:D7

S

T

D0:D7

S

D0:D7

T

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

48

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

PACKAGE DIMENSIONS

48 LEAD QUAD FLAT NO LEAD (7 x 7 x 0.9 mm, 0.50 mm pitch QFN)

Note: The actual center pad is

metallic and the size (D2) is

device-dependent with a typical

tolerance of 0.3mm. The lead

may be half-etched terminal.

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

0.80

0.00

0.15

6.85

5.10

0.18

MAX

1.00

0.05

0.25

7.15

5.30

0.30

A

A1

A3

D

0.031

0.000

0.006

0.270

0.201

0.007

0.039

0.002

0.010

0.281

0.209

0.012

D2

b

e

0.0197 BSC

0.50 BSC

L

0.012

0.008

0.020

-

0.30

0.20

0.50

-

k

49

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

64 LEAD LOW-PROFILE QUAD FLAT PACK (10 x 10 x 1.4 mm LQFP)

REV. 1.0.0

D

D₁

48

33

49

32

D₁

D

64

17

1

16

B

A₂

e

C

A

α

Seating Plane

A₁

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

1.45

0.27

0.20

12.20

10.10

A

A1

A2

B

0.055

0.002

0.053

0.007

0.004

0.465

0.390

0.063

0.006

0.057

0.011

0.008

0.480

0.398

1.40

0.05

1.35

0.17

0.09

11.80

9.90

C

D

D1

e

0.020 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

50

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

D

C

Seating Plane

D₁

45° x H

1

A₂

45° x H

2

2 1 68

B₁

B

D

3

D

2

D

1

e

R

D

3

A₁

A

Note: The control dimension is the inch column

INCHES MILLIMETERS

SYMBOL

MIN

0.165

0.090

MAX

0.200

0.130

MIN

MAX

5.08

3.30

A

4.19

2.29

A

1

2

0.020

---.

0.51

---

B

0.013

0.026

0.021

0.032

0.33

0.66

0.53

0.81

B

1

C

0.008

0.985

0.950

0.013

0.995

0.958

0.19

25.02

24.13

0.32

25.27

24.33

D

1

2

3

D

0.890

0.930

22.61

23.62

0.800 typ.

0.050 BSC

0.042

20.32 typ.

1.27 BSC

e

H

0.056

0.048

0.045

1.07

0.64

1.42

1.22

1.14

1

2

0.042

0.025

R

51

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

80 LEAD PLASTIC QUAD FLAT PACK (12 mm x 12 mm LQFP, 1.4 mm Form)

REV. 1.0.0

p

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

1.45

0.27

0.20

14.20

12.20

A

A1

A2

B

0.055

0.002

0.053

0.007

0.004

0.543

0.465

0.063

0.006

0.057

0.011

0.008

0.559

0.480

1.40

0.05

1.35

0.17

0.09

13.80

11.80

C

D

D1

e

0.0197 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

52

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

REVISION HISTORY

D

ATE

REVISION

DESCRIPTION

August 2007

May 2008

Rev P1.0.0 Preliminary Datasheet.

Rev 1.0.0

Final Datasheet. Updated DC and AC Electrical Characteristics.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet May 2008.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

53

XR16M564/564D

REV. 1.0.0

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................ 1

F

A

EATURES.................................................................................................................................................... 1

PPLICATIONS .............................................................................................................................................. 1

F

IGURE 1. XR16M564 BLOCK DIAGRAM .......................................................................................................................................... 1

IGURE 2. PIN

IGURE 3. PIN

O

UT

A

SSIGNMENT

F

OR 68-PIN PLCC PACKAGES

OR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE............................................................... 3

IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES ......................... 2

OUT

ASSIGNMENT

PIN DESCRIPTIONS ........................................................................................................ 4

ORDERING INFORMATION ............................................................................................................................... 4

1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9

2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10

2.1 CPU INTERFACE .............................................................................................................................................. 10

FIGURE 4. XR16M564 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS.......................................................................... 10

2.2 DEVICE RESET................................................................................................................................................. 11

2.3 CHANNEL SELECTION .................................................................................................................................... 11

TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 11

TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 11

2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 12

2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 12

TABLE 3: INT PIN

O

PERATION FOR

T

RANSMITTER FOR

C

HANNELS A-D ........................................................................................... 12

TABLE 4: INT PIN

O

PERATION FOR

R

ECEIVER FOR

CHANNELS A-D ................................................................................................. 12

2.6 DMA MODE ....................................................................................................................................................... 12

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 13

2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13

FIGURE 5. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 13

2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13

FIGURE 6. BAUD

RATE GENERATOR ............................................................................................................................................... 14

TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 15

2.9 TRANSMITTER.................................................................................................................................................. 15

2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15

2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................... 16

F

IGURE 7. TRANSMITTER

O

PERATION IN NON-FIFO MODE .............................................................................................................. 16

2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16

ODE ..................................................................................... 16

FIGURE 8. TRANSMITTER

OPERATION IN FIFO AND FLOW CONTROL M

2.10 RECEIVER....................................................................................................................................................... 17

2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 17

F

IGURE 9. RECEIVER

O

PERATION IN NON-FIFO MODE.................................................................................................................... 17

UTO RTS FLOW ODE ....................................................................... 18

FIGURE 10. RECEIVER

PERATION IN FIFO AND

A

CONTROL M

2.11 AUTO RTS (HARDWARE) FLOW CONTROL................................................................................................ 18

2.12 AUTO RTS HYSTERESIS ............................................................................................................................... 18

TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 18

2.13 AUTO CTS FLOW CONTROL......................................................................................................................... 19

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19

2.14 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20

TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 20

2.15 SPECIAL CHARACTER DETECT.................................................................................................................. 20

2.16 INFRARED MODE ........................................................................................................................................... 21

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 21

2.17 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 22

2.18 INTERNAL LOOPBACK................................................................................................................................. 22

FIGURE 13. INTERNAL LOOP BACK IN CHANNELS A - D................................................................................................................... 23

3.0 UART INTERNAL REGISTERS............................................................................................................. 24

TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 24

TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ....................................... 25

4.0 INTERNAL REGISTER DESCRIPTIONS.............................................................................................. 26

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY.................................................................................. 26

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 27

1

XR16M564/564D

1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28

4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28

4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28

TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 29

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 29

TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31

TABLE 13: PARITY SELECTION ........................................................................................................................................................ 32

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 32

TABLE 14: INT OUTPUT MODES ..................................................................................................................................................... 33

4.8 LINE STATUS REGISTER (LSR) - READ/WRITE ............................................................................................ 34

4.9 MODEM STATUS REGISTER (MSR) - READ/WRITE...................................................................................... 35

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 35

4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 36

TABLE 15: SAMPLING RATE SELECT ............................................................................................................................................... 36

4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 36

TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37

4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE................... 38

TABLE 17: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 39

ABSOLUTE MAXIMUM RATINGS.................................................................................. 40

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40

ELECTRICAL CHARACTERISTICS ............................................................................... 40

DC ELECTRICAL

AC ELECTRICAL

TA = -40O TO +85

C

HARACTERISTICS ............................................................................................................. 40

HARACTERISTICS ............................................................................................................. 41

C, VCC IS 1.62 TO 3.63V, 70 LOAD WHERE APPLICABLE ........................................... 41

O

T

PF

F

IGURE 14. CLOCK

IGURE 15. MODEM

IMING............................................................................................................................................................. 42

HANNELS A-D .................................................................................................... 43

HANNELS A-D.................................................................................... 43

HANNELS A-D.................................................................................. 44

HANNELS A-D........................................................................... 44

IMING [NON-FIFO MODE HANNELS A-D ............................................................ 45

US RITE IMING FOR HANNELS A-D ......................................................................... 45

EADY & INTERRUPT IMING [NON-FIFO MODE HANNELS A-D .......................................................... 46

IMING [FIFO MODE, DMA DISABLED

IMING [FIFO MODE, DMA ENABLED

I

NPUT/OUTPUT

T

B

IMING

F

OR

EAD

RITE

US

C

IGURE 16. 16 MODE (INTEL) DATA

IGURE 17. 16 MODE (INTEL) DATA

IGURE 18. 68 MODE (MOTOROLA) DATA

IGURE 20. RECEIVE EADY & INTERRUPT

IGURE 19. 68 MODE (MOTOROLA) DATA

IGURE 21. TRANSMIT

IGURE 22. RECEIVE

IGURE 23. RECEIVE

IGURE 24. TRANSMIT

IGURE 25. TRANSMIT

US

R

W

T

IMING FOR

EAD IMING FOR C

C

T

B

R

T

R

T

] FOR C

B

W

T

C

R

T

] FOR C

READY & INTERRUPT

]

FOR

C

HANNELS A-D........................................... 46

READY & INTERRUPT

CHANNELS A-D............................................ 47

R

EADY & INTERRUPT

T

IMING [FIFO MODE, DMA MODE

D

ISABLED

]

FOR

C

HANNELS A-D............................... 47

E

NABLED

]

FOR

CHANNELS A-D ............................... 48

P

R

ACKAGE

EVISION

D

H

IMENSIONS ................................................................................................................................ 49

ISTORY...................................................................................................................................... 53

2


型号：	XR16M564IJ-0A-EVB
厂家：	EXAR CORPORATION
描述：	EVAL BOARD FOR XR16M654-A 68PLCC
文件：	总55页 (文件大小：1080K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16M564IJ-0A-EVB [EXAR]

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