XR16M780IL32 [EXAR]
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO; 1.62V至3.63V高性能的64字节FIFO的UART型号: | XR16M780IL32 |
厂家: | EXAR CORPORATION |
描述: | 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO |
文件: | 总58页 (文件大小:1184K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
SEPTEMBER 2008
REV. 1.0.0
FEATURES
GENERAL DESCRIPTION
•
Pin-to-pin compatible with XR16L580 in 32-QFN
and 48-TQFP packages
1
The XR16M780 (M780) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
64 bytes of transmit and receive FIFOs,
programmable transmit and receive FIFO trigger
levels, automatic hardware and software flow control,
and data rates of up to 16 Mbps at 3.3V, 12.5 Mbps at
2.5V and 7.5 Mbps at 1.8V with 4X data sampling
rate.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Intel or Motorola Bus Interface select
16Mbps maximum data rate
Programmable TX/RX FIFO Trigger Levels
TX/RX FIFO Level Counters
Independent TX/RX Baud Rate Generator
Fractional Baud Rate Generator
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
Auto RTS/CTS Hardware Flow Control
Auto XON/XOFF Software Flow Control
Auto RS-485 Half-Duplex Direction Control
Multidrop mode w/ Auto Address Detect
Sleep Mode with Automatic Wake-up
PowerSave mode
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M780 can be minimized by enabling the sleep mode
and PowerSave mode.
Infrared (IrDA 1.0 and 1.1) mode
1.62V to 3.63V supply operation
Crystal oscillator or external clock input
The M780 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M780 is available in 32-pin
QFN, 48-pin TQFP and 25-pin BGA packages. All
three packages offer both the 16 mode (Intel bus)
interface and the 68 mode (Motorola bus) interface
which allows easy integration with Motorola
processors.
APPLICATIONS
•
•
•
•
•
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
N
OTE: 1 Covered by U.S. Patent #5,649,122.
F
IGURE 1. XR16M780 BLOCK DIAGRAM
VCC
(1.62 to 3.63 V)
PwrSave
A2:A0
GND
D7:D0
IOR#
UART
TX, RX,
IOW# (R/W#)
CS#
64 Byte TX FIFO
UART
Regs
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
TX &
RX
IR
ENDEC
INT (IRQ#)
Intel or
Motorola
Data Bus
Interface
RESET
(RESET#)
64 Byte RX FIFO
BRG
16/68#
XTAL1
XTAL2
Crystal Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 2. PIN
O
UT ASSIGNMENT FOR 32-PIN QFN AND 48-PIN TQFP PACKAGES IN 16 AND 68 MODE
24
23
22 21 20 19 18
17
16
24 23 22 21 20 19 18 17
NC
DSR# 25
NC
NC
14 IOR#
DSR# 25
16
15
CD#
RI#
VCC
D0
26
27
28
29
30
31
15
14
13
CD#
26
RI#
27
VCC
28
NC
IOR #
GND
IOW #
XTAL 2
XTAL 1
PwrSave
VCC
32-pin QFN in
Motorola Bus
Mode
32- pin QFN in
Intel Bus Mode
13
GND
29
30
31
32
12
11
10
9
D0
D1
D2
D3
12
11
10
9
R/W#
XTAL
XTAL
D1
D2
2
1
32
D3
PwrSave
7
3 4 5 6
8
1
2 3 4 5 6
7 8
2
1
GND
VCC
36 35 34 33 32 31 30 29 28 27 26 25
24
36 35 34 33 32 31 30 29 28 27 26 25
37
NC
NC
NC
NC
NC
IOR#
GND
NC
NC
37
38
39
40
41
42
43
44
45
46
47
24
NC
NC
23
22
21
20
19
18
17
16
15
14
13
38
39
40
41
42
43
44
45
46
47
NC
NC
NC
NC
IOR#
GND
23
22
21
20
19
18
17
16
15
14
13
CTS#
DSR#
CD#
RI#
VCC
D0
CTS#
DSR#
CD#
RI#
VCC
D0
48-TQFP in
Intel Bus Mode
48-TQFP in
Motorola Bus Mode
VCC
D1
D2
D3
D4
D1
D2
D3
D4
NC
R/W#
XTAL2
XTAL1
IOW#
XTAL2
XTAL1
PwrSave
48
1
48
1
NC
NC
PwrSave
2
3 4 5 6 7 8 9 10 11 12
2
3 4 5 6 7 8 9 10 11 12
GND
VCC
2
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
SSIGNMENT FOR 25-PIN BGA PACKAGE
REV. 1.0.0
IGURE 3. PIN
F
O
UT
A
A1 Corner
1 2 3 4
5
A
B
C
D
E
Transparent Top View
CTS#
VCC
D0
RESET
16/68#
D6
INT
RTS#
D7
A1
A0
A2
IOR#
IOW#
XTAL1
GND
PwrSave
CS#
D3
D1
TX
D4
D2
D5
RX
ORDERING INFORMATION
O
PERATING
T
EMPERATURE
P
ART
N
UMBER
P
ACKAGE
DEVICE STATUS
RANGE
XR16M780IL32
XR16M780IM48
XR16M780IB25
32-Pin QFN
48-Lead TQFP
25-Pin BGA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Active
Active
Active
3
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
32-QFN 48-TQFP 25-BGA
NAME
TYPE
DESCRIPTION
P
IN
#
PIN#
PIN#
DATA BUS INTERFACE
A2
A1
A0
17
18
19
26
27
28
A5
A4
B4
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART channel during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
5
4
4
C3
C2
E3
E1
D1
E2
D2
C1
I/O
Data bus lines [7:0] (bidirectional).
3
3
2
1
47
46
45
44
43
32
31
30
29
IOR#
14
19
B5
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
IOW#
12
16
C5
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
(R/W#)
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CS#
8
11
30
D4
A3
I
This input is chip select (active low) to enable the device.
INT
20
O
When 16/68# pin is at logic 1 for Intel bus interface, this output
(IRQ#)
(OD) become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX D3
7
8
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
4
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
Pin Description
32-QFN 48-TQFP 25-BGA
NAME
TYPE
DESCRIPTION
P
IN
#
PIN#
PIN#
RX
6
7
E4
B3
A1
I
O
I
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
RTS#
CTS#
21
24
32
38
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
DTR#
DSR#
22
25
33
39
-
-
O
I
UART Data-Terminal-Ready (active low) or general purpose output.
UART Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used.
CD#
RI#
26
27
40
41
-
-
I
I
UART Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used.
ANCILLARY SIGNALS
XTAL1
XTAL2
10
11
9
14
15
13
D5
-
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
PwrSave
C4
Power-Save (active high). This feature isolates the M780’s data bus
interface from the host preventing other bus activities that cause
higher power drain during sleep mode. See Sleep Mode with Auto
Wake-up and Power-Save Feature section for details. This pin does
not have an internal pull-down resistor. This input should be con-
nected to GND when not used.
16/68#
2
1
B2
A2
I
I
Intel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or
Intel Mode, the device will operate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface. This pin does not
have an internal pull-up or pull-down resistor.
RESET
23
35
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes RESET (active high). When 16/68# pin is at logic 0 for
Motorola bus interface, this input becomes RESET# (active low).
(RESET#)
A 40 ns minimum active pulse on this pin will reset the internal reg-
isters and all outputs of the UART. The UART transmitter output will
be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see UART Reset Conditions).
VCC
GND
GND
28
13
42
18
-
B1
E5
-
Pwr
Pwr
Pwr
1.62V to 3.63V power supply.
Power supply common, ground.
Center
Pad
The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
5
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
Pin Description
REV. 1.0.0
32-QFN 48-TQFP 25-BGA
NAME
TYPE
DESCRIPTION
P
IN
#
PIN#
P
IN#
NC
15, 16
5, 6, 9,
10, 12,
-
No Connects.
-
17, 20-
25, 29,
31, 34,
36, 37, 48
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
6
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16M780 (M780) is a high performance single-channel UART. It has its set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, the M780 channel has 64 bytes of transmit and receive FIFOs, Automatic RTS/CTS Hardware
Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder
(IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and
data rate up to 16 Mbps. The XR16M780 can operate from 1.62 to 3.63 volts. The M780 is fabricated with an
advanced CMOS process.
Larger FIFO
The M780 provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes
in the XR16L580. The M780 is designed to work with high performance data communication systems, that
requires fast data processing time. Increased performance is realized in the M780 by the larger transmit and
receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external
processor to handle more networking tasks within a given time. For example, the XR16L580 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 64 byte FIFO in the M780, the data buffer will not require unloading/loading for 6.1
ms. This increases the service interval giving the external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt
and automatic hardware/software flow control is uniquely provided for maximum data throughput performance
especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s
bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The M780 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate. The device can
operate at 3.3V with a 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on
XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler
bit and sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the M780 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/
decoder, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. The M780 includes new features
such as 9-bit (Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX,
fast IR mode and fractional baud rate generator.
7
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
REV. 1.0.0
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M780 data interface supports the Intel and Motorola compatible types of CPUs. No
clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous
using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is
shown in Figure 4.
F
IGURE 4. XR16M780 TYPICAL
INTEL/MOTOROLA
DATA
B
US
I
NTERCONNECTIONS
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
16/68#
TX
RX
Serial Transceivers of
RS-232
RS-485
RS-422
DTR#
A0
A1
A2
A0
A1
A2
RTS#
CTS#
DSR#
CD#
Or Infrared
IOR#
IOW#
IOR#
IOW#
CS#
UART_CS#
UART_INT
RI#
INT
POWERSAVE
UART_RESET
PwrSave
GND
RESET
Intel Data Bus Interconnections
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TX
RX
Serial Transceivers of
RS-232
A0
A1
A2
DTR#
A0
A1
A2
RS-485
RS-422
Or Infrared
RTS#
CTS#
DSR#
CD#
IOR#
IOW#
CS#
VCC
R/W#
UART_CS#
vcc
RI#
UART_IRQ#
POWERSAVE
UART_RESET#
INT
16/68#
GND
PwrSave
RESET
Motorola Data Bus Interconnections
8
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.2
Serial Interface
The M780 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical
connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422
transceivers, go to www.exar.com or send an e-mail to uarttechsupport@exar.com.
F
IGURE 5. XR16M780 TYPICAL SERIAL INTERFACE CONNECTIONS
V C C
V C C
R S -232
T ransceiver
T X
R X
T1 IN
R 1 O U T
D T R #
T 2IN
T 3IN
R T S #
C T S #
D S R #
C D #
U A R T
R 2O U T
R 3O U T
R 4O U T
R I#
R 5O U T
G N D
G N D
R S -232 F u ll-M o d em S erial In terface
VCC
VCC
RS-485
Transceiver
Full-duplex
TX+
TX-
TX
RX
DI
RO
VCC
NC
NC
RTS#
VCC
RX+
RX-
DTR#
CTS#
DSR#
UART
DE
RE#
CD
#
#
RI
GND
RS-485 Full-Duplex Serial Interface
9
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 6. XR16M780 TYPICAL
S
ERIAL
INTERFACE
C
ONNECTIONS
VCC
VCC
RS-485
Y
Z
Transceiver
Half-duplex
TX
RX
DI
RO
DE
RTS#
VCC
A
RE#
NC
DTR#
CTS#
DSR#
UART
B
CD
#
RI#
GND
RS-485 Half-Duplex Serial Interface
VCC
VCC
IR
Transceiver
TX
TXD
RXD
RX
NC
NC
DTR#
RTS#
CTS#
DSR#
CD#
UART
VCC
RI#
GND
Infrared Connection
10
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Table 18). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device. Following a power-on reset or an external reset, the M780 is software compatible with previous
generation of UARTs, XR16L580 and ST16C550.
2.4
Internal Registers
The M780 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M780 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR, FC and TRIG) that provide automatic RTS and CTS hardware flow
control, automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control,
different baud rate for TX and RX and fractional baud rate generator. All the register functions are discussed in
full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 25.
2.5
INT Ouput
The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2
summarize the operating behavior for the transmitter and receiver. Also see Figure 22 through 25.
NOTE: The IRQ# pin requires a pull-up resistor for proper operation.
T
ABLE 1: INT PIN PERATION FOR
O
T
RANSMITTER
FCR BIT-0 = 1 (FIFO ENABLED
LOW = FIFO above trigger level
FCR BIT-0 = 0 (FIFO DISABLED
)
)
INT Pin
LOW = One byte in THR
HIGH = THR empty
(16/68# = 1)
HIGH = FIFO below trigger level or FIFO empty
IRQ# Pin
HIGH = One byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
(16/68# = 0)
LOW = FIFO below trigger level or FIFO empty
TABLE 2: INT PIN
O
PERATION FOR
R
ECEIVER
FCR BIT-0 = 0 (FIFO DISABLED
)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
HIGH = One byte in RHR
LOW = RHR empty
LOW = FIFO below trigger level
(16/68# = 1)
HIGH = FIFO above trigger level or RX Data Timeout
IRQ# Pin
LOW = One byte in RHR
HIGH = RHR empty
HIGH = FIFO below trigger level
(16/68# = 0)
LOW = FIFO above trigger level or RX Data Timeout
11
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
2.6
Crystal Oscillator or External Clock Input
The M780 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a
crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock
for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRGs) in the
UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For
programming details, see “Section 2.7, Programmable Baud Rate Generator with Fractional Divisor” on
page 13.
F
IGURE 7. TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2
R1
0-120
(Optional)
R2
500K - 1M
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47pF
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in Figure 7. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
generator for standard or custom rates. The BGA package has XTAL1 only, the external clock is required. For
further reading on oscillator circuit, see application note DAN108 on EXAR’s web site.
12
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.7
Programmable Baud Rate Generator with Fractional Divisor
The M780 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescalers are controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescalers
to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
16
further divides this clock by a programmable divisor between 1 and (2 - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling. For transmitter and receiver, the M780 provides
respective BRG divisors. The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL =
0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization
to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD
registers provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value
from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 3 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 3. At 8X sampling rate, these
data rates would double. And at 4X sampling rate, they would quadruple. Also, when using 8X sampling mode,
please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number.
When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the
following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
The closest divisor that is obtainable in the M780 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
2.7.1
Independent TX/RX BRG
The XR16M780 has two independent sets of TX and RX baud rate generator. See Figure 8. TX and RX can
work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data to the
remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting,
please See ”Section 4.13, Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write” on
page 39.
13
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
FIGURE 8. BAUD
R
ATE
G
ENERATOR
DLD[7]=0
16X or 8X or 4X
Sampling Rate Clock
to Transmitter
DLL
DLM
DLD[5:0]
Prescaler
Divide by 1
-
MCR Bit 7=0
(default)
Crystal
Osc/
Buffer
XTAL1
XTAL2
0
1
16X or 8X or 4X
Sampling Rate Clock
to Receiver
MCR Bit-7=1
DLL
DLM
Prescaler
Divide by 4
DLD[5:0]
DLD[7]=1
DLD[6]
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
D
IVISOR FOR 16x
Clock
(Decimal)
DIVISOR
BTAINABLE IN
DLM PROGRAM DLL PROGRAM DLD PROGRAM
ALUE (HEX) ALUE (HEX) ALUE (HEX)
DATA ERROR
O
V
V
V
R
ATE (%)
M780
400
2400
3750
625
3750
625
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6
71
38
9C
96
4E
3C
34
27
1E
1A
14
F
0
0
8
4
0
2
0
1
1
0
1
0
0
0
C
8
B
8
0
0
C
4
0
0
A
8
0
0
4800
312.5
156.25
150
312 8/16
156 4/16
150
0
9600
0
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
0
78.125
60
78 2/16
60
0
0
52.0833
39.0625
30
52 1/16
39 1/16
30
0.04
0
0
26.0417
20
26 1/16
20
0.08
0
15
15
0
13.0208
9.7656
7.5
13
D
0.16
0.16
0
9 12/16
7 8/16
6 11/16
6 8/16
6
9
7
6.6667
6.5104
6
6
0.31
0.16
0
6
6
5
5
5
0
3.75
3 12/16
3 4/16
3
3
0
3.2552
3
3
0.16
0
3
2
2
2
0
1.6276
1.5
1 10/16
1 8/16
1
0.16
0
1
14
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.8
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16/8/4 clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
2.8.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.8.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
F
IGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X or 8X or 4X
Clock
( DLD[5:4] )
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
15
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
2.8.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
F
IGURE 10. TRANSMITTER
O
PERATION IN FIFO AND FLOW CONTROL MODE
Transmit
FIFO
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
16X or 8X or 4X Clock
(DLD[5:4])
Transmit Data Shift Register
(TSR)
TXFIFO1
2.9
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0. See Figure 11 and Figure 12 below.
2.9.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
16
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
F
IGURE 11. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
F
IGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example
- RX FIFO trigger level selected at 16 bytes
:
(See Note Below)
64 bytes by 11-bit wide
FIFO
Data falls to
8
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data FIFO
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
56
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data
Receive Data
Byte and Errors
RXFIFO1
17
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.10 Auto RTS (Hardware) Flow Control
REV. 1.0.0
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 13):
•
•
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
•
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.11 Auto RTS Hysteresis
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the selected RX
trigger level. The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches one trigger level
above the selected trigger level in the trigger table (Table 9). The RTS# pin will return LOW after the RX FIFO
is unloaded to one level below the selected trigger level. Under the above described conditions, the M780 will
continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS#
output pin is asserted LOW (RTS On).
TABLE 4: AUTO RTS (HARDWARE) FLOW
CONTROL
RTS# D
E
-
ASSERTED (HIGH
)
RTS# ASSERTED (LOW)
R
X
TRIGGER
LEVEL
INT PIN ACTIVATION
(CHARACTERS IN
RX
F
IFO
)
(CHARACTERS IN RX FIFO)
8
8
16
56
60
60
0
8
16
56
60
16
56
60
16
56
2.12 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 13):
•
Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend
18
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after
the CTS# input is re-asserted (LOW), indicating more data may be sent.
F
IGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
TXB
Receiver FIFO
Trigger Reached
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto RTS
Auto CTS
Monitor
Trigger Level
Receiver FIFO
Trigger Reached
Transmitter
CTSA#
RTSB#
Auto CTS
Monitor
Auto RTS
Trigger Level
Assert RTS# to Begin
Transmission
1
10
ON
ON
ON
RTSA#
OFF
7
2
ON
11
OFF
CTSB#
TXB
8
3
Restart
Data Starts
6
Suspend
9
4
RXA FIFO
Receive
Data
RX FIFO
Trigger Level
RTS High
Threshold
RTS Low
Threshold
5
RX FIFO
Trigger Level
12
INTA
(RXA FIFO
Interrupt)
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
19
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
2.13 Auto Xon/Xoff (Software) Flow Control
REV. 1.0.0
When software flow control is enabled (See Table 17), the M780 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the M780 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the M780 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the M780 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 17) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the M780 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the M780 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The M780 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level. To clear this condition, the M780 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed
trigger level. Table 5 below explains this.
TABLE 5: AUTO
XON/XOFF (SOFTWARE) FLOW CONTROL
X
OFF
C
HARACTER
(
S
) SENT
XON CHARACTER(S) SENT
RX TRIGGER
LEVEL
INT PIN
ACTIVATION
(
CHARACTERS IN RX FIFO
)
(
CHARACTERS IN RX FIFO)
8
8
8*
0
8
16
56
60
16
56
60
16*
56*
60*
16
56
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.14
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The M780 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the
Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
2.15 Normal Multidrop Mode
Normal multidrop mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR[5] = 0 (Special Character
Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
20
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
2.15.1 Auto Address Detection
Auto address detection mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
2.16 Infrared Mode
The M780 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1
standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit
data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 14 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the
infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to
be compatible to the IrDA 1.1 standard, MSR bit-7 will also need to be set to a ’1’ when EFR bit-4 is set to ’1’.
Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 14.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
21
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 14. INFRARED
TRANSMIT
D
ATA
E
NCODING AND
R
ECEIVE
D
ATA
D
ECODING
Character
Data Bits
1
1
1
1
1
0
0
0
0
0
TX Data
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 or 1/4 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
1
1
1
1
0
0
0
0
0
RX Data
Data Bits
Character
IRdecoder-1
2.17 Sleep Mode with Auto Wake-Up and Power-Save feature
The M780 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save
feature is included to reduce its power consumption when the chip is not actively used.
2.17.1 Sleep mode
All of these conditions must be satisfied for the M780 to enter sleep mode:
■
■
■
■
■
■
no interrupts pending (ISR bit-0 = 1)
sleep mode is enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pin is idling HIGH in normal mode or LOW in infrared mode
divisor is non-zero
TX and RX FIFOs are empty
The M780 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The M780 resumes normal operation by any of the following:
■
■
■
a receive data start bit transition (HIGH to LOW)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the M780 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the M780 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
22
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
an interrupt is pending from any channel. The M780 will stay in the sleep mode of operation until it is disabled
by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX pin is idling HIGH or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on each of the RX input.
2.17.2 Power-Save Feature
If the address lines, data bus lines, IOW#, IOR#, CS# and modem input lines remain steady when the M780 is
in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 45. If the input lines are floating or are toggling while the M780 is in sleep mode, the
current can be up to 100 times more. If not using the Power-Save feature, an external buffer would be required
to keep the address and data bus lines from toggling or floating to achieve the low current. But if the Power-
Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by
internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that
could cause wasteful power drain. The M780 enters Power-Save mode when this pin is connected to VCC and
the M780 is in sleep mode (see Sleep Mode section above).
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■
■
a receive data start bit transition (HIGH to LOW) at the RX input or
a change of logic state on the modem or general purpose serial input CTS#, DSR#, CD#, RI#
The M780 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem input
CTS#) and all interrupting conditions have been serviced and cleared. The M780 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND.
2.17.3 Wake-up Interrupt
The M780 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The
default status of wake up interrupt is disabled. Please See ”Section 4.5, FIFO Control Register (FCR) -
Write-Only” on page 31.
23
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
2.18
Internal Loopback
The M780 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate
normally. Figure 15 shows how the modem port signals are re-configured. Transmit data from the transmit shift
register output is internally routed to the receive shift register input allowing the system to receive the same
data that it was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted,
and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
F
IGURE 15. INTERNAL LOOPBACK
VCC
TX
Transm it Shift Register
(THR/FIFO )
M CR bit-4=1
Receive Shift Register
(RHR/FIFO)
RX
VCC
RTS#
RTS#
CTS#
CTS#
DTR#
VCC
DTR#
DSR#
RI#
DSR#
RI#
O P1#
O P2#
CD#
CD#
24
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
3.0 UART INTERNAL REGISTERS
The complete register set for the M780 is shown in Table 6 and Table 7.
ABLE 6: UART INTERNAL REGISTERS
T
A2 A1 A0
R
EGISTER
READ/WRITE
COMMENTS
ADDRESSES
16C550 COMPATIBLE
REGISTERS
0
0
0
0
0
0 0
0 1
0 0
0 1
1 0
DREV - Device Revision
Read-only
Read-only
Read/Write
Read/Write
Read/Write
LCR[7] = 1, LCR ≠ 0xBF,
DLL = 0x00, DLM = 0x00
DVID - Device Identification Register
DLL - Divisor LSB Register
LCR[7] = 1, LCR ≠ 0xBF
See DLD[7:6]
DLM - Divisor MSB Register
DLD - Divisor Fractional Register
LCR[7] = 1, LCR ≠ 0xBF,
EFR[4] = 1
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0
0 1
1 0
IER - Interrupt Enable Register
Read/Write
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7] = 0 if EFR[4] = 1
or
LCR ≠ 0xBF if EFR[4] = 0
0
1
1
1
1
1 1
0 0
0 1
1 0
1 0
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
Read/Write
Read/Write
Read-only
Read-only
Write-only
LCR ≠ 0xBF
MSR - Modem Status Register
MSR - Modem Status Register
LCR ≠ 0xBF
EFR[4] = 1
1
1
1
1 1
1 1
1 1
SPR - Scratch Pad Register
Read/Write
Write-only
Read-only
LCR ≠ 0xBF, FCTR[6] = 0
EMSR - Enhanced Mode Select Register
FC - RX/TX FIFO Level Counter Register
LCR ≠ 0xBF, FCTR[6] = 1
E
NHANCED REGISTERS
0
0
0
0
1
1
1
1
0 0
0 0
0 1
1 0
0 0
0 1
1 0
1 1
FC - RX/TX FIFO Level Counter Register
Read-only
Write-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
TRIG - RX/TX FIFO Trigger Level Register
FCTR - Feature Control Register
EFR - Enhanced Function Reg
Xon-1 - Xon Character 1
LCR = 0xBF
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
25
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
A
DDRESS
R
EG
R
EAD
/
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
W
RITE
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat. Int.
Enable
TX
Empty
Int
RX
Data
Int.
LCR[7] = 0
Stat.
Int.
CTS#
Int.
Enable Enable
RTS#
Int.
Xoff Int.
Enable
Sleep
Mode
Enable
Enable Enable Enable
0 1 0
ISR
RD
FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
Source Source Source Source
LCR[7] = 0
if EFR[4]=1
RTS
CTS
Interrupt
Xoff
Bit-3
Bit-2
Bit-1
Bit-0
Interrupt
or
LCR≠0xBF
if EFR[4]=0
0 1 0
0 1 1
FCR
WR RXFIFO RXFIFO TXFIFO TXFIFO Wake up
Trigger Trigger Trigger
TX
RX
FIFOs
Trigger Int Enable FIFO
FIFO Enable
Reset Reset
LCR RD/WR Divisor Set TX
Set
Even
Parity
Stop
Word
Word
Enable
Break
Parity
Enable
Bits Length Length
Parity
Bit-1 Bit-0
1 0 0
1 0 1
MCR RD/WR
0/
0/
0/
Internal INT Out- OP1# RTS# DTR#
Lopback
Enable
put
Enable
Output Output
Control Control
BRG
Pres-
caler
IR Mode XonAny
ENable
(OP2#)
LSR
RD
RXFIFO THR &
THR
RX Break RX Fram-
RX
RX
RX
Global
Error
TSR
Empty
Empty
ing Error Parity Over-
Data
Ready
Error
run
Error
LCR≠0xBF
1 1 0
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
WR
Fast IR Enable Disable Disable
0
0
0
0
9-bit
RX
TX
mode
1 1 1
1 1 1
SPR RD/WR
Bit-7
Xoff
Bit-6
LSR
Bit-5
RTS
Bit-4
RTS
Bit-3
Bit-2
Bit-1
Bit-0 LCR≠0xBF
FCTR[6]=0
EMSR
WR
Invert
Send
TX
FIFO
count
FIFO
count
interrupt interrupt delay bit- delay bit- RTS in
mode
select
mode
select
3
2
RS485
mode
imme- control control
LCR≠0xBF
FCTR[6]=1
diate
bit-1
bit-0
1 1 1
FC
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
26
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
A
DDRESS
R
EG
R
EAD
/
BIT-7
B
IT-6
B
IT-5
B
IT-4
B
IT-3
B
IT-2
B
IT-1
B
IT-0
COMMENT
A2-A0
NAME
W
RITE
Baud Rate Generator Divisor
0 0 0
0 0 1
DREV
DVID
RD
RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
1
Bit-2
0
Bit-1
0
Bit-0 LCR[7] = 1
LCR≠0xBF
1
DLL= 0x00
DLM= 0x00
0 0 0
0 0 1
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0 LCR[7] = 1
LCR≠0xBF
Bit-0
DLD[7:6]
0 1 0
DLD RD/WR BRG
Enable 4X Mode 8X Mode
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7] = 1
LCR≠0xBF
select Indepen-
dent
BRG
EFR[4] = 1
Enhanced Registers
0 0 0
0 0 0
0 0 1
FC
RD
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
invert
Bit-1
Bit-1
RTS
Bit-0
Bit-0
TRIG
WR
FCTR RD/WR RX/TX
select
Swap
SCR
trigger
mode
bit-1
trigger
mode
RS485
interrupt RX IR delay
mode
RTS
delay
bit-0
bit-1
bit-0
0 1 0
EFR RD/WR
Auto
CTS#
Enable Enable
Auto
RTS#
Special
Char
Select
Enable
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
IER [7:4],
ISR [5:4],
FCR[5:3],
MCR[7:5],
DLD
LCR=0XBF
Cntl
Bit-2
Bit-1
Bit-0
Bit-3
1 0 0
1 0 1
1 1 0
1 1 1
XON1 RD/WR
XON2 RD/WR
XOFF1 RD/WR
XOFF2 RD/WR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 16.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 15.
27
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M780 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error. However,
when EMSR bit-6 changes to 1 (default is 0), LSR bit 2-4 generate an interrupt when the character is received
in the RX FIFO. Please refer to “Section 4.12, Enhanced Mode Select Register (EMSR) - Write-only” on
page 38.
•
•
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
28
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
IER[3]: Modem Status Interrupt Enable
•
•
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
•
•
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
•
•
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
•
•
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from LOW to HIGH (if enabled by EFR bit-6).
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
•
•
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH (if enabled by EFR bit-7).
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
•
•
•
•
•
•
•
•
•
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
Wakeup interrupt is generated when the M780 wakes up from the sleep mode.
29
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
4.4.2
Interrupt Clearing:
•
•
•
•
•
•
•
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xon or Xoff interrupt is cleared by a read to the ISR register. See EMSR[7].
Special character interrupt is cleared by a read to ISR register or after next character is received. See
EMSR[7].
•
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wakeup interrupt is cleared by a read to ISR register.
•
]
T
ABLE 8: INTERRUPT
S
OURCE AND
P
RIORITY
L
EVEL
OURCE OF INTERRUPT
P
RIORITY
ISR REGISTER
STATUS
BITS
S
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
6
7
-
0
0
0
1
1
0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
MSR (Modem Status Register)
0
1
0
0
0
0
RXRDY (Received Xon, Xoff or Special character)
CTS#, RTS# change of state
1
0
0
0
0
0
0
0
0
0
0
1
None (default) or Wakeup interrupt
ISR[0]: Interrupt Status
•
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
•
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
30
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
enable the wake up interrupt. They are defined as follows:
FCR[0]: TX and RX FIFO Enable
•
•
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)
•
•
Logic 0 = Disable the wake up interrupt (default).
Logic 1 = Enable the wake up interrupt.
Please refer to “Section 2.17.3, Wake-up Interrupt” on page 23.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 9 below shows the selections. Note that the
receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to
both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
31
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
T
T
RANSMIT
RIGGER
EVEL
T
T
RIGGER FCTR FCTR
FCR
FCR
IT-6
FCR
FCR
BIT-4
R
ECEIVE
COMPATIBILITY
ABLE
BIT-5
BIT-4
BIT-7
B
BIT-5
T
RIGGER EVEL
L
L
Table-A
0
0
0
0
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580
0
0
1
1
0
1
0
1
1 (default)
4
8
14
Table-B
0
1
1
1
0
1
0
0
1
1
0
1
0
1
16
8
16C650A
24
30
0
0
1
1
0
1
0
1
8
16
24
28
Table-C
0
0
1
1
0
1
0
1
8
16C654
16
32
56
0
0
1
1
0
1
0
1
8
16
56
60
Table-D
X
X
X
X
Programmable Programmable 16L2752, 16C2850,
16C2852, 16C850,
16C854, 16C864
via TRG
via TRG
register.
register.
FCTR[7] = 0.
FCTR[7] = 1.
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
32
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
S
TOP BIT LENGTH
W
ORD
BIT-2
LENGTH
5,6,7,8
5
(BIT TIME
(S))
0
1
1
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
•
•
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
•
•
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•
•
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
•
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 10: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
P
ARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, HIGH
Forced parity to space, LOW
33
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
LCR[6]: Transmit Break Enable
REV. 1.0.0
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
•
•
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
•
•
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW. It is required to start Auto RTS Flow Control.
MCR[2]: Reserved
OP1# is not available as an output pin on the M780. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This bit is also used to control the OP2#
signal during internal loopback mode.
•
•
Logic 0 = INT output disabled (three state) in the 16 mode (default). During internal loopback mode, OP2# is
HIGH.
Logic 1 = INT output enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.
TABLE 11: INT OUTPUT
MODES
MCR
INT OUTPUT 16 MODE
I
N
BIT-3
0
Three-State
Active
1
34
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
MCR[4]: Internal Loopback Enable
•
•
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 15.
MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)
•
•
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the M780 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)
•
•
Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be LOW during idle data conditions.
MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)
•
•
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR
bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
•
•
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
•
•
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
•
•
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
•
•
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
35
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
LSR[4]: Receive Break Tag
REV. 1.0.0
•
•
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or HIGH.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
•
•
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals. Reading the higher four bits shows the status of the modem signals.
MSR[0]: Delta CTS# Input Flag
•
•
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
•
•
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
•
•
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
•
•
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
36
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS Flow Control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10 Modem Status Register (MSR) - Write Only
This register provides the advanced features of XR16M780. Lower four bits of this register are reserved.
Writing to the higher four bits enables additional functions.
MSR[3:0]: Reserved
MSR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
•
•
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.
MSR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
•
•
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
MSR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
For the 9-bit mode information, See ”Section 2.15, Normal Multidrop Mode” on page 20.
•
•
Logic 0 = Normal 8-bit mode (default).
Logic 1 = Enable 9-bit or Multidrop mode.
MSR[7]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M780 supports the new fast IR transmission with data rate up to 1.152 Mbps.
•
•
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
See ”Section 2.16, Infrared Mode” on page 21.
4.11 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
37
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
4.12 Enhanced Mode Select Register (EMSR) - Write-only
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
REV. 1.0.0
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0]
Scratchpad is
Scratchpad
0
1
1
1
X
X
0
1
X
0
1
1
RX FIFO Level Counter Mode
TX FIFO Level Counter Mode
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[2]: Send TX Immediately
•
•
Logic 0 = Do not send TX immediately (default).
Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the
TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only
1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If
more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
EMSR[3]: Invert RTS in RS485 mode
•
•
Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
38
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
EMSR[5:4]: Extended RTS Hysteresis
TABLE 13: AUTO RTS HYSTERESIS
RTS#
YSTERESIS
EMSR
EMSR
FCTR
FCTR
H
BIT-5
BIT-4
BIT-1
BIT-0
(CHARACTERS
)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
±4
±6
±8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
±8
±16
±24
±32
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
±40
±44
±48
±52
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
±12
±20
±28
±36
EMSR[6]: LSR Interrupt Mode
•
•
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
•
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
•
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
4.13 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M780 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M780 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 14 below and See ”Section 2.7, Programmable
Baud Rate Generator with Fractional Divisor” on page 13.
39
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
DLD[5:4]: Sampling Rate Select
REV. 1.0.0
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.
TABLE 14: SAMPLING RATE SELECT
DLD[5]
DLD[4]
S
AMPLING
16X
RATE
0
0
1
0
1
X
8X
4X
DLD[6]: Independent BRG enable
•
•
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0]. .
TABLE 15: BRG SELECT
DLD[7]
DLD[6]
BRG
0
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
0
1
1
1
1
0
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
4.14 Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.15 RX/TX FIFO Level Count Register (FC) - Read-Only
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See Table 12.
40
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data.
4.16 Feature Control Register (FCTR) - Read/Write
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See Table 13 for more details.
FCTR[2]: IrDa RX Inversion
•
•
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
FCTR[3]: Auto RS-485 Direction Control
•
•
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 16 for more details.
TABLE 16: TRIGGER
TABLE SELECT
FCTR
FCTR
TABLE
BIT-5
BIT-4
0
0
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
0
1
1
0
1
1
FCTR[6]: Scratchpad Swap
•
•
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
•
•
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
4.17 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 17). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
41
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
EFR[3:0]: Software Flow Control Select
REV. 1.0.0
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 17: SOFTWARE
FLOW CONTROL FUNCTIONS
EFR BIT-3
EFR BIT-2
EFR BIT-1 EFR BIT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
CONT-1
CONT-0
CONT-3
CONT-2
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
1
0
1
0
X
X
X
X
0
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
0
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, and DLD
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
•
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 3-5,
and MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
•
Logic 1 = Enables the EFR[3:0] register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
•
•
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
42
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
•
•
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.18 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 5. The xoff2 is also used as auto address detect register when the auto 9-bit mode
enabled. See ”Section 2.15.1, Auto Address Detection” on page 21.
43
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
TABLE 18: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these val-
ues during a power up. They do not reset when the
Reset Pin is asserted.
(Both TX and RX)
DLD
RHR
THR
IER
Bits 7-0 = 0x00
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
FCR
ISR
LCR
MCR
LSR
MSR
Bits 7-0 =0xX0 (Read-only)
Bits 7-4 = 0000 (Write-only)
SPR
EMSR
FC
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
RESET STATE
HIGH
TRG
FCTR
EFR
XON1
XON2
XOFF1
XOFF2
I/O SIGNALS
TX
RTS#
HIGH
DTR#
HIGH
INT
Three-State Condition
(16 Mode)
IRQ#
HIGH
(68 Mode)
44
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
3.6 Volts
GND-0.3 V to 3.6 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja = 33oC/W, theta-jc = 22oC/W
Thermal Resistance (32-QFN)
theta-ja = 59oC/W, theta-jc = 16oC/W
Thermal Resistance (48-TQFP)
theta-ja = 166oC/W, theta-jc = 98.2oC/W
Thermal Resistance (25-BGA)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
U
NLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V
LIMITS
LIMITS
LIMITS
S
YMBOL
P
ARAMETER
1.8V
2.5V
3.3V
UNITS
CONDITIONS
MIN
MAX
MIN
MAX
M
IN
MAX
VILCK Clock Input Low Level
VIHCK Clock Input High Level
-0.3
1.4
0.3
-0.3
2.0
0.4
-0.3
2.4
0.6
VCC
0.7
V
V
V
V
VCC
0.2
VCC
0.5
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.3
1.4
-0.3
1.8
-0.3
2.0
VCC
VCC
VCC
0.4
V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 1.5 mA
0.4
0.4
VOH
Output High Voltage
2.0
V
V
IOH = -4 mA
IOH = -2 mA
IOH = -200 uA
1.8
1.4
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
±15
±15
5
±15
±15
5
±15
±15
5
uA
uA
pF
CIN
ICC
Power Supply Current
1.5
3
2
2.5
15
mA Ext Clk = 5MHz
uA See Test 1
ISLEEP/ Sleep / Power Save Current
(16 and 68 modes)
6
IPWRSV
Test 1: The following inputs remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-D7, IOR#, IOW#,
CS#. Also, RX input must idle at HIGH while asleep.
For Power-Save, the UART internally isolates all of these inputs (except the modem inputs, 16/68# and Reset pins) there-
fore eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWER-SAVE FEATURE” ON
45
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
PAGE 23. To achieve minimum power drain, the voltage at any of the inputs of the M780 should NOT be lower than its VCC
supply.
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 1.62 TO 3.6V, 70
P
F
LOAD WHERE APPLICABLE
IMITS IMITS
L
L
LIMITS
S
YMBOL
P
ARAMETER
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
UNIT
M
IN
MAX
M
IN
MAX
M
IN
MAX
XTAL1
ECLK
TECLK
UART Crystal Frequency
External Clock Frequency
External Clock Time Period
24
24
24
MHz
MHz
ns
30
50
64
15
0
9
0
7
0
0
TAS
TAH
Address Setup Time (16 Mode)
Address Hold Time (16 Mode)
Chip Select Width (16 Mode)
IOR# Strobe Width (16 Mode)
Read Cycle Delay (16 Mode)
Data Access Time (16 Mode)
Data Disable Time (16 Mode)
IOW# Strobe Width (16 Mode)
Write Cycle Delay (16 Mode)
Data Setup Time (16 Mode)
Data Hold Time (16 Mode)
Address Setup (68 Mode)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
TCS
90
90
90
60
60
60
35
35
35
TRD
TDY
TRDV
TDD
85
25
55
10
30
5
TWR
TDY
90
90
30
3
60
60
15
3
35
35
10
3
TDS
TDH
TADS
TADH
TRWS
TRDA
TRDH
TWDS
TWDH
TRWH
5
0
0
Address Hold (68 Mode)
0
0
0
R/W# Setup to CS# (68 Mode)
Data Access Time (68 mode)
Data Disable Time (68 mode)
Write Data Setup (68 mode)
Write Data Hold (68 Mode)
0
0
0
85
15
55
15
30
15
15
3
10
3
10
3
CS# De-asserted to R/W# De-
asserted (68 Mode)
3
3
3
TCSL
TCSD
TWDO
CS# Strobe Width (68 Mode)
CS# Cycle Delay (68 Mode)
Delay From IOW# To Output
90
90
60
60
35
35
ns
ns
ns
50
50
50
46
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 1.62 TO 3.6V, 70
P
F
LOAD WHERE APPLICABLE
IMITS IMITS
L
L
LIMITS
S
YMBOL
P
ARAMETER
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
UNIT
M
IN
MAX
M
IN
MAX
M
IN
MAX
TMOD
Delay To Set Interrupt From MODEM
Input
50
50
50
ns
TRSI
TSSI
TRRI
TSI
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Start To Interrupt
50
1
50
1
50
1
ns
Bclk
ns
45
45
24
45
45
24
45
45
24
ns
TINT
Delay From Initial INT Reset To
Transmit Start
8
8
8
Bclk
TWRI
TSSR
TRR
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
45
1
45
1
45
1
ns
Bclk
ns
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
45
45
8
45
45
8
45
45
8
TWT
ns
TSRT
Delay From Center of Start To Reset
TXRDY#
Bclk
TRST
Bclk
Reset Pulse Width
Baud Clock
40
40
40
ns
16X or 8X or 4X of data rate
Hz
F
IGURE 16. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
47
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 17. MODEM INPUT/OUTPUT TIMING
IO W #
IO W
A c tiv e
T W
D O
R T S #
D T R #
C h a n g e o f s ta te
C h a n g e o f s ta te
C D #
C T S #
D S R #
C h a n g e o f s ta te
C h a n g e o f s ta te
T M O D
T M O D
IN T
A c tiv e
A c tiv e
A c tiv e
A c tiv e
T R S I
IO R #
A c tiv e
A c tiv e
T M O D
C h a n g e o f s ta te
R I#
F
IGURE 18. 16 MODE (INTEL) DATA BUS READ TIMING
A0-A2
CS#
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
TDY
TRD
TRD
IOR#
D0-D7
TDD
TDD
TRDV
TRDV
Valid Data
Valid Data
RDTm
48
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
F
IGURE 19. 16 MODE (INTEL) DATA BUS WRITE TIMING
A0-A2
CS#
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
TDY
TWR
TWR
IOW#
D0-D7
TDH
TDH
TDS
Valid Data
TDS
Valid Data
16Write
F
IGURE 20. 68 MODE (MOTOROLA) DATA BUS READ TIMING
A0-A2
CS#
Valid Address
Valid Address
ADS
T
CSL
T
ADH
T
CSD
T
RWS
T
RWH
T
R/W#
D0-D7
RDH
T
RDA
T
Valid Data
Valid Data
68Read
49
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 21. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
A0-A2
CS#
Valid Address
Valid Address
ADS
T
CSL
T
ADH
T
CSD
T
RWS
T
RWH
T
R/W#
D0-D7
T
WDH
WDS
T
Valid Data
Valid Data
68Write
F
IGURE 22. RECEIVE
R
EADY & INTERRUPT
TIMING [NON-FIFO MODE]
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Active
Data
Active
Data
RXRDY#
Ready
Ready
Ready
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
50
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
F
IGURE 23. TRANSMIT
R
EADY & INTERRUPT
TIMING [NON-FIFO MODE]
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
F
IGURE 24. RECEIVE
R
EADY & INTERRUPT
TIMING [FIFO MODE]
Start
Bit
RX
S
S
S
S
T
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
S
T
S
D0:D7
T
D0:D7
T
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
51
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
F
IGURE 25. TRANSMIT
R
EADY & INTERRUPT
TIMING [FIFO MODE
]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
T
S
T
S
D0:D7
D0:D7
T
S
D0:D7
T
D0:D7
T
D0:D7
D0:D7
T
ISR is read
TSI
IER[1]
enabled
ISR is read
TSRT
INT*
TX FIFO
Empty
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
52
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm
)
Note: the actual center pad
is metallic and the size (D2)
is device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.039
0.002
0.010
0.201
0.150
0.012
MIN
0.80
0.00
0.15
4.90
3.50
0.18
MAX
1.00
0.05
0.25
5.10
3.80
0.30
A
A1
A3
D
0.031
0.000
0.006
0.193
0.138
0.007
D2
b
e
0.0197 BSC
0.50 BSC
L
0.012
0.008
0.020
-
0.35
0.20
0.45
-
k
53
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm
)
D
D1
36
25
37
24
D1
D
48
13
1
1
2
B
e
A2
C
A
Seating
Plane
A1
α
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
0.047
0.006
0.041
0.011
0.008
0.362
0.280
A
A1
A2
B
0.039
0.002
0.037
0.007
0.004
0.346
0.272
1.00
0.05
0.95
0.17
0.09
8.80
6.90
1.20
0.15
1.05
0.27
0.20
9.20
7.10
C
D
D1
e
0.020 BSC
0.50 BSC
L
0.018
0×
0.030
7×
0.45
0×
0.75
7×
a
54
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
PACKAGE DIMENSIONS (25 PIN BGA - 3 X 3 X 0.8 mm
)
5
4
3
2
1
A1 corner
A
B
C
D
E
D
D1
D1
D
(A1 corner feature is mfger option)
Seating
Plane
b
A2
A
A1
e
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.031
0.007
0.024
0.122
MIN
MAX
0.80
0.19
0.61
3.10
A
A1
A2
D
0.028
0.005
0.022
0.114
0.70
0.13
0.57
2.90
D1
b
0.079 BSC
0.012
0.020 BSC
2.00 BSC
0.50 BSC
0.008
0.20
0.30
e
55
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
REVISION HISTORY
D
ATE
REVISION
DESCRIPTION
September 2008
Rev 1.0.0
Final Datasheet.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet September 2008.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
56
XR16M780
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
GENERAL DESCRIPTION................................................................................................ 1
F
A
EATURES.................................................................................................................................................... 1
PPLICATIONS .............................................................................................................................................. 1
F
F
F
IGURE 1. XR16M780 BLOCK DIAGRAM .......................................................................................................................................... 1
IGURE 2. PIN
IGURE 3. PIN
O
UT
A
SSIGNMENT
F
F
OR 32-PIN QFN AND 48-PIN TQFP PACKAGES
OR 25-PIN BGA PACKAGE........................................................................................................... 3
IN 16 AND 68 MODE............................................. 2
OUT
ASSIGNMENT
ORDERING INFORMATION ............................................................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................ 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8
2.1 CPU INTERFACE ................................................................................................................................................ 8
FIGURE 4. XR16M780 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS............................................................................ 8
2.2 SERIAL INTERFACE........................................................................................................................................... 9
FIGURE 5. XR16M780 TYPICAL
S
ERIAL
I
NTERFACE
C
ONNECTIONS ................................................................................................... 9
FIGURE 6. XR16M780 TYPICAL
S
ERIAL
I
NTERFACE
C
ONNECTIONS ................................................................................................. 10
2.3 DEVICE RESET................................................................................................................................................. 11
2.4 INTERNAL REGISTERS.................................................................................................................................... 11
2.5 INT OUPUT ........................................................................................................................................................ 11
TABLE 1: INT PIN
O
PERATION FOR
T
RANSMITTER ........................................................................................................................... 11
TABLE 2: INT PIN
O
PERATION FOR
R
ECEIVER ................................................................................................................................ 11
2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 12
FIGURE 7. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 12
2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13
2.7.1 INDEPENDENT TX/RX BRG......................................................................................................................................... 13
FIGURE 8. BAUD
RATE GENERATOR ............................................................................................................................................... 14
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 14
2.8 TRANSMITTER.................................................................................................................................................. 15
2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15
2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................... 15
F
IGURE 9. TRANSMITTER
O
PERATION IN NON-FIFO MODE .............................................................................................................. 15
2.8.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16
ODE ................................................................................... 16
FIGURE 10. TRANSMITTER
OPERATION IN FIFO AND FLOW CONTROL M
2.9 RECEIVER......................................................................................................................................................... 16
2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 16
F
F
IGURE 11. RECEIVER
IGURE 12. RECEIVER
O
O
PERATION IN NON-FIFO MODE.................................................................................................................. 17
UTO RTS FLOW ODE ....................................................................... 17
PERATION IN FIFO AND
A
CONTROL M
2.10 AUTO RTS (HARDWARE) FLOW CONTROL................................................................................................ 18
2.11 AUTO RTS HYSTERESIS ............................................................................................................................... 18
TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 18
2.12 AUTO CTS FLOW CONTROL......................................................................................................................... 18
FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20
TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 20
2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 20
2.15 NORMAL MULTIDROP MODE........................................................................................................................ 20
2.15.1 AUTO ADDRESS DETECTION .................................................................................................................................. 21
2.16 INFRARED MODE ........................................................................................................................................... 21
FIGURE 14. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 22
2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWER-SAVE FEATURE...................................................... 22
2.17.1 SLEEP MODE ............................................................................................................................................................. 22
2.17.2 POWER-SAVE FEATURE .......................................................................................................................................... 23
2.17.3 WAKE-UP INTERRUPT .............................................................................................................................................. 23
2.18 INTERNAL LOOPBACK................................................................................................................................. 24
FIGURE 15. INTERNAL LOOPBACK................................................................................................................................................... 24
3.0 UART INTERNAL REGISTERS............................................................................................................. 25
TABLE 6: UART INTERNAL REGISTERS .................................................................................................................................. 25
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 26
4.0 INTERNAL REGISTER DESCRIPTIONS.............................................................................................. 27
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY.................................................................................. 27
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 27
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
I
XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
REV. 1.0.0
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 28
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 29
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 29
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 30
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 30
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 31
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION ............................................................................ 32
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 32
TABLE 10: PARITY SELECTION ........................................................................................................................................................ 33
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 34
TABLE 11: INT OUTPUT MODES ..................................................................................................................................................... 34
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 35
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 36
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 37
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 37
4.12 ENHANCED MODE SELECT REGISTER (EMSR) - WRITE-ONLY ............................................................... 38
TABLE 12: SCRATCHPAD
S
WAP
S
ELECTION .................................................................................................................................... 38
TABLE 13: AUTO RTS HYSTERESIS ................................................................................................................................................ 39
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 39
TABLE 14: SAMPLING
R
ATE
S
ELECT ............................................................................................................................................... 40
TABLE 15: BRG SELECT ................................................................................................................................................................ 40
4.14 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 40
4.15 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 40
4.16 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE............................................................................ 41
TABLE 16: TRIGGER TABLE SELECT ................................................................................................................................................ 41
4.17 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 41
TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 42
4.18 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE................... 43
TABLE 18: UART RESET CONDITIONS ...................................................................................................................................... 44
ABSOLUTE MAXIMUM RATINGS.................................................................................. 45
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 45
ELECTRICAL CHARACTERISTICS ............................................................................... 45
DC ELECTRICAL
AC ELECTRICAL
TA = -40O TO +85
C
C
HARACTERISTICS ............................................................................................................. 45
HARACTERISTICS ............................................................................................................. 46
C, VCC IS 1.62 TO 3.6V, 70 LOAD WHERE APPLICABLE ............................................. 46
O
T
PF
F
F
F
F
F
F
F
F
F
F
IGURE 16. CLOCK
IGURE 17. MODEM
IGURE 18. 16 MODE (INTEL) DATA
IGURE 19. 16 MODE (INTEL) DATA
IMING............................................................................................................................................................. 47
I
NPUT/OUTPUT TIMING .................................................................................................................................... 48
B
B
US
US
R
W
B
EAD
RITE
US
T
T
READ T
IMING ................................................................................................................... 48
IMING.................................................................................................................. 49
IMING .......................................................................................................... 49
IMING [NON-FIFO MODE]............................................................................................ 50
IMING......................................................................................................... 50
IMING [NON-FIFO MODE].......................................................................................... 51
IMING [FIFO MODE].................................................................................................... 51
IMING [FIFO MODE].................................................................................................. 52
IGURE 20. 68 MODE (MOTOROLA) DATA
IGURE 22. RECEIVE EADY & INTERRUPT
IGURE 21. 68 MODE (MOTOROLA) DATA
IGURE 23. TRANSMIT EADY & INTERRUPT
EADY & INTERRUPT
EADY & INTERRUPT
R
T
B
US WRITE T
T
T
T
R
R
R
IGURE 24. RECEIVE
IGURE 25. TRANSMIT
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm).............................................. 53
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)............................................... 54
PACKAGE DIMENSIONS (25 PIN BGA - 3 X 3 X 0.8 mm).............................................. 55
R
EVISION
H
ISTORY...................................................................................................................................... 56
II
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