XR16M890IL40 [EXAR]
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS; UART，具有128字节FIFO和集成电平转换器
| 型号： | XR16M890IL40 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS |
| 文件： | 总63页 (文件大小：1427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
APRIL 2011
REV. 1.0.0
FEATURES
GENERAL DESCRIPTION
• Integrated Level Shifters on CPU interface, UART
1
The XR16M890
(M890) is
a
single-channel
and GPIO signals
Universal Asynchronous Receiver and Transmitter
(UART) with integrated level shifters and 128 bytes of
transmit and receive FIFOs.
• Intel/Motorola/VLIO Bus Interface select
■ ’0’ ns address setup/hold times
• 24 Mbps maximum UART data rate
• Up to 16 GPIOs
For flexibility in a mixed voltage environment, the
M890 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and CPU interface signals allow for the M890 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters.
• 128-Bytes TX and RX FIFOs
• Programmable TX/RX trigger levels
• TX/RX FIFO Level Counters
• Independent TX/RX Baud Rate Generator
• Fractional Baud Rate Generator
• Auto RTS/CTS Hardware Flow Control
• Auto XON/XOFF Software Flow Control
• Auto RS-485 Half-Duplex Direction Control
• Multidrop mode w/ Auto Address Detect (RX)
• Multidrop mode w/ Address Byte Control (TX)
• Sleep Mode with Automatic Wake-up
• Infrared (IrDA 1.0 and 1.1) mode
• 1.62V to 3.63V supply operation
• 5V tolerant inputs
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address Byte Control features increase the
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M890 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M890 can be minimized by
enabling the sleep mode.
• Crystal oscillator or external clock input
APPLICATIONS
• Personal Digital Assistants (PDA)
• Cellular Phones/Data Devices
• Battery-Operated Devices
• Global Positioning System (GPS)
• Bluetooth
The M890 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M890 has a selectable
Intel/Motorola/VLIO bus interface.
NOTE: 1 Covered by U.S. Patent #5,649,122.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 1. XR16M890 BLOCK DIAGRAM
VCC_BUS
VCC_CORE
VCC_UART
A2:A0
D7:D0
(AD7:AD0)
128-Byte
TX FIFO
TX
RX
TX
UART
Regs
1.62V-
3.63V
I/O
128-Byte
RX FIFO
RX
CS#
LLA#
IOR#
Intel/
Motorola/
VLIO
Bus
Interface
1.62V-
3.63V
I/O
Buffers
RTS#
CTS#
Flow Control
IOW# (R/W#)
INT (IRQ#)
RESET
GPIO[3:0]
Buffers
(RESET#)
VCC_GPIO
Fractional
BRG
16/68#
VLIO_EN
EN485#
ENIR#
GPIOs
1.62V-
3.63V
I/O
GPIO[15:4]
Buffers
XTAL1
XTAL2
Crystal Oscillator/
Buffer
SLEEP/PWRDN#
ORDERING INFORMATION
NUMBER OF
GPIOS
OPERATING TEMPERATURE
RANGE
PART NUMBER
PACKAGE
DEVICE STATUS
XR16M890IL32-F
XR16M890IL32TR-F
XR16M890IL40-F
QFN-32
QFN-32
QFN-40
QFN-40
TQFP-48
TQFP-48
4
4
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Active
Active
Active
Active
Active
Active
8
XR16M890IL40TR-F
XR16M890IM48-F
XR16M890IM48TR-F
8
16
16
NOTE: TR = Tape and Reel, F = Green / RoHS
2
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 2. PIN OUT ASSIGNMENTS - 48-PIN TQFP
GND
VCC_BUS
16/68#
D0
1
2
3
4
5
6
7
8
9
36 DSR#/GPIO1
35 CD#/GPIO2
34 RI#/GPIO3
33 GND
D1
D2
D3
32 VCC_UART
31 GPIO15
30 GPIO14
29 GPIO13
28 GPIO4
XR16M890IM48
Intel (16) Mode
D4
D5
D6
D7
IOR# 10
IOW# 11
CS# 12
27 GPIO5
26 GPIO6
25 GPIO7
GND
GND
16/68#
D0
1
2
3
4
5
6
7
8
9
36 DSR#/GPIO1
35 CD#/GPIO2
34 RI#/GPIO3
33 GND
D1
D2
D3
32 VCC_UART
31 GPIO15
30 GPIO14
29 GPIO13
28 GPIO4
XR16M890IM48
Motorola (68) Mode
D4
D5
D6
D7
VCC_BUS
IOR# 10
R/W# 11
CS# 12
27 GPIO5
26 GPIO6
25 GPIO7
VCC_BUS
GND
16/68#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1
2
3
4
5
6
7
8
9
36 DSR#/GPIO1
35 CD#/GPIO2
34 RI#/GPIO3
33 GND
32 VCC_UART
31 GPIO15
30 GPIO14
29 GPIO13
28 GPIO4
XR16M890IM48
VLIO Mode
IOR# 10
IOW# 11
CS# 12
27 GPIO5
26 GPIO6
25 GPIO7
3
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 3. PIN OUT ASSIGNMENTS - 40-PIN QFN AND 32-PIN QFN
REV. 1.0.0
GND
GND
VCC_BUS
VCC_BUS
30 CTS#
16/68#
D0
1
2
3
4
5
6
7
8
9
29 DTR#/GPIO0
28 DSR#/GPIO1
27 CD#/GPIO2
26 RI#/GPIO3
25 GND
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DTR#/GPIO0
D1
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
VCC_UART
RTS#
D2
XR16M890IL40
Intel (16) Mode
XR16M890IL32
Intel (16) Mode
D3
D4
24 VCC_UART
23 GPIO4
D5
D6
RX
22 GPIO5
D7
TX
21 GPIO6
RESET 10
GND
GND
GND
GND
30 CTS#
16/68#
D0
1
2
3
4
5
6
7
8
9
29 DTR#/GPIO0
28 DSR#/GPIO1
27 CD#/GPIO2
26 RI#/GPIO3
25 GND
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
24
23
22
21
DTR#/GPIO0
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
VCC_UART
RTS#
D1
D2
XR16M890IL40
Motorola (68) Mode
D3
XR16M890IL32
D4
Motorola (68) Mode 20
24 VCC_UART
23 GPIO4
D5
19
18
17
D6
RX
22 GPIO5
D7
TX
21 GPIO6
RESET# 10
VCC_BUS
VCC_BUS
GND
30 CTS#
16/68#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1
29 DTR#/GPIO0
28 DSR#/GPIO1
27 CD#/GPIO2
26 RI#/GPIO3
25 GND
2
3
4
5
6
7
8
9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1
24
23
22
21
20
19
18
17
DTR#/GPIO0
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
VCC_UART
RTS#
2
3
4
5
6
7
8
XR16M890IL40
VLIO Mode
XR16M890IL32
VLIO Mode
24 VCC_UART
23 GPIO4
RX
22 GPIO5
TX
21 GPIO6
RESET 10
4
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PIN DESCRIPTIONS
Pin Description
QFN-32 QFN-40 TQFP-48
NAME
TYPE
DESCRIPTION
PIN#
PIN#
PIN#
DATA BUS INTERFACE - Intel/Motorola
16/68#
32
1
1
I
Intel or Motorola Bus Select. This pin selects the 16 or 68 mode
when VLIO_EN is a logic 0. In the VLIO mode (VLIO_EN is a logic
1), this pin becomes the SLEEP/PWRDN# pin in the QFN-32 pack-
age.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will oper-
ate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface. This pin does not have
an internal pull-up or pull-down resistor.
A2
A1
A0
29
30
31
38
39
40
46
47
48
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART channel during a data bus transaction.
In the VLIO bus mode (details on next page):
■ A2 becomes ENIR#
■ A1 becomes ENRS485# in the QFN-32 package
■ A1 is an unused input on the TQFP-48 and QFN-40
packages and should be connected to GND
■ A0 becomes LLA#
D7
D6
D5
D4
D3
D2
D1
D0
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
In the VLIO bus mode, D7:D0 becomes AD7:AD0.
IOR#
13
16
10
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
IOW#
14
15
17
18
11
12
I
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
(R/W#)
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CS#
This input is chip select (active low) to enable the device.
5
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
REV. 1.0.0
QFN-32 QFN-40 TQFP-48
NAME
TYPE
DESCRIPTION
PIN#
PIN#
PIN#
INT
10
12
15
O
When 16/68# pin is at logic 1 for Intel bus interface, this output
(IRQ#)
(OD) become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
RESET
9
10
13
I
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes RESET (active high). When 16/68# pin is at logic 0 for
Motorola bus interface, this input becomes RESET# (active low).
(RESET#)
A 40 ns minimum active pulse on this pin will reset the internal reg-
isters and all outputs of the UART. The UART transmitter output will
be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see UART Reset Conditions).
DATA BUS INTERFACE - VLIO
VLIO_EN
28
37
45
I
VLIO Bus Enable. When VLIO_EN pin is at logic 0, the bus interface
is selected by the 16/68# pin. When VLIO_EN pin is at logic 1, the
VLIO bus interface is enabled and the 16/68# pin has no effect.
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
I/O
Multiplexed Address/Data lines [7:0]. The register address is
latched on the rising edge of the LLA#. After the LLA# signal goes
high, the UART enters the data phase where the data is placed on
these lines.
IOR#
13
16
10
I
Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
IOW#
CS#
14
15
31
17
18
40
11
12
48
I
I
I
Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
LLA#
Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
In the Intel/Motorola mode, this pin becomes A0.
6
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
QFN-32 QFN-40 TQFP-48
NAME
TYPE
DESCRIPTION
PIN#
PIN#
PIN#
INT
10
12
15
O
Interrupt output (active high). The output state is defined by the user
through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
MODEM I/O and GPIOs
TX
17
32
40
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX
18
19
33
31
41
39
I
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
RTS#
O
UART Request-to-Send (active low) or general purpose output. This
output must be asserted prior to using Auto RTS HW flow control,
see EFR[6], MCR[1] and IER[6]. This output can also be used for
the Auto RS-485 half-duplex output control.
CTS#
16
30
38
I
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
DTR#/GPIO0
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
24
23
22
21
29
28
27
26
37
36
35
34
I/O
I/O
I/O
I/O
General purpose I/O or UART Data-Terminal-Ready (active low).
General purpose I/O or UART Data-Set-Ready (active low).
General purpose I/O or UART Carrier-Detect (active low).
General purpose I/O or UART Ring-Indicator (active low).
General purpose I/Os.
GPIO4
GPIO5
GPIO6
GPIO7
-
-
-
-
23
22
21
20
28
27
26
25
I/O
I/O
I/O
These GPIOs are only available on the QFN-40 and TQFP-48 pack-
I/O ages.
GPIO8
GPIO9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19
20
21
22
23
29
30
31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose I/Os.
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
These GPIOs are only available on the TQFP-48 package.
ANCILLARY SIGNALS
XTAL1
XTAL2
26
27
35
36
43
44
I
Crystal or external clock input. Note: This input is not 5V tolerant.
Crystal or buffered clock output.
O
7
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
REV. 1.0.0
QFN-32 QFN-40 TQFP-48
NAME
TYPE
DESCRIPTION
PIN#
PIN#
PIN#
EN485#
30
13
16
I
Enable Auto RS-485 Half-Duplex Mode. This pin is sampled upon
power-up. If this pin is HIGH, then the RTS# output can be used for
Auto RTS Hardware Flow Control or as a general purpose output. If
this pin is LOW, then the RTS# output is the Auto RS-485 Half-
Duplex direction control pin.
In the QFN-32 package, this pin is the A1 pin when in the Intel/
Motorola mode.
ENIR#
29
32
38
11
46
14
I
Enable IR Mode. This pin is sampled upon power-up. If this pin is
HIGH, then the TX output and RX input will behave as the UART
transmit data output and UART receive data input. If this pin is
LOW, then the TX output and RX input will behave as the infrared
encoder data output and the infrared receive data input.
In the Intel/Motorola mode, this pin is the A2 pin for all packages.
SLEEP/
PWRDN#
I/O
Sleep / Power Down pin. This pin powers up as the SLEEP input.
The SLEEP input can force the UART to enter into the sleep mode
after the next byte transmitted or received without meeting any of
the sleep mode conditions. See ”Section 1.20.2, Sleep Mode -
SLEEP pin” on page 25.
(16/68#)
This pin can also be configured as an output pin which can be used
to indicate to the CPU that the UART has entered the sleep mode.
This output can also be used to power down other devices.
In the QFN-32 package, this pin is the 16/68# input pin when the
VLIO mode is disabled.
VCC_CORE
VCC_BUS
25
12
34
15
42
18
Pwr
Pwr
1.62V to 3.63V VCC for the core. This supply voltage is used for the
core logic including the crystal oscillator circuit.
1.62V to 3.63V VCC for bus interface signals.
This supply voltage pin will determine the I/O levels of the CPU bus
interface signals.
VCC_UART
VCC_GPIO
20
-
24
19
32
24
Pwr
Pwr
1.62V to 3.63V VCC for the UART signals.
This supply voltage pin will determine the I/O levels of the UART I/O
signals including GPIO[3:0].
1.62V to 3.63V VCC for the GPIO signals.
This supply voltage pin will determine the I/O levels of the
GPIO[15:4] signals.
GND
GND
11
14, 25
17, 33
Pwr
Pwr
Power supply common, ground.
Center
Pad
Center
Pad
Center
Pad
The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
8
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.0 FUNCTIONAL DESCRIPTIONS
1.1
CPU Interface
There are 3 CPU interfaces that can be selected on the XR16M890. They are the Intel, Motorola and VLIO
bus interfaces. Note: no clock (crystal or external clock) is required for data bus transactions. Each bus cycle
is asynchronous.
1.1.1
Intel bus interface (16 mode)
The Intel bus interface consists of 8 data bits, 3 address lines and 3 control signals (CS#, IOR# and IOW#) for
data bus read/write transactions. In this mode, the interrupt output (INT) is active high. A typical data bus
interconnection is shown in Figure 4.
FIGURE 4. XR16M890 TYPICAL INTEL DATA BUS INTERCONNECTION
VCC_BUS
16/68#
VCC_BUS
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TX
RX
Serial Transceivers of
RS-232
RS-485
RS-422
DTR#
A0
A1
A0
A1
A2
RTS#
CTS#
DSR#
CD#
O r Infrared
A2
IOR#
UART_IOR #
UART_IOW #
IO W #
CS#
UART_CS#
UART_INT
RI#
INT
VLIO_EN
G ND
SLEEP/PW RDN
SLEEP /PW RDN
UART_RESET
RESET
1.1.2
Motorola bus interface (68 mode)
The Motorola bus interface is similar to the Intel bus interface. This interface consists of 8 data bits, 3 address
lines, but only 2 control signals (CS# and R/W#) for data bus read/write transactions. In this mode, the
interrupt output (IRQ#) is an open-drain and active low. A typical data bus interconnection is shown in
Figure 5.
FIGURE 5. XR16M890 TYPICAL MOTOROLA DATA BUS INTERCONNECTIONS
VC C _B U S
V C C _B U S
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
TX
R X
D TR #
S erial Transceivers of
R S-232
R TS#
C TS#
D S R #
C D #
A 0
A 1
A 2
A 0
A 1
A 2
R S-485
R S-422
O r Infrared
IO R #
IO W #
C S#
VC C
R /W #
R I#
U A R T_C S #
vcc
16/68#
U A R T_IR Q #
IR Q #
VLIO _EN
G N D
S LEE P /PW R D N
SLE EP /PW R D N
U AR T_R ES ET #
R ES ET #
9
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.1.3
VLIO bus interface
The VLIO bus interface is similar to the Intel bus interface. The only difference is that the address and data
lines are shared. A typical data bus interconnection is shown below in Figure 6.
FIGURE 6. XR16M890 TYPICAL VLIO DATA BUS INTERCONNECTIONS
VCC_BUS
VLIO_EN
VCC_BUS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
TX
RX
Serial Transceivers of
RS-232
RS-485
DTR#
RS-422
Or Infrared
RTS#
CTS#
DSR#
CD#
LLA#
LLA#
IOR#
UART_IOR#
UART_IOW#
IOW#
CS#
UART_CS#
UART_INT
RI#
INT
SLEEP/PWRDN
SLEEP/PWRDN
UART_RESET#
GND
RESET#
10
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.2
Serial Interface
The M890 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical
connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422
transceivers, go to www.exar.com or send an e-mail to uarttechsupport@exar.com.
FIGURE 7. XR16M890 TYPICAL SERIAL INTERFACE CONNECTIONS
V C C _U A R T
V C C _U A R T
R S -232
T ransceiver
T X
R X
T1 IN
R 1 O U T
D T R #
R T S #
T 2IN
T 3IN
U A R T
R 2 O U T
C T S #
D S R #
C D #
R 3O U T
R 4O U T
R I#
R 5O U T
G N D
G N D
R S -232 F u ll-M o d em S erial In terface
VCC_UART
VCC_UART
RS-485
Transceiver
Full-duplex
TX+
TX-
TX
RX
DI
RO
VCC_UART
NC
NC
RTS#
DTR#
VCC_UART
RX+
RX-
UART
DE
CTS#
DSR#
RE#
CD
#
RI#
GND
RS-485 Full-Duplex Serial Interface
11
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 8. XR16M890 TYPICAL SERIAL INTERFACE CONNECTIONS
VCC_UART
VCC_UART
RS-485
Y
Z
Transceiver
Half-duplex
TX
RX
DI
RO
RTS#
DTR#
DE
VCC_UART
A
RE#
NC
UART
CTS#
DSR#
B
CD
#
RI#
GND
RS-485 Half-Duplex Serial Interface
VCC_UART
VCC_UART
IR
Transceiver
TX
TXD
RXD
RX
NC
NC
DTR#
RTS#
UART
VCC_UART
CTS#
DSR#
CD#
RI#
GND
Infrared Connection
12
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.3
Device Reset
The RESET (RESET#) input resets the internal registers and the serial interface outputs to their default state
(see Table 19). An active high (RESET) or active low (RESET#) pulse of longer than 40 ns duration will be
required to activate the reset function in the device. Following a power-on reset or an external reset, the M890
is software compatible with previous generation of UARTs.
1.4
The M890 can accept and withstand 5V signals on the inputs without any damage. But note that if the supply
voltage for the M890 is at the lower end of the supply voltage range (ie. 1.8V), its V may not be high enough
5-Volt Tolerant Inputs
OH
to meet the requirements of the V of a CPU or a serial transceiver that is operating at 5V. Caution: XTAL1 is
IH
not 5 volt tolerant.
1.5
Internal Registers
The M890 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M890 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR, FC and TRIG, SFR, SHR, GPIOINT, GPIO3T, GPIOINV, GPIOSEL)
that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff software flow control, 9-bit
(Multidrop) mode, auto RS-485 half duplex control, different baud rate for TX and RX and fractional baud rate
generator. All the register functions are discussed in full detail later in “Section 2.0, UART Internal Registers”
on page 27.
1.6
INT Ouput
The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2
summarize the operating behavior for the transmitter and receiver. Also see Figure 26 through 29.
TABLE 1: INTERRUPT PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO
FCR BIT-0 = 1 (FIFO ENABLED)
DISABLED)
INT Pin
LOW = One byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
(Intel or VLIO Mode)
HIGH = FIFO below trigger level or FIFO empty
IRQ# Pin
HIGH = One byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
(Motorola Mode)
LOW = FIFO below trigger level or FIFO empty
TABLE 2: INTERRUPT PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0 (FIFO
FCR BIT-0 = 1 (FIFO ENABLED)
DISABLED)
INT Pin
HIGH = One byte in RHR
LOW = RHR empty
LOW = FIFO below trigger level
(Intel or VLIO Mode)
HIGH = FIFO above trigger level or RX Data Timeout
IRQ# Pin
HIGH = One byte in THR
LOW = RHR empty
HIGH = FIFO above trigger level
(Motorola Mode)
LOW = FIFO above trigger level or RX Data Timeout
13
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.7
Crystal Oscillator or External Clock Input
The M890 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a
crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock
for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRGs) in the
UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For
programming details, see “Section 1.8, Programmable Baud Rate Generator with Fractional Divisor” on
page 15.
FIGURE 9. TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2
R1
0-120
(Optional)
R2
500K - 1M
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47pF
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in Figure 9. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
generator for standard or custom rates. For further reading on oscillator circuit, see application note DAN108
on EXAR’s web site.
14
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.8
Programmable Baud Rate Generator with Fractional Divisor
The M890 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescalers are controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescalers
to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
16
further divides this clock by a programmable divisor between 1 and (2 - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling.
The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD
= 0x00) during power-on reset. The DLL and DLM registers provide the integer part of the divisor and the DLD
register provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value from
0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). The divisor values can be calculated with the following
equations:
Divisor = (XTAL1 clock frequency / prescaler) / (serial data rate * 16), with 16X mode, DLD[5:4] = ’00’
Divisor = (XTAL1 clock frequency / prescaler / (serial data rate * 8), with 8X mode, DLD[5:4] = ’01’
Divisor = (XTAL1 clock frequency / prescaler / (serial data rate * 4), with 4X mode, DLD[5:4] = ’10’
The BRG divisors can be calculated using the following formulas:
Integer Divisor = TRUNC (Divisor)
Fractional Divisor = Divisor - Integer Divisor
DLM = Integer Divisor / 256
DLL = Integer Divisor & 256
DLD = TRUNC(Fractional Divisor * 16)
In the formulas above, please note that TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
1.8.1
Fractional BRG Example
For example, if the crystal clock is 24MHz, prescaler is 1, and the sampling mode is 16X, the divisor for a baud
rate of 38400bps would be:
Divisor = (24000000 / 1) / (38400 * 16) = 39.0625
Integer Divisor = TRUNC (39.0625) = 39
Fractional Divisor = 39.0625 - 39 = 0.0625
DLM = 39 / 256 = 0 = 0x00
DLL = 39 & 256 = 39 = 0x27
DLD = 0.0625 * 16 = 1 = 0x1
Table 3 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 3. At 8X
sampling rate, these data rates would double. And at 4X sampling rate, they would quadruple. Also, when
using 8X sampling mode, please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero
and is an odd number.
1.8.2
Independent TX/RX BRG
The XR16M890 has two independent sets of TX and RX baud rate generator. See Figure 10. TX and RX can
use different baud rates by setting DLD, DLL and DLM register. For example, TX can transmit data to the
remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting,
See ”Section 3.15, Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write” on page 45.
15
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 10. BAUD RATE GENERATOR
DLD[7]=0
DLL
16X or 8X or 4X
Sampling Rate Clock
to Transmitter
Prescaler
DLM
-
MCR Bit 7=0
Divide by 1
DLD[5:0]
(default)
Crystal
Osc/
Buffer
XTAL1
XTAL2
0
1
16X or 8X or 4X
Sampling Rate Clock
to Receiver
MCR Bit-7=1
DLL
DLM
Prescaler
Divide by 4
DLD[5:0]
DLD[7]=1
DLD[6]
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required Output
Data Rate
DIVISOR FOR 16x
Clock (Decimal)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DLD PROGRAM
VALUE (HEX)
DATA ERROR
RATE (%)
400
2400
3750
625
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6
71
38
9C
96
4E
3C
34
27
1E
1A
14
F
0
0
8
4
0
2
0
1
1
0
0
0
0
0
C
8
A
8
0
0
C
4
0
0
A
8
0
0
4800
312.5
156.25
150
0
9600
0
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
0
78.125
60
0
0
52.0833
39.0625
30
0.04
0
0
26.0417
20
0.08
0
15
0
13.0208
9.7656
7.5
D
0.16
0.16
0
9
7
6.6667
6.5104
6
6
0.31
0.16
0
6
6
5
5
0
3.75
3
0
3.2552
3
3
0.16
0
3
2
2
0
1.6276
1.5
1
0.16
0
1
16
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.9
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16/8/4 clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
1.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
1.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 11. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X or 8X or 4X
Clock
( DLD[5:4] )
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
17
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 12. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
FIFO
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
16X or 8X or 4X Clock
(DLD[5:4])
Transmit Data Shift Register
(TSR)
TXFIFO1
1.10 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0. See Figure 13 and Figure 14 below.
1.10.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
18
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 13. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift
Data Bit
Register (RSR)
Validation
Receive Data Characters
Error
Tags in
LSR bits
4:2
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 14. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example
- RX FIFO trigger level selected at 16 bytes
:
(See Note Below)
128 bytes by 11-bit wide
FIFO
Data falls to
8
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data FIFO
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
56
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data
Receive Data
Byte and Errors
RXFIFO1
19
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.11 Auto RTS (Hardware) Flow Control
REV. 1.0.0
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 15):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
1.12 Auto RTS Hysteresis
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the selected RX
trigger level. The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches one trigger level
above the selected trigger level in the trigger table (Table 10). The RTS# pin will return LOW after the RX FIFO
is unloaded to one level below the selected trigger level. Under the above described conditions, the M890 will
continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS#
output pin is asserted LOW (RTS On). Table 4 below explains this when the Trigger Table-C (Table 10) is
selected.
TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
RX TRIGGER LEVEL
INT PIN ACTIVATION
8
8
16
56
60
60
0
8
16
56
60
16
56
60
16
56
20
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.13 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 15):
• Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend
transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after
the CTS# input is re-asserted (LOW), indicating more data may be sent.
FIGURE 15. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
TXB
Receiver FIFO
Trigger Reached
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto RTS
Auto CTS
Monitor
Trigger Level
Receiver FIFO
Trigger Reached
Transmitter
CTSA#
RTSB#
Auto CTS
Monitor
Auto RTS
Trigger Level
Assert RTS# to Begin
Transmission
1
10
ON
ON
ON
RTSA#
OFF
OFF
7
2
ON
3
11
CTSB#
TXB
8
Restart
9
Data Starts
6
Suspend
4
RXA FIFO
Receive
Data
RX FIFO
12
RTS High
Threshold
RTS Low
Threshold
5
RX FIFO
Trigger Level
Trigger Level
INTA
(RXA FIFO
Interrupt)
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
21
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.14 Auto Xon/Xoff (Software) Flow Control
REV. 1.0.0
When software flow control is enabled (See Table 18), the M890 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the M890 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the M890 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the M890 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 18) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the M890 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed in the RX FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the M890 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The M890 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level. To clear this condition, the M890 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed
trigger level. Table 5 below explains this when the Trigger Table-C (Table 10) is selected.
TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
RX TRIGGER LEVEL
INT PIN ACTIVATION
8
8
8*
0
8
16
56
60
16
56
60
16*
56*
60*
16
56
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
1.15
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The M890 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the
Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
1.16 Auto RS485 Half-Duplex Control Operation
The auto RS485 half-duplex direction control feature can be enabled by FCTR bit [3]. The RTS# pin becomes
the half-duplex control output when this feature has been enabled. The RTS# pin is typically connected to both
the Driver Enable (DE) and Receiver Enable (RE) of an RS-485 transceiver. When the Transmitter is idle, the
RTS# pin is de-asserted so that the RS-485 driver is disabled and the RS-485 receiver is enabled. When data
is loaded into the TX FIFO, the RTS# pin is asserted to enable the RS-485 driver and disable the RS-485
receiver. This changes the transmitter empty interrupt to TSR empty instead of THR empty.
22
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.16.1 RS-485 Setup Time
By default, the RTS# pin is asserted immediately before there is data on the TX output pin. For faster baud
rates, it may be possible that data is lost due to a long start-up time for an RS-485 transceiver. The M890 can
delay the data from 0-15 bit times to allow the RS-485 transceiver to start up (See ”Section , SHR[7:4]: RS-
485 Setup Delay” on page 40.).
1.16.2 RS-485 Turn-Around Delay
At the end of sending data, the RTS# pin is de-asserted immediately after the TX pin goes idle. The RTS# pin
can be programmed to delay the RTS# from being asserted from 0-15 bit times (See ”Section , SHR[3:0]: RS-
485 Turn-Around Delay / Auto RTS Hysteresis” on page 40.). The delay optimizes the time needed for the
last transmission to reach the farthest station on a long cable network before switching off the line driver.
1.17 Normal Multidrop (9-bit) Mode - Receiver
Normal multidrop mode is enabled when SFR[6] = 1 (requires EFR[4] = 1) and EFR[5] = 0 (Special Character
Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
1.17.1 Auto Address Detection - Receiver
Auto address detection mode is enabled when SFR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
1.18 Multidrop (9-bit) Mode - Transmitter
This feature simplifies sending an address byte (9th bit = 1) and improves the efficiency of the transmit data
routine for transmitting 9-bit data. In previous generation UARTs, the only way to send an address byte is by
changing the parity to Forced 1 parity, load the address byte in the THR, wait for the byte to be transmitted,
change the parity back to Forced 0 parity, then load data into the TX FIFO. In the XR16M890, there’s no
waiting required and no changing parity. The transmit routine can set SFR[7]=1, then write the address byte
into the TX FIFO followed immediately by the data bytes. SFR[7] is self-clearing, therefore, if multiple address
bytes need to be transmitted, then SFR[7] will need to be set prior to each address byte written into the TX
FIFO. During initialization, the parity must be set to Force Parity 0 (LCR[5:3] = ’111’).
23
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.19 Infrared Mode
The M890 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1
standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit
data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 16 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the
infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to
be compatible to the IrDA 1.1 standard, SFR bit-3 will also need to be set to a ’1’ when EFR bit-4 is set to ’1’.
Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 16.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 16. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
1
1
1
1
1
0
0
0
0
0
TX Data
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 or 1/4 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
1
1
1
1
0
0
0
0
0
RX Data
Data Bits
Character
IRdecoder-1
24
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.20 Sleep Mode with Auto Wake-Up
The M890 supports low voltage system designs, hence, a sleep mode with auto wake-up feature is included to
reduce its power consumption when the chip is not actively used.
1.20.1 Sleep mode - IER bit-4
All of these conditions must be satisfied for the M890 to enter sleep mode:
■ no interrupts pending (ISR bit-0 = 1)
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pin is idling HIGH in normal mode or LOW in infrared mode
■ divisor is non-zero
■ TX and RX FIFOs are empty
The M890 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The M890 resumes normal operation by any of the following:
■ a receive data start bit transition (HIGH to LOW)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the M890 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the M890 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from any channel. The M890 will stay in the sleep mode of operation until it is disabled
by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX pin is idling HIGH or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on each of the RX input.
1.20.2 Sleep Mode - SLEEP pin
The M890 has a new pin called the SLEEP pin that can be used instead of setting IER bit-4=1. The M890 will
enter the sleep mode when:
■ the current byte in the TSR has completely shifted out
■ the current byte in the RSR has been completely received
Under this condition, there could be data in the TX and RX FIFOs. Any data that is the TX and RX FIFOs when
the SLEEP pin is asserted will not be affected. The only data that will be lost is any data that is still being
received on the RX pin. The M890 will only wake up after the SLEEP pin has been de-asserted.
1.20.3 Wake-up Interrupt
The M890 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The
default status of wake up interrupt is disabled. Please See ”Section 3.5, FIFO Control Register (FCR) -
Write-Only” on page 34.
25
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.21
Internal Loopback
The M890 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 17 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 17. INTERNAL LOOPBACK
VCC
TX
Transm it Shift Register
(THR/FIFO )
M CR bit-4=1
Receive Shift Register
(RHR/FIFO)
RX
VCC
RTS#
RTS#
CTS#
CTS#
VCC
DTR#
DTR#
DSR#
DSR#
O P1#
RI#
RI#
O P2#
CD#
CD#
26
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
2.0 UART INTERNAL REGISTERS
The complete register set for the M890 is shown in Table 6 and Table 7.
TABLE 6: UART INTERNAL REGISTERS
A2 A1 A0
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0
0
0
0
0
0 0
0 1
0 0
0 1
1 0
0 0
DREV - Device Revision
Read-only
Read-only
Read/Write
Read/Write
Read/Write
LCR[7] = 1, LCR ≠ 0xBF,
DLL = 0x00, DLM = 0x00
DVID - Device Identification Register
DLL - Divisor LSB Register
LCR[7] = 1, LCR ≠ 0xBF
See DLD[7:6]
DLM - Divisor MSB Register
DLD - Divisor Fractional Register
LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0
0 1
1 0
IER - Interrupt Enable Register
Read/Write
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7] = 0 if EFR[4] = 1
or
LCR ≠ 0xBF if EFR[4] = 0
0
1
1
1
1
1
1 1
0 0
0 1
0 1
1 0
1 0
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
Read/Write
Read/Write
Read-only
Write-only
Read-only
Write-only
LCR ≠ 0xBF
SHR - Setup/Hysteresis Register
MSR - Modem Status Register
SFR - Special Function Register
LCR ≠ 0xBF
EFR[4] = 1
1
1 1
SPR - Scratch Pad Register
Read/Write
LCR ≠ 0xBF, FCTR[6] = 0,
SFR[0] = 0
1
1
1 1
1 1
EMSR - Enhanced Mode Select Register
FC - RX/TX FIFO Level Counter Register
Write-only
Read-only
LCR ≠ 0xBF, FCTR[6] = 1,
SFR[0] = 0
ENHANCED REGISTERS
0
0
0
0
1
1
1
1
1
1
1
1
0 0
0 0
0 1
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
FC - RX/TX FIFO Level Counter Register
TRIG - RX/TX FIFO Trigger Level Register
FCTR - Feature Control Register
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Read-only
Write-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
LCR = 0xBF
Xon-2 - Xon Character 2
LCR = 0xBF
SFR[0]=0
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
GPIOINT - GPIO Interrupt Enable Register
GPIO3T - GPIO Three-State Control Register
GPIOINV - GPIO Polarity Control Register
GPIOSEL - GPIO Select Register
LCR = 0xBF
SFR[0]=1
27
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
IER
RD
WR
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
RD/WR
Modem RXLine
Stat. Int.
Enable
TX
Empty
Int
RX Data
Int.
Enable
LCR[7] = 0
Stat.
Int.
Enable Enable
CTS#
Int.
Enable Enable
FIFOs FIFOs
Enabled Enabled
RTS#
Int.
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0
ISR
RD
0/
0/
INT
INT INT
INT
Source Source Source Source
Bit-3
LCR[7] = 0
if EFR[4]=1
RTS
CTS
Interrupt
Xoff
Bit-2
Bit-1
Bit-0
Interrupt
or
LCR≠0xBF
if EFR[4]=0
0 1 0
0 1 1
FCR
LCR
WR RXFIFO RXFIFO TXFIFO TXFIFO Wake up
Trigger Trigger Trigger
TX
RX
FIFO
FIFOs
Enable
Trigger Int Enable FIFO
Reset Reset
RD/WR Divisor Set TX
Set
Even
Parity
Stop
Bits
Word
Length Length
Word
Enable
Break
Parity
Enable
Parity
Bit-1
Bit-0
1 0 0
MCR
RD/WR
0/
0/
0/
Internal INT Out- OP1#/ RTS#
DTR#
Lopback
Enable
put
Enable
Output Output
Control Control
BRG
Pres-
caler
IR Mode XonAny
ENable
GPIO
Select
(OP2#)
1 0 1
1 0 1
LSR
SHR
RD
RX FIFO THR &
THR
Empty
RX Break RX Fram-
RX
RX
RX Data
Ready
Global
Error
TSR
Empty
ing Error Parity Over-
Error
run
Error
WR
RS-485 RS-485 RS-485 RS-485
RS-485 RS-485 RS-485 RS-485
Setup
Setup
Setup
Setup
Delay
Delay Delay
Delay
LCR≠0xBF
Bit-3
Bit-2
Bit-1
Bit-0
Bit-3/
Bit-2/ Bit-1/
Bit-0/
Hystere- Hyster- Hyster- Hystere-
sis
esis
esis
sis
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0
1 1 0
MSR
SFR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
WR
TX
Enable Disable Disable
9-bit
mode
Fast
IR
GPIO GPIO
INT
GPIO
RX
TX
9-bit
[15:8]/ Access
Enable [7:0]
Select
1 1 1
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR≠0xBF
FCTR[6]=0
SFR[0]=0
GPIOLVL RD/WR Bit-15/
Bit-7
Bit-14/
Bit-6
Bit-13/
Bit-5
Bit-12/
Bit-4
Bit-11/
Bit-3
Bit-10/ Bit-9/
Bit-2 Bit-1
Bit-8/ LCR≠0xBF
Bit-0
FCTR[6]=0
SFR[0]=1
28
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
1 1 1
EMSR
FC
WR
RD
Xoff
LSR
Rsvd
Modem
3-State
Control
Invert
RTS in
RS485
mode
Send
TX
FIFO
count
FIFO
count
interrupt interrupt
mode
select
LCR≠0xBF
FCTR[6]=1
SFR[0]=0
mode
select
imme- control control
diate
bit-1
bit-0
1 1 1
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
0 0 1
DREV
DVID
RD
RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
1
Bit-3
0
Bit-2
0
Bit-1
0
Bit-0
1
LCR[7] = 1
LCR≠0xBF
DLL= 0x00
DLM= 0x00
0 0 0
0 0 1
DLL
RD/WR
RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
LCR≠0xBF
DLD[7:6]
DLM
0 1 0
DLD
RD/WR BRG
Enable 4X Mode 8X Mode
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 1
LCR≠0xBF
EFR[4] = 1
select Indepen-
dent
BRG
Enhanced Registers
0 0 0
0 0 0
0 0 1
FC
RD
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
TRIG
WR
FCTR RD/WR RX/TX
select
Swap
SPR
Trigger
Table
bit-1
Trigger
Table
bit-0
Auto
RS485
Half-
invert
RX IR
Rsvd PWRDN
#
control
Duplex
0 1 0
EFR
RD/WR
Auto
CTS#
Enable Enable
Auto
RTS#
Special
Char
Select
Enable
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
Soft-
ware
Flow
Cntl
LCR=0XBF
IER [7:4],
ISR [5:4],
FCR[5:3],
MCR[7:5],
DLD,
Bit-2
Bit-1
Bit-0
Bit-3
SHR,
SFR
1 0 0
1 0 1
1 1 0
1 1 1
XON1 RD/WR
XON2 RD/WR
XOFF1 RD/WR
XOFF2 RD/WR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
LCR=0XBF
SFR[0]=0
Bit-15/
Bit-7
Bit-14/
Bit-6
Bit-13/
Bit-5
Bit-12/
Bit-4
Bit-11/
Bit-3
Bit-10/ Bit-9/
Bit-2 Bit-1
Bit-10/ Bit-9/
Bit-2 Bit-1
Bit-10/ Bit-9/
Bit-2 Bit-1
Bit-10/ Bit-9/
Bit-2 Bit-1
Bit-8/
Bit-0
1 0 0
1 0 1
1 1 0
GPIOINT RD/WR
GPIO3T RD/WR
GPIOINV RD/WR
Bit-15/
Bit-7
Bit-14/
Bit-6
Bit-13/
Bit-5
Bit-12/
Bit-4
Bit-11/
Bit-3
Bit-8/
Bit-0
LCR=0XBF
SFR[0]=1
Bit-15/
Bit-7
Bit-14/
Bit-6
Bit-13/
Bit-5
Bit-12/
Bit-4
Bit-11/
Bit-3
Bit-8/
Bit-0
Bit-15/
Bit-7
Bit-14/
Bit-6
Bit-13/
Bit-5
Bit-12/
Bit-4
Bit-11/
Bit-3
Bit-8/
Bit-0
1 1 1 GPIOSEL RD/WR
29
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
3.0 INTERNAL REGISTER DESCRIPTIONS
REV. 1.0.0
3.1
SEE”RECEIVER” ON PAGE 18.
3.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 17.
3.3 Interrupt Enable Register (IER) - Read/Write
Receive Holding Register (RHR) - Read- Only
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
3.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
3.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M890 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
30
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error. However,
when EMSR bit-6 changes to 1 (default is 0), LSR bit 2-4 generate an interrupt when the character is received
in the RX FIFO. Please refer to “Section 3.14, Enhanced Mode Select Register (EMSR) - Write-only” on
page 44.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from LOW to HIGH (if enabled by EFR bit-6).
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH (if enabled by EFR bit-7).
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REV. 1.0.0
3.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
3.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
• Wakeup interrupt is generated when the M890 wakes up from the sleep mode.
• GPIO interrupt is generated when a GPIO input has been asserted (polarity selected by GPIOINV register)
3.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xon or Xoff interrupt is cleared by a read to the ISR register.
• Special character interrupt is cleared by a read to ISR register or after next character is received.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
• Wakeup interrupt is cleared by a read to ISR register.
• GPIO interrupt is cleared by a read to the GPIOLVL register
]
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
REV. 1.0.0
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
6
7
-
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RXRDY (Received Xon, Xoff or Special character)
CTS#, RTS# change of state
None (default) or Wakeup interrupt
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 8).
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[6]: GPIO Interrupt Status
This bit reports the GPIO interrupt status. When a GPIO interrupt has been generated, this bit will be the
inverse of ISR[7]. When the GPIO interrupt is not enabled, this bit will match ISR[7] for 16550 compatibility
(See Table 9).
ISR[7]: FIFO Enable Status
This bit is set to a logic 0 when the FIFOs are disabled. It is set to a logic 1 when the FIFOs are enabled (See
Table 9).
TABLE 9: FIFO ENABLE STATUS/GPIO INTERRUPT STATUS
GPIO INTERRUPT ENABLED
FCR[0]
FIFO MODE
GPIO INTERRUPT STATUS
ISR[7]
ISR[6]
(GPIOINT REGISTER)
0
0
0
1
1
1
FIFO Disabled
FIFO Disabled
FIFO Disabled
FIFO Enabled
FIFO Enabled
FIFO Enabled
No
Yes
Yes
No
No GPIO Interrupt
No GPIO Interrupt
GPIO Interrupt
0
0
0
1
1
1
0
0
1
1
1
0
No GPIO Interrupt
No GPIO Interrupt
GPIO Interrupt
Yes
Yes
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REV. 1.0.0
3.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
enable the wake up interrupt. They are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)
• Logic 0 = Disable the wake up interrupt (default).
• Logic 1 = Enable the wake up interrupt.
Please refer to “Section 1.20.3, Wake-up Interrupt” on page 25.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. Note that the
receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to
both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
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TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRANSMIT
TRIGGER FCTR FCTR
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT-4
RECEIVE
TRIGGER LEVEL
TRIGGER
LEVEL
COMPATIBILITY
TABLE
BIT-5
BIT-4
Table-A
0
0
0
0
1 (default)
16C550, 16x255x,
16x554, 16x57x,
16x58x
0
0
1
1
0
1
0
1
1 (default)
4
8
14
Table-B
Table-C
Table-D
0
1
1
1
0
1
0
0
1
1
0
1
0
1
16
8
16C650A, 16L651,
16x265x, 16x564
24
30
0
0
1
1
0
1
0
1
8
16
24
28
0
0
1
1
0
1
0
1
8
16x654
16
32
56
0
0
1
1
0
1
0
1
8
16
56
60
X
X
X
X
Programmable Programmable 16x275x, 16C285x,
16C850, 16C854,
16C864
via TRG
via TRG
register.
register.
FCTR[7] = 0.
FCTR[7] = 1.
3.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
LCR[2]: TX and RX Stop-bit Length Select
REV. 1.0.0
The length of stop bit is specified by this bit in conjunction with the programmed word length.
STOP BIT LENGTH
(BIT TIME(S))
WORD
LENGTH
BIT-2
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, HIGH
Forced parity to space, LOW
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LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition. (default)
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
3.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output HIGH (default).
• Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
• Logic 0 = Force RTS# output HIGH (default).
• Logic 1 = Force RTS# output LOW. It is required to start Auto RTS Flow Control.
MCR[2]: GPIO[3:0] or Modem IO Select
This bit controls whether GPIO[3:0] behave as GPIO pins or as modem IO pins (RI#, CD#, DTR#, DSR#)
• Logic 0 = GPIO[3:0] behave as GPIO pins
• Logic 1 = GPIO[3:0] behave as RI#, CD#, DTR#, DSR#
In the Loopback Mode, this bit is used as the OP1# to write the state of the modem RI# interface signal.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This bit is also used to control the OP2#
signal during internal loopback mode. This bit applies only to the Intel and VLIO bus modes. This bit has no
effect in the Motorola bus mode.
• Logic 0 = INT output disabled (three state). During internal loopback mode, OP2# is HIGH.
• Logic 1 = INT output enabled (active). During internal loopback mode, OP2# is LOW.
TABLE 12: INT OUTPUT MODES
MCR
INT OUTPUT
BIT-3
0
1
Three-State
Active
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
MCR[4]: Internal Loopback Enable
REV. 1.0.0
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 17.
MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the M890 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)
• Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be LOW during idle data conditions.
MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
3.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR
bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
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LSR[4]: Receive Break Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or HIGH.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
3.9
Setup/Hysteresis Register (SHR) - Write Only
In the Auto RS-485 half-duplex mode, the RTS# control output can be asserted from 0 to 15 bit times before
data is transmitted to allow for the startup time of an RS-485 transceiver that may be in shutdown mode. The
RTS# control output can also be delayed from 0 to 15 bit times after the last byte has been transmitted to allow
the data to propogate down long data cables.
In the Auto RTS flow control mode, this register selects the hysteresis levels that will be used with
programmable trigger levels (Trigger Table-D).
SHR[3:0]: RS-485 Turn-Around Delay / Auto RTS Hysteresis
When the Auto RS-485 half-duplex mode is enabled (FCTR[3] = 1), the value programmed in these bits will be
the number of bits (0-15) the RTS# pin will wait before it is de-asserted after the last byte that has been
transmitted.
When Auto RTS flow control is enabled (EFR[6] = 1) and programmable trigger levels are used (FCTR[5:4] =
’11’), these bits select the hysteresis levels for the RTS# flow control pin (See Table 13).
TABLE 13: AUTO RTS HYSTERESIS
RTS# HYSTERESIS
(CHARACTERS)
SHR BIT-3
SHR BIT-2
SHR BIT-1
SHR BIT-0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
±4
±6
±8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
±8
±16
±24
±32
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
±40
±44
±48
±52
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
±12
±20
±28
±36
SHR[7:4]: RS-485 Setup Delay
When the Auto RS-485 half-duplex mode is enabled (FCTR[3] = 1), the value programmed in these bits will be
the number of bits (0-15) the RTS# pin is asserted before the first byte is transmitted.
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3.10 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals. Reading the higher four bits shows the status of the modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
MSR[4]: CTS Input Status
REV. 1.0.0
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS Flow Control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
3.11 Special Function Register (SFR) - Write Only
This register provides access to some of the advanced features of XR16M890. This register can only be
written to if EFR[4] = 1.
SFR[0]: Enable GPIO Registers (Requires EFR[4] = 1)
• Logic 0 = GPIO control and status registers are not enabled.
• Logic 1 = GPIOLVL register is accessible at SPR register location. GPIOINT, GPIO3T, GPIOINV, GPIOSEL
registers are accessible at XON1, XON2, XOFF1, and XOFF2 register locations.
SFR[1]: GPIO[15:8] or GPIO[7:0] Select (Requires EFR[4] = 1)
• Logic 0 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[7:0].
• Logic 1 = GPIOLVL, GPIOINT, GPIO3T, GPIOINV and GPIOSEL registers will control and report the status
of GPIO[15:8].
SFR[2]: GPIO Interrupt Enable (Requires EFR[4] = 1)
• Logic 0 = GPIO interrupt is disabled.
• Logic 1 = GPIO interrupt is enabled. GPIOs that have been configured as inputs can generate GPIO
interrupts if the bit is enabled in the GPIOINT register. The polarity of the GPIO interrupt is selected via the
GPIOINV register.
SFR[3]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M890 supports the new fast IR transmission with data rate up to 1.152 Mbps.
• Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
• Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
See ”Section 1.19, Infrared Mode” on page 24.
SFR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
• Logic 0 = Enable Transmitter (default).
• Logic 1 = Disable Transmitter.
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
SFR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
• Logic 0 = Enable Receiver (default).
• Logic 1 = Disable Receiver.
SFR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
For the 9-bit mode information, See ”Section 1.17, Normal Multidrop (9-bit) Mode - Receiver” on page 23.
• Logic 0 = Normal 8-bit mode (default).
• Logic 1 = Enable 9-bit or Multidrop mode.
SFR[7]: TX Address Bit (Requires EFR[4] = 1)
This bit requires that forced "0" parity is enabled (LCR[5:3]=’111’). If this bit is enabled, the 9th bit of the next
byte written to THR will be a ’1’. This bit resets after a write to THR. For the 9-bit mode information, See
”Section 1.18, Multidrop (9-bit) Mode - Transmitter” on page 23.
• Logic 0 = Value of 9th bit will be ’0’ (default).
• Logic 1 = Value of 9th bit will be ’1’.
3.12 Scratch Pad Register (SPR) - Read/Write
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
3.13 GPIO Level Register (GPIOLVL) - Read/Write
This register provides the current state of the GPIO pins.
If a GPIO has been configured as an input:
■ A read will report the current state of the input.
■ A write to any GPIO configured as an input will not have any effect.
If a GPIO has been configured as an output:
■ A read will report the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
■ A write will change the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
3.14 Enhanced Mode Select Register (EMSR) - Write-only
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
REV. 1.0.0
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 14: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0]
Scratchpad is
0
1
1
1
X
X
0
1
X
0
1
1
Scratchpad
RX FIFO Level Counter Mode
TX FIFO Level Counter Mode
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[2]: Send TX Immediately
• Logic 0 = Do not send TX immediately (default).
• Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the
TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only
1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If
more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
EMSR[3]: Invert RTS in RS485 mode
• Logic 0 = RTS# output is a logic 0 during TX(default).
• Logic 1 = RTS# output is a logic 1 during TX.
EMSR[4]: Modem Outputs Three-State Control
• Logic 0 = TX, RTS#, and DTR# outputs are active (default).
• Logic 1 = TX, RTS#, and DTR# outputs are in three-state mode.
EMSR[5]: Reserved
This bit is reserved and should be ’0’.
EMSR[6]: LSR Interrupt Mode
• Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
• Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
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XR16M890
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
• Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
• Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
3.15 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M890 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M890 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 15 below and See ”Section 1.8, Programmable
Baud Rate Generator with Fractional Divisor” on page 15.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 15 below.
TABLE 15: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
0
0
1
0
1
X
16X
8X
4X
DLD[6]: Independent BRG enable
• Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator (default).
• Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0].
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
.
TABLE 16: BRG SELECT
DLD[7]
DLD[6]
BRG
0
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
0
1
1
1
1
0
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
3.16 Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
3.17 RX/TX FIFO Level Count Register (FC) - Read-Only
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See Table 14.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register.
3.18 Feature Control Register (FCTR) - Read/Write
FCTR[0]: SLEEP/PWRDN# Function Control
• Logic 0 = SLEEP pin (input) is enabled. This pin can be used to force the XR16M890 to enter the sleep
mode immediately after the next data byte that is being transmitted on the TX pin and being received on the
RX pin has been completed.
• Logic 1 = PWRDN# pin (output) is enabled. When the XR16M890 enters the sleep mode, this pin will be
LOW. When the XR16M890 is not in sleep mode, this pin will be HIGH.
FCTR[1]: Reserved
This bit is reserved and should be ’0’.
FCTR[2]: IrDa RX Inversion
• Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
• Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
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XR16M890
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FCTR[3]: Auto RS-485 Direction Control
• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
• Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 17 for more details.
TABLE 17: TRIGGER TABLE SELECT
FCTR
BIT-5
FCTR
BIT-4
TABLE
0
0
1
1
0
1
0
1
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
FCTR[6]: Scratchpad Swap
• Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
• Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
• Logic 0 = Registers TRG and FC selected for RX.
• Logic 1 = Registers TRG and FC selected for TX.
3.19 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
EFR[3:0]: Software Flow Control Select
REV. 1.0.0
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
1
0
1
X
X
X
1
0
0
0
1
1
X
X
X
0
0
X
X
X
X
0
1
0
1
0
X
X
X
X
0
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
0
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, DLD,
SHR and SFR to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-
7, DLD, SHR and SFR are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 3-5, and MCR bits 5-7, DLD, SHR and SFR are set to a logic 0 to be compatible with ST16C550 mode
(default).
• Logic 1 = Enables the EFR[3:0] register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
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XR16M890
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UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
3.20 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 5. The xoff2 is also used as auto address detect register when the auto 9-bit mode
enabled. See ”Section 1.17.1, Auto Address Detection - Receiver” on page 23.
3.21 GPIO Interrupt Enable Register (GPIOINT) - Read/Write
If a GPIO has been configured as an input, this register selects which inputs can generate a GPIO interrupt.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
• Logic 0 = GPIO interrupt for this input pin is not enabled.
• Logic 1 = GPIO interrupt for this input pin is enabled.
3.22 GPIO Three-State Control Register (GPIO3T) - Read/Write
If a GPIO has been configured as an output, this register selects which outputs will be in three-state mode.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
• Logic 0 = GPIO output is in active mode and can be controlled via GPIOLVL register.
• Logic 1 = GPIO output is in three-state mode.
3.23 GPIO Polarity Control Register (GPIOINV) - Read/Write
If a GPIO has been configured as an interrupt, this register selects the polarity that can generate a GPIO
interrupt. This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
• Logic 0 = GPIO interrupt is generated when this input pin transitions from LOW to HIGH. Read GPIOLVL
returns GPIO pin state.
• Logic 1 = GPIO interrupt is generated when this input pin transitions from HIGH to LOW. Read GPIOLVL
returns inverted GPIO pin state.
3.24 GPIO Select Register (GPIOSEL) - Read/Write
This register selects where a GPIO is an input or an output.
• Logic 0 = GPIO is an output.
• Logic 1 = GPIO is an input (default).
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XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
TABLE 19: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.
They do not reset when the Reset Pin is asserted.
(Both TX and RX)
DLD
RHR
Bits 7-0 = 0x00
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 7-0 = 0x00
Bits 7-0 =0xX0 (Bits 7-4 = complement of modem inputs)
Bits 7-0 = 0x00
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0xFF
RESET STATE
HIGH
THR
IER
FCR
ISR
LCR
MCR
LSR
SHR
MSR
SFR
SPR
GPIOLVL
EMSR
FC
TRG
FCTR
EFR
XON1
XON2
XOFF1
XOFF2
GPIOINT
GPIO3T
GPIOINV
GPIOSEL
I/O SIGNALS
TX
RTS#
DTR#
HIGH
HIGH
INT (Intel or VLIO mode)
IRQ# (Motorola mode)
Three-State Condition
HIGH
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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
3.63 Volts
GND-0.3 V to 3.63 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja = 33oC/W, theta-jc = 22oC/W
Thermal Resistance (32-QFN)
theta-ja = 32oC/W, theta-jc = 16oC/W
Thermal Resistance (40-QFN)
theta-ja = 59oC/W, theta-jc = 16oC/W
Thermal Resistance (48-TQFP)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC_XXXX IS 1.62V TO 3.63V
LIMITS
1.8V
LIMITS
2.5V
LIMITS
3.3V
SYMBOL
PARAMETER
UNITS
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
VILCK Clock Input Low Level
VIHCK Clock Input High Level
-0.3
1.4
0.3
-0.3
2.0
0.4
-0.3
2.4
0.6
V
V
(XTAL1 input)
VCC_
CORE
VCC_
CORE
VCC_
CORE
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.3
1.4
0.2
5.5
-0.3
1.8
0.5
5.5
-0.3
2.0
0.7
5.5
0.4
V
V
V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 1.5 mA
0.4
0.4
VOH
Output High Voltage
2.0
V
V
V
IOH = -4 mA
IOH = -2 mA
IOH = -200 uA
1.8
1.4
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
±15
±15
5
±15
±15
5
±15
±15
5
uA
uA
pF
CIN
ICC
Power Supply Current
2
3
4
mA Ext Clk = 5MHz
uA See Test 1
ISLEEP Sleep Current
5
10
20
Test 1: All inputs should remain steady at VCC or GND to minimize Sleep current. RX input must idle at HIGH while asleep.
51
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
LIMITS
SYMBOL
PARAMETER
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
UNIT
MIN
MAX MIN
MAX MIN
MAX
XTAL1
ECLK
TECLK
UART Crystal Frequency
24
36
24
64
24
MHz
MHz
ns
External Clock Frequency
External Clock Time Period
100
13
7
5
16 Mode (Intel) Data Bus Read/Write Timing
TAS
TAH
TCS
TRD
TDY
TRDV
TDD
TWR
TDY
TDS
TDH
Address Setup Time
Address Hold Time
Chip Select Width
IOR# Strobe Width
Read Cycle Delay
Data Access Time
Data Disable Time
IOW# Strobe Width
Write Cycle Delay
Data Setup Time
Data Hold Time
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
50
50
50
45
45
45
40
40
40
35
15
40
40
20
0
45
25
40
20
50
50
30
0
45
45
25
0
68 Mode (Motorola) Data Bus Read/Write Timing
TADS
TADH
TRWS
Address Setup
Address Hold
0
0
0
0
0
0
0
0
0
ns
ns
ns
R/W# Setup to CS#
TRDA
TRDH
TWDS
TWDH
TRWH
TCSL
Data Access Time
45
25
40
15
35
ns
ns
ns
ns
ns
ns
ns
Data Disable Time
10
Write Data Setup
20
3
15
3
10
3
Write Data Hold
CS# De-asserted to R/W# De-asserted
CS# Strobe Width
0
0
0
50
50
45
45
40
40
TCSD
CS# Cycle Delay
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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
LIMITS
SYMBOL
PARAMETER
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
UNIT
MIN
MAX MIN
MAX MIN
MAX
VLIO Data Bus Read/Write Timing
TAS
TAH
Address Setup Time
Address Hold Time
15
15
5
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
TCSL
TLLA
TRD
Delay from CS# to LLA#/IOR#/IOW#
LLA# Strobe Width
0
10
50
5
0
0
10
45
5
10
40
5
IOR# Strobe Width
TLLAR
TLLAW
TDY
Delay from LLA# to IOR#
Delay from LLA# to IOW#
Read/Write Cycle Delay
Data Access Time
5
5
5
50
45
40
TRDV
TDD
45
25
40
20
35
15
Data Disable Time
TWR
TDS
IOW# Strobe Width
50
15
5
45
15
5
40
15
5
Data Setup Time
TDH
Data Hold Time
Modem/Interrupt Timing
TWDO
TMOD
TRSI
TSSI
TRRI
TSI
Delay From IOW# To Output
50
50
50
1
50
50
50
1
50
50
50
1
ns
ns
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Start To Interrupt
ns
Bclk
ns
45
45
33
45
45
33
45
45
33
ns
TWTS
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0x0)
8
8
8
8
8
8
Bclk
TWTS
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0xF)
48
48
48
Bclk
TWRI
TSSR
TRR
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
Delay From Center of Start To Reset TXRDY#
Reset Pulse Width
45
1
45
1
45
1
ns
Bclk
ns
45
45
8
45
45
8
45
45
8
TWT
ns
TSRT
TRST
Bclk
Bclk
ns
40
40
40
Baud Clock
16X or 8X or 4X of data rate
Hz
53
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 18. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 19. MODEM INPUT/OUTPUT TIMING
IO W #
IO W
A c tiv e
T W
D O
R T S #
D T R #
C h a n g e o f s ta te
C h a n g e o f s ta te
C D #
C T S #
D S R #
C h a n g e o f s ta te
C h a n g e o f s ta te
T M O D
T M O D
IN T
A c tiv e
A c tiv e
A c tiv e
A c tiv e
T R S I
IO R #
A c tiv e
A c tiv e
T M O D
C h a n g e o f s ta te
R I#
54
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 20. 16 MODE (INTEL) DATA BUS READ TIMING
A0-A2
CS#
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
TDY
TRD
TRD
IOR#
D0-D7
TDD
TDD
TRDV
TRDV
Valid Data
Valid Data
RDTm
FIGURE 21. 16 MODE (INTEL) DATA BUS WRITE TIMING
A0-A2
CS#
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
TDY
TWR
TWR
IOW#
D0-D7
TDH
TDH
TDS
Valid Data
TDS
Valid Data
16Write
55
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 22. 68 MODE (MOTOROLA) DATA BUS READ TIMING
A0-A2
CS#
Valid Address
Valid Address
ADS
T
CSL
T
ADH
T
CSD
T
RWS
T
RWH
T
R/W#
D0-D7
RDH
T
RDA
T
Valid Data
Valid Data
68Read
FIGURE 23. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
A0-A2
CS#
Valid Address
Valid Address
ADS
T
CSL
T
ADH
T
CSD
T
RWS
T
RWH
T
R/W#
D0-D7
T
WDH
WDS
T
Valid Data
Valid Data
68Write
56
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 24. VLIO MODE DATA BUS READ TIMING
AD7-
Upper Address
TAS
Lower Address
Data
TDD
AD0
CS#
TAH
T
CSL
TLLA
T
CSL
LLA#
IOR#
TRDV
TDY
T
LLAR
TRD
FIGURE 25. VLIO MODE DATA BUS WRITE TIMING
AD7-
AD0
Upper Address
TAS
Lower Address
Data
TDH
TAH
CS#
T
CSL
TLLA
TDS
LLA#
T
CSL
TDY
TLLAW
TWR
IOW#
57
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
FIGURE 26. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Active
Data
Active
Data
RXRDY#
Ready
Ready
Ready
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 27. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]
TX
Stop
Bit
Start
Bit
(Unloading)
D0:D7
D0:D7
D0:D7
TWTS
ISR is read
ISR is read
ISR is read
IER[1]
enabled
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
58
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE]
Start
Bit
RX
S
S
S
S
T
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
S
T
S
D0:D7
T
D0:D7
T
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T S
S
S
S
T
S
T
D0:D7
D0:D7
T
T
D0:D7
T
D0:D7
D0:D7
D0:D7
S
T
TWTS
ISR is read
TSI
IER[1]
enabled
ISR is read
TSRT
INT*
TX FIFO
Empty
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
59
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
Note: the actual center pad
is metallic and the size (D2)
is device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.039
0.002
0.010
0.201
0.150
0.012
MIN
0.80
0.00
0.15
4.90
3.50
0.18
MAX
1.00
0.05
0.25
5.10
3.80
0.30
A
A1
A3
D
0.031
0.000
0.006
0.193
0.138
0.007
D2
b
e
0.0197 BSC
0.50 BSC
L
0.012
0.008
0.020
-
0.35
0.20
0.45
-
k
60
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PACKAGE DIMENSIONS (40 PIN QFN - 6 X 6 X 0.9 mm)
Note: the actual center pad is
metallic and the size (D2) is
device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
0.80
0.00
0.15
5.90
4.80
0.18
MAX
1.00
0.05
0.25
6.10
5.00
0.30
A
A1
A3
D
0.031
0.000
0.006
0.232
0.189
0.007
0.039
0.002
0.010
0.240
0.197
0.012
D2
b
e
0.0197 BSC
0.50 BSC
L
0.014
0.008
0.018
-
0.35
0.20
0.45
-
k
61
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D
1
36
25
37
24
D
1
D
48
13
1
1
2
B
e
A
2
C
A
Seating
Plane
α
A
1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.047
0.006
0.041
0.011
0.008
0.362
0.280
MIN
1.00
0.05
0.95
0.17
0.09
8.80
6.90
MAX
1.20
0.15
1.05
0.27
0.20
9.20
7.10
A
A1
A2
B
0.039
0.002
0.037
0.007
0.004
0.346
0.272
C
D
D1
e
0.020 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
62
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REVISION HISTORY
DATE
REVISION
DESCRIPTION
April 2011
1.0.0
Final Datasheet.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2011 EXAR Corporation
Datasheet April 2011.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
63
相关型号：
XR16V2550IL-F
Serial I/O Controller, 2 Channel(s), 2MBps, CMOS, 5 X 5 MM, 0.90 MM HEIGHT, GREEN, QFN-32
EXAR
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