XR68M752IB49-F_技术文档

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

JUNE 2009

REV. 1.1.1

FEATURES

GENERAL DESCRIPTION

• 1.62 to 3.6 Volt Operation

1

The XR16M752/XR68M752 (M752) is a high

• Pin-to-pin and software compatible to TI’s

TL16C752B and Philips’ SC16C752B in the 48-

TQFP package

performance dual universal asynchronous receiver

and transmitter (UART) with 64 byte TX and RX

FIFOs. The M752 operates from 1.62 to 3.63 volts. It

is pin-to-pin and software compatible to the

TL16C752B and SC16C752B, but with additional

features such as a programmable fractional baud rate

generator, automatic RS-485 half-duplex direction

control, infrared mode and 8X and 4X sampling rate.

The standard features include 16 selectable TX and

RX FIFO trigger levels, automatic hardware (RTS/

CTS) and software (Xon/Xoff) flow control, and a

complete modem interface. Onboard registers

provide the user with operational status and data

error flags. An internal loopback capability allows

system diagnostics. Each channel is independently

programmable for data rates up to 16 Mbps at 3.3V

with a 4X sampling rate. The XR68M752 has an

additional 16/68# pin to select between the Intel and

Motorola bus interface. The M752 is available in the

48-pin TQFP, 32-pin QFN and 49-pin STBGA

packages.

• Two independent UART channels

■ Data rate of up to 16 Mbps at 3.3 V

■ Data rate of up to 12.5 Mbps at 2.5 V

■ Data rate of up to 8 Mbps at 1.8 V

■ Fractional Baud Rate Generator

■ Data sampling rates of 16X, 8X and 4X

■ Transmit and Receive FIFOs of 64 bytes

■ Programmable TX and RX FIFO Trigger Levels

■ Automatic Hardware (RTS/CTS) Flow Control

■ Automatic Software (Xon/Xoff) Flow Control

■ Halt and Resume Transmission Control

■ Automatic RS-485 Half-duplex Direction

Control Output via RTS#

■ Wireless Infrared (IrDA 1.0) Encoder/Decoder

■ Automatic sleep mode

■ Full modem interface

NOTE: 1 Covered by U.S. Patent #5,649,122

• Crystal oscillator (up to 24MHz) or external clock

(up to 64MHz) input

APPLICATIONS

• 48-TQFP, 32-QFN and 49-STBGA packages

• Portable Appliances

• Telecommunication Network Routers

• Ethernet Network Routers

• Cellular Data Devices

• Factory Automation and Process Controls

FIGURE 1. XR16M752 BLOCK DIAGRAM

1.62 to 3.63 Volt VCC

A2:A0

D7:D0

GND

IOR# (NC)

IOW# (R/W#)

UART Channel A

TXA, RXA, DTRA#,

64 Byte TX FIFO

CSA# (CS#)

CSB# (A3)

UART

Regs

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

IR

TX & RX

ENDEC

8-bit Data

Bus

Interface

INTA (IRQ#)

INTB (NC)

BRG

64 Byte RX FIFO

TXRDYA#

TXRDYB#

RXRDYA#

RXRDYB#

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

UART Channel B

(same as Channel A)

Reset/Reset#

16/68#

XTAL1

XTAL2

Crystal Osc/Buffer

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

FIGURE 2. PIN OUT ASSIGNMENT - TQFP AND QFN PACKAGES

36

35

34

33

32

31

30

29

28

27

26

25

RESET

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

INTA

D5

D6

1

2

3

4

5

6

D7

1

2

3

4

5

6

7

8

24 RESET

23 RTSA#

D6

D7

RXB

RXA

INTA

INTB

A0

22

21

20

19

18

RXB

RXA

TXA

TXB

XR16M752

48-pin TQFP

Intel Mode Only

TXRDYB#

TXA

XR16M752

32-pin QFN

Intel Mode Only

7

A1

TXB

8

9

INTB

A2

CSA#

CSB#

A0

OP2B#

17 NC

A1

CSA# 10

CSB# 11

NC 12

A2

NC

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

RESET

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

INTA

D5

D6

D7

1

2

3

4

5

6

7

8

24 RESET

23 RTSA#

D6

D7

RXB

RXA

INTA

INTB

A0

22

21

20

19

18

RXB

RXA

TXA

TXB

XR68M752

48- pin TQFP

Intel Mode

XR68M752

32-pin QFN

Intel Mode

TXRDYB#

TXA

7

A1

INTB

TXB

8

9

A2

CSA#

CSB#

VCC

A0

OP2B#

17 16/68#

A1

CSA# 10

CSB# 11

NC 12

A2

N C

VCC

36

35

34

33

32

31

30

29

28

27

26

25

RESET#

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

IRQ#

D5

D6

1

2

3

4

5

6

D7

1

2

3

4

5

6

7

8

24 RESET#

23 RTSA#

D6

D7

RXB

RXA

IRQ#

NC

A0

22

21

20

19

18

RXB

RXA

TXA

TXB

XR68M752

32-pin QFN

Motorola Mode

XR68M752

48- pin TQFP

Motorola Mode

TXRDYB#

A1

TXA

TXB

7

A2

CS#

A3

NC

8

9

17 16/68#

A0

OP2B#

GND

A1

CS# 10

A3 11

NC 12

A2

NC

GND

2

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 3. PIN OUT ASSIGNMENT - STBGA PACKAGE

A1 Corner

1

2

3

4

5 6 7

A

B

C

D

E

F

G

Transparent Top View

NC

D5

D3

D4

D0

D1

RIA#

D2

CTSA#

VCC

RS485#

DSRA#

OP2A#

INTA

DTRA#

RESET

DTRB#

INTB

D6

D7

RXB

TXA

TXRDYA#

TXRDYB#

RIB#

CDA#

TXB

RXA

RTSA#

RXRDYA#

DSRB#

RTSB#

CSB#

PWRSAVE

XTAL1

CSA#

IOW#

OP2B#

CDB#

GND

A0

A1

RXRDYB#

IOR#

CTSB#

16/68#

ENIR#

A2

XTAL2

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

DEVICE STATUS

XR16M752IL32

XR16M752IM48

XR68M752IL32

XR68M752IM48

XR68M752IB49

32-pin QFN

48-Lead TQFP

32-pin QFN

-40°C to +85°C

Active

48-Lead TQFP

49-pin STBGA

3

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

PIN DESCRIPTIONS

Pin Description

32-QFN

PIN #

48-TQFP 49-STBGA

NAME

TYPE

DESCRIPTION

PIN #

DATA BUS INTERFACE

A2

A1

A0

18

19

20

26

27

28

G7

E7

E6

I

Address data lines [2:0]. These 3 address lines select

one of the internal registers in UART channel A/B during

a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

2

3

C2

C1

B1

B2

A2

B4

B3

A3

I/O

Data bus lines [7:0] (bidirectional).

1

2

32

31

30

29

28

27

1

48

47

46

45

44

14

19

G4

I

IOR#

(NC)

When 16/68# pin is HIGH, the Intel bus interface is

selected and this input becomes read strobe (active low).

The falling edge instigates an internal read cycle and

retrieves the data byte from an internal register pointed

by the address lines [A2:A0], puts the data byte on the

data bus to allow the host processor to read it on the ris-

ing edge.

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input is not used.

12

15

F2

I

IOW#

When 16/68# pin is HIGH, it selects Intel bus interface

and this input becomes write strobe (active low). The fall-

ing edge instigates the internal write cycle and the rising

edge transfers the data byte on the data bus to an inter-

nal register pointed by the address lines.

(R/W#)

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input becomes read (HIGH) and write

(LOW) signal.

7

8

10

11

E2

E1

I

CSA#

(CS#)

When 16/68# pin is HIGH, this input is chip select A

(active low) to enable channel A in the device.

When 16/68# pin is LOW, this input becomes the chip

select (active low) for the Motorola bus interface.

CSB#

(A3)

When 16/68# pin is HIGH, this input is chip select B

(active low) to enable channel B in the device.

When 16/68# pin is LOW, this input becomes address

line A3 which is used for channel selection in the Motor-

ola bus interface. Input logic 0 selects channel A and

logic 1 selects channel B.

4

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

Pin Description

32-QFN

48-TQFP 49-STBGA

NAME

TYPE

DESCRIPTION

PIN #

22

30

D6

O

INTA

When 16/68# pin is HIGH for Intel bus interface, this out-

put becomes channel A interrupt output. The output state

is defined by the user through the software setting of

MCR[3]. INTA is set to the active mode and OP2A# out-

put LOW when MCR[3] is set to a logic 1. INTA is set to

the three state mode and OP2A# to HIGH when MCR[3]

is set to a logic 0. See MCR[3].

(IRQ#)

When 16/68# pin is LOW for Motorola bus interface, this

output becomes device interrupt output (active low, open

drain). An external pull-up resistor is required for proper

operation.

INTB

(NC)

21

29

D7

O

When 16/68# pin is HIGH for Intel bus interface, this out-

put becomes channel B interrupt output. The output state

is defined by the user through the software setting of

MCR[3]. INTB is set to the active mode and OP2A# out-

put to LOW when MCR[3] is set to a logic 1. INTA is set to

the three state mode and OP2A# to HIGH when MCR[3]

is set to a logic 0. See MCR[3].

When 16/68# pin is LOW for Motorola bus interface, this

output is not used.

TXRDYA#

-

43

C4

O

UART channel A Transmitter Ready (active low). The

output provides the TX FIFO/THR status for transmit

channel A. See Table 3. If it is not used, leave it uncon-

nected.

RXRDYA#

TXRDYB#

-

31

6

E5

D4

O

UART channel A Receiver Ready (active low). This out-

put provides the RX FIFO/RHR status for receive channel

A. See Table 3. If it is not used, leave it unconnected.

UART channel B Transmitter Ready (active low). The

output provides the TX FIFO/THR status for transmit

channel B. See Table 4. If it is not used, leave it uncon-

nected.

RXRDYB#

-

18

F4

O

UART channel B Receiver Ready (active low). This out-

put provides the RX FIFO/RHR status for receive channel

B. See Table 3. If it is not used, leave it unconnected.

MODEM OR SERIAL I/O INTERFACE

TXA

5

7

D3

UART channel A Transmit Data or infrared encoder data.

Standard transmit and receive interface is enabled when

MCR[6] = 0. In this mode, the TX signal will be HIGH dur-

ing reset or idle (no data). Infrared IrDA transmit and

receive interface is enabled when MCR[6] = 1. In the

Infrared mode, the inactive state (no data) for the Infrared

encoder/decoder interface is LOW. If it is not used, leave

it unconnected.

5

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

Pin Description

REV. 1.1.1

32-QFN

PIN #

48-TQFP 49-STBGA

NAME

TYPE

DESCRIPTION

PIN #

RXA

4

5

D2

I

UART channel A Receive Data or infrared receive data.

Normal receive data input must idle HIGH. The infrared

receiver pulses typically idles at LOW but can be inverted

by software control prior going in to the decoder, see

MCR[6]. If this pin is not used, tie it to VCC or pull it high

via a 100k ohm resistor.

RTSA#

CTSA#

23

25

33

38

D5

A5

O

I

UART channel A Request-to-Send (active low) or general

purpose output. This output must be asserted prior to

using auto RTS flow control, see EFR[6] and IER[6]. For

auto RS485 half-duplex direction control, see DLD[6].

UART channel A Clear-to-Send (active low) or general

purpose input. It can be used for auto CTS flow control,

see EFR[7] and IER[7]. This input should be connected to

VCC or GND when not used.

DTRA#

DSRA#

CDA#

-

34

39

40

41

32

A7

B6

C5

A4

C6

O

I

UART channel A Data-Terminal-Ready (active low) or

general purpose output. If it is not used, leave it uncon-

nected.

UART channel A Data-Set-Ready (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

I

UART channel A Carrier-Detect (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

RIA#

I

UART channel A Ring-Indicator (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

OP2A#

O

Output Port 2 Channel A - The output state is defined by

the user and through the software setting of MCR[3].

INTA is set to the active mode and OP2A# output LOW

when MCR[3] is set to a logic 1. INTA is set to the three

state mode and OP2A# output HIGH when MCR[3] is set

to a logic 0. See MCR[3]. If INTA is used, this output

should not be used as a general output else it will disturb

the INTA output functionality.

TXB

6

8

D1

O

UART channel B Transmit Data or infrared encoder data.

Standard transmit and receive interface is enabled when

MCR[6] = 0. In this mode, the TX signal will be HIGH dur-

ing reset or idle (no data). Infrared IrDA transmit and

receive interface is enabled when MCR[6] = 1. In the

Infrared mode, the inactive state (no data) for the Infrared

encoder/decoder interface is LOW. If it is not used, leave

it unconnected.

RXB

3

4

C3

I

UART channel B Receive Data or infrared receive data.

Normal receive data input must idle HIGH. The infrared

receiver pulses typically idles at logic 0 but can be

inverted by software control prior going in to the decoder,

see MCR[6]. If this pin is not used, tie it to VCC or pull it

high via a 100k ohm resistor.

6

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

Pin Description

32-QFN

48-TQFP 49-STBGA

NAME

TYPE

DESCRIPTION

PIN #

RTSB#

15

22

G5

O

UART channel B Request-to-Send (active low) or general

purpose output. This port must be asserted prior to using

auto RTS flow control, see EFR[6] and IER[6]. For auto

RS485 half-duplex direction control, see DLD[6].

CTSB#

16

23

F6

I

UART channel B Clear-to-Send (active low) or general

purpose input. It can be used for auto CTS flow control,

see EFR[7] and IER[7]. This input should be connected to

VCC or GND when not used.

DTRB#

DSRB#

CDB#

-

35

20

16

21

9

C7

F5

F3

E4

E3

O

I

UART channel B Data-Terminal-Ready (active low) or

general purpose output. If it is not used, leave it uncon-

nected.

UART channel B Data-Set-Ready (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

I

UART channel B Carrier-Detect (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

RIB#

I

UART channel B Ring-Indicator (active low) or general

purpose input. This input should be connected to VCC or

GND when not used.

OP2B#

O

Output Port 2 Channel B - The output state is defined by

the user and through the software setting of MCR[3].

INTB is set to the active mode and OP2B# output LOW

when MCR[3] is set to a logic 1. INTB is set to the three

state mode and OP2B# output HIGH when MCR[3] is set

to a logic 0. See MCR[3]. If INTB is used, this output

should not be used as a general output else it will disturb

the INTB output functionality.

ANCILLARY SIGNALS

XTAL1

XTAL2

10

11

13

14

G1

G2

I

Crystal or external clock input.

Crystal or buffered clock output.

O

PwrSave

16/68#

-

F1

I

PowerSave (active high, internal pull-down resistor). This

feature isolates the 752’s data bus interface from the host

preventing other bus activities that cause higher power

drain during sleep mode. See Sleep Mode with Auto

Wake-up and PowerSave Feature section for details.

17

24

G6

I

Intel or Motorola Bus Select (internal pull-up resistor).

This pin is not available for the XR16M752. This pin is

available for the XR68M752 only.

When 16/68# pin is HIGH, 16 or Intel Mode, the device

will operate in the Intel bus type of interface.

When 16/68# pin is LOW, 68 or Motorola mode, the

device will operate in the Motorola bus type of interface.

7

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

Pin Description

REV. 1.1.1

32-QFN

PIN #

48-TQFP 49-STBGA

NAME

TYPE

DESCRIPTION

PIN #

RESET

24

36

B7

I

When 16/68# pin is HIGH for Intel bus interface, this input

becomes RESET (active high). When 16/68# pin is LOW

for Motorola bus interface, this input becomes RESET#

(active low).

(RESET#)

A 40 ns minimum active pulse on this pin will reset the

internal registers and all outputs of channel A and B. The

UART transmitter output will be held HIGH, the receiver

input will be ignored and outputs are reset during reset

period (see Table 16).

EN485#

-

A6

I

Auto RS-485 half-duplex direction output enable for

channel A and B (active low, internal pull-up resistor).

Connect this pin to VCC or leave unconnected for normal

RTS# A/B function. Connect to GND for auto RS-485

half-duplex direction output via the RTS# A/B pins. The

Auto RS-485 half-duplex direction output control feature

can be disabled via DLD[6] after power-up. SEE ”AUTO

RS485 HALF-DUPLEX CONTROL” ON PAGE 18.

ENIR#

-

F7

I

IR mode enable for channel A and B (active low, internal

pull-up resistor). Connect this pin to VCC or leave uncon-

nected for normal TX and RX. Connect to GND for both

channel A and B to power up in the IR mode. The IR

mode can be disabled via DLD[7] after power-up. SEE

”INFRARED MODE” ON PAGE 20.

VCC

GND

26

13

42

17

-

B5

G3

-

Pwr

1.62V to 3.63V power supply.

Power supply common, ground.

Center Pad

The center pad on the backside of the QFN package is

metallic and should be connected to GND on the PCB.

The thermal pad size on the PCB should be the approxi-

mate size of this center pad and should be solder mask

defined. The solder mask opening should be at least

0.0025" inwards from the edge of the PCB thermal pad.

NC

9

12, 25, 37

A1

No Connection.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

8

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

1.0 PRODUCT DESCRIPTION

The XR16M752/XR68M752 (M752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous

Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device

configuration registers. The configuration registers set is 16550 UART compatible for control, status and data

transfer. Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS

hardware flow control, automatic Xon/Xoff and special character software flow control, programmable transmit

and receive FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud

rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps with 4X sampling clock rate.

The XR16M752 is a 1.62V to 3.63V device. The M752 is fabricated with an advanced CMOS process.

Enhanced Features

The M752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of

16 bytes in the industry standard 16C550. The M752 is designed to work with low supply voltage and high

performance data communication systems, that require fast data processing time. Increased performance is

realized in the M752 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow

control mechanism. This allows the external processor to handle more networking tasks within a given time.

For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses

a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to

service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the M752, the data buffer will

not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional

time for other applications and reducing the overall UART interrupt servicing time. In addition, the

programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided

for maximum data throughput performance especially when operating in a multi-channel system. The

combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and

reduces power consumption.

The M752 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the

external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive

state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic

state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The

auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has

to set DLD Bit-6 to “1”. This pin is HIGH for receive state and LOW for transmit state.

Data Rate

The M752 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate, 8 Mbps at 3.3V

with 8X sampling clock rate, and 4 Mbps at 3.3V with 16X internal sampling clock rate. The device can operate

with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1

pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for

data rates of up to 3.68 Mbps.

The rich feature set of the M752 is available through the internal registers. Automatic hardware/software flow

control, programmable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared

encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.

Following a power on reset or an external reset, the M752 is software compatible with previous generation of

UARTs, 16C450, 16C550 and 16C2550.

9

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

REV. 1.1.1

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The XR16M752 data interface supports the Intel compatible types of CPUs while the

XR68M752 supports both the Intel and Motorola compatible data interfaces. No clock (oscillator nor external

clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and

IOW# signals. Both UART channels share the same data bus for host operations. The data bus

interconnections are shown in Figure 4.

FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

UART

Channel A

Serial Interface of

RS-232, RS-422

or RS-485

A0

A1

A0

A1

A2

RIA#

OP2A#

(no connect)

IOR#

IOW#

IOR#

IOW#

TXB

RXB

CSA#

CSB#

UART_CSA#

UART_CSB#

DTRB#

RTSB#

UART_INTA

UART_INTB

INTA

INTB

UART

Channel B

Serial Interface of

RS-232, RS-422

or RS-485

CTSB#

DSRB#

CDB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

(no connect)

UART_RESET

RESET

GND

Intel Data Bus Interconnections

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

2.25 to 3.6 Volt VCC

VCC

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

Serial Interface of

RS-232, RS-422

or RS-485

UART

Channel A

A0

A1

A0

A1

A2

A3

CSB#

RIA#

OP2A#

(no connect)

VCC

IOR#

IOW#

R/W#

TXB

RXB

CSA#

UART_CS#

VCC

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

UART

Channel B

Serial Interface of

UART_IRQ#

INTA

INTB

RS-232, RS-422

or RS-485

(no connect)

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

(no connect)

GND

UART_RESET#

RESET#

Motorola Data Bus Interconnections

10

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.2

Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset

function in the device.

2.3

Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a

logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send

transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power

up initialization to write to the same internal registers, but do not attempt to read from both UARTs

simultaneously. Individual channel select functions are shown in Table 1.

TABLE 1: CHANNEL A AND B SELECT IN 16 MODE

CSA#

CSB#

FUNCTION

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel A and B selected

During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for

connection with Motorola, and other popular microprocessor bus types. In this mode the M752 decodes an

additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in

the Motorola Bus Mode. See Table 2.

TABLE 2: CHANNEL A AND B SELECT IN 68 MODE

CS#

A3

N/A

0

FUNCTION

1

0

UART de-selected

Channel A selected

Channel B selected

1

2.4

Channel A and B Internal Registers

Each UART channel in the M752 has a set of enhanced registers for control, monitoring and data loading and

unloading. The configuration register set is compatible to those already available in the standard single

16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status

and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/

LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/

DLM/DLD), and a user accessible Scratchpad Register (SPR).

Beyond the general 16C550 features and capabilities, the M752 offers enhanced feature registers (EFR, Xon/

Xoff 1, Xon/Xoff 2, TCR, TLR and DLD) that provide automatic RTS and CTS hardware flow control, Xon/Xoff

software flow control, automatic RS-485 half-duplex direction output enable/disable, and programmable FIFO

trigger level control. All the register functions are discussed in full detail later in “Section 3.0, UART Internal

Registers” on page 24.

11

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

2.5

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional

flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is

empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive

FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is

disabled (FCR bit-3 = 0), the M752 is placed in single-character mode for data transmit or receive operation.

When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the M752

sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO

becomes empty. The following table shows their behavior. Also see Figures 20 through 25.

TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(DMA Mode Enabled)

RXRDY# A/B LOW = 1 byte.

HIGH = no data.

LOW = at least 1 byte in FIFO. HIGH to LOW transition when FIFO reaches the

trigger level, or time-out occurs.

HIGH = FIFO empty.

LOW to HIGH transition when FIFO empties or

LSR[7] = 1.

TXRDY# A/B LOW = THR empty. LOW = FIFO empty.

LOW = FIFO is below the trigger level.

HIGH = byte in THR. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full.

2.6

INTA and INTB Outputs

The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.

Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 20

through 25.

TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER

Auto RS485

Mode

FCR BIT-0 = 0

FCR BIT-0 = 1 (FIFO ENABLED)

LOW = FIFO above trigger level

(FIFO DISABLED)

INTA/B Pin

NO

LOW = a byte in THR

HIGH = THR empty

HIGH = FIFO below trigger level or FIFO empty

YES

LOW = a byte in THR

LOW = FIFO above trigger level

HIGH = transmitter empty

HIGH = FIFO below trigger level or transmitter empty

TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

FCR BIT-0 = 1

(FIFO DISABLED)

(FIFO ENABLED)

INTA/B Pin

LOW = no data

HIGH = 1 byte

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

12

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.7

Crystal Oscillator or External Clock Input

The M752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not

5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.8,

Programmable Baud Rate Generator with Fractional Divisor” on page 13.”

FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS

XTAL1

XTAL2

R1

0-120 Ω

(Optional)

R2

500 ΚΩ− 1 ΜΩ

1.8432 MHz

to

Y1

24 MHz

C1

C2

22-47 pF

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). The programmable Baud

Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an

external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at 3.3V

with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note DAN108

on the EXAR web site at http://www.exar.com.

2.8

Programmable Baud Rate Generator with Fractional Divisor

Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The

prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide

the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further

divides this clock by a programmable divisor between 1 and (2¹⁶- 0.0625) in increments of 0.0625 (1/16) to

obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for

data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the

value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed

during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor

and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are used to select

a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator

Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 6 shows the

standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used

(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X sampling rate, these

data rates would double and at 4X sampling rate, these data rates would quadruple. Also, when using 8X

sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an odd number.

13

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a

multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value can be calculated

with the following equation(s):

Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’

The closest divisor that is obtainable in the M752 can be calculated using the following formula:

ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where

DLM = TRUNC(Required Divisor) >> 8

DLL = TRUNC(Required Divisor) & 0xFF

DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)

In the formulas above, please note that:

TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.

ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.

A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.

FIGURE 6. BAUD RATE GENERATOR

To Other

Channel

DLL, DLM and DLD

Registers

MCR Bit-7=0

(default)

Prescaler

Divide by 1

16X or 8X or 4X

Sampling

Rate Clock

to Transmitter

and Receiver

Crystal

Osc/

Buffer

XTAL1

XTAL2

Fractional Baud

Rate Generator

Logic

Prescaler

Divide by 4

MCR Bit-7=1

14

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING

Required

Output Data

Rate

DIVISOR FOR

16x Clock

(Decimal)

DIVISOR

OBTAINABLE IN

M752

DLM PROGRAM DLL PROGRAM DLD PROGRAM DATA ERROR

VALUE (HEX)

RATE (%)

400

2400

3750

625

3750

625

E

2

1

0

A6

71

38

9C

96

4E

3C

34

27

1E

1A

14

F

0

8

4

0

2

0

1

0

1

0

C

8

B

8

0

C

4

0

A

8

0

4800

312.5

156.25

150

312 8/16

156 4/16

150

0

9600

0

10000

19200

25000

28800

38400

50000

57600

75000

100000

115200

153600

200000

225000

230400

250000

300000

400000

460800

500000

750000

921600

1000000

0

78.125

60

78 2/16

60

0

52.0833

39.0625

30

52 1/16

39 1/16

30

0.04

0

26.0417

20

26 1/16

20

0.08

0

15

0

13.0208

9.7656

7.5

13

D

0.16

0

9 12/16

7 8/16

6 11/16

6 8/16

6

9

7

6.6667

6.5104

6

0.31

0.16

0

6

5

0

3.75

3 12/16

3 4/16

3

0

3.2552

3

0.16

0

3

2

0

1.6276

1.5

1 10/16

1 8/16

1

0.16

0

1

2.9

Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X

internal clock. A bit time is 16 (8 if 8X or 4 if 4X) clock periods (see DLD[5:4]). The transmitter sends the start-

bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The

status of the FIFO and TSR are reported in the Line Status Register (LSR[6:5]).

15

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

2.9.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.9.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

Register

(THR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X or 8X or 4X

Clock

( DLD[5:4] )

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.9.3

Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by

IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.)

Auto Software Flow Control

16X or 8X or 4X Clock

( DLD[5:4] )

Transmit Data Shift Register

(TSR)

TXFIFO1

16

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.10 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It

verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of

a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks

(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is

sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same

manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon

unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are

immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data

ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data

delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4

word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR

interrupt is enabled by IER bit-0.

2.10.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X or 8X or 4X Clock

( DLD[5:4] )

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Error

Tags in

LSR bits

4:2

Receive

Data Byte

and Errors

Receive Data

Holding Register

RHR Interrupt (ISR bit-2)

(RHR)

RXFIFO1

17

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X or 8X or 4X Clock

( DLD[5:4] )

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example

- RX FIFO trigger level selected at 16 bytes

:

(See Note Below)

64 bytes by 11-bit wide

FIFO

Data falls to

Resume Level

RTS# re-asserts when data falls to the Resume

Level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data FIFO

FIFO

Trigger=16

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

Data fills to

Halt Level

RTS# de-asserts when data fills to the Halt Level

to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

2.11 Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enabled to fit specific application requirement (see Figure 11):

• Enable auto RTS flow control using EFR bit-6.

• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.12

Auto RTS Halt and Resume

The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The

RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these

conditions, the M752 will continue to accept data if the remote UART continues to transmit data. It is the

responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,

it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated

when the RTS# output pin is asserted LOW (RTS On).

2.13

Auto RS485 Half-duplex Control

The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by DLD

bit-6. When idle, the auto RS485 half-duplex direction control signal (RTS#) is LOW for receive mode. When

data is loaded into the THR for transmission, the RTS# output is automatically asserted HIGH prior to sending

the data. After the last stop bit of the last character that has been transmitted, the RTS# signal is automatically

de-asserted. This helps in turning around the transceiver to receive the remote station’s response. When the

host is ready to transmit next polling data packet, it only has to load data bytes to the transmit FIFO. The

transmitter automatically re-asserts RTS# (HIGH) output prior to sending the data. In addition to changing the

behavior of the RTS# output, this feature also changes the behavior of the transmit empty interrupt (see

Table 4). In the 49-pin STBGA package, this feature can be enabled by connecting the EN485# pin to GND. If

this feature is enabled by the EN485# pin, it can be disabled by DLD bit-6 after power-up.

18

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.14

Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 11):

• Enable auto CTS flow control using EFR bit-7.

If using the Auto CTS interrupt:

• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the

CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as

the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-

asserted (LOW), indicating more data may be sent.

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

RXB

Auto RTS

Trigger Level

Auto CTS

Monitor

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

11

ON

RTSA#

OFF

7

2

ON

3

CTSB#

TXB

8

Restart

9

Data Starts

6

Suspend

4

RXA FIFO

Receive

Data

RX FIFO

12

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

19

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.15 Auto Xon/Xoff (Software) Flow Control

REV. 1.1.1

When software flow control is enabled (See Table 15), the M752 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the M752 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the M752 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the M752 will resume operation

and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to 0x00. Following reset the user can

write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff

characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are

selected, the M752 compares two consecutive receive characters with two software flow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control

mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the M752 automatically

sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level

(TCR[3:0]). To clear this condition, the M752 will transmit the programmed Xon-1,2 characters as soon as RX

FIFO falls down to the Resume Level.

2.16

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal

incoming RX data.

The M752 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal

Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison.

2.17 Infrared Mode

The M752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)

version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-

pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,

hence reduces the power consumption. See Figure 12 below.

The infrared encoder and decoder can be enabled by setting DLD register bit-7 to a ‘1’. When the infrared

feature is enabled, the transmit data output, TX, idles LOW. Likewise, the RX input also idles LOW, see

Figure 12. In the 49-pin STBGA package, this feature can be enabled upon power-up by connecting the

ENIR# pin of the STBGA package to GND. If the IR mode is enabled via the ENIR# pin, it can be disabled

after power-up via DLD bit-7.

The wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each

time it senses a light pulse, it returns a logic 1 to the data bit stream.

20

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data Bits

1

0

TX Data

Transmit

IR Pulse

(TX Pin)

1/2 Bit Time

Bit Time

3/16 Bit Time

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

1 1

1

0

RX Data

Data Bits

Character

IRdecoder-

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

2.18

Sleep Mode with Wake-Up Indicator and PowerSave Feature

The M2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave

feature is included to reduce power consumption when the device is not actively used.

2.19 Sleep Mode with Auto Wake-Up

The M752 supports low voltage system designs, hence, a sleep mode is included to reduce its power

consumption when the chip is not actively used. In addition, there is a PowerSave Feature on the 49-pin

STBGA package that eliminates any unnecessary external buffer.

All of these conditions must be satisfied for the M752 to enter sleep mode:

■ no interrupts pending for both channels of the M752 (ISR bit-0 = 1)

■ sleep mode of both channels are enabled (IER bit-4 = 1)

■ modem inputs are not toggling (MSR bits 0-3 = 0)

■ RX input pins are idling HIGH

The M752 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The M752 resumes normal operation by any of the following:

■ a receive data start bit transition (HIGH to LOW)

■ a data byte is loaded to the transmitter, THR or FIFO

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the M752 is awakened by any one of the above conditions, it will return to the sleep mode automatically after

all interrupting conditions have been serviced and cleared. If the M752 is awakened by the modem inputs, a

read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while

an interrupt is pending from channel A or B. The M752 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the

M752 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical

Characteristics on page 40. If the input lines are floating or are toggling while the M752 is in sleep mode, the

current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer

would be required to keep the address, data and control lines steady to achieve the low current.

2.19.1 PowerSave Feature (49-pin STBGA pacakge only)

The PowerSave Feature will eliminate the need for an external buffer by internally isolating the address, data

and control signals from other bus activities that could cause wasteful power drain. The M752 enters

PowerSave mode when pin F1 is connected to VCC and the M752 is in sleep mode (see Sleep Mode section

above).

Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:

■ a receive data start bit transition (HIGH to LOW)

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

The M752 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem

inputs) and all interrupting conditions have been serviced and cleared. The 2751 will stay in the PowerSave

mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to

GND.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the

first few receive characters may be lost. The number of characters lost during the restart also depends on your

operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep

RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition

upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)

are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a

47k-100k ohm pull-up resistor on the RXA and RXB pins.

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.20

Internal Loopback

The M752 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.

Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the

UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during

internal loopback.

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TXA/TXB

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RXA/RXB

VCC

RTSA#/RTSB#

RTS#

CTS#

CTSA#/CTSB#

VCC

DTRA#/DTRB#

DTR#

DSR#

DSRA#/DSRB#

OP1#

RI#

RIA#/RIB#

VCC

OP2A#/OP2B#

OP2#

CD#

CDA#/CDB#

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

3.0 UART INTERNAL REGISTERS

REV. 1.1.1

Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0,

A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 7 and

Table 8.

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS

ADDRESSES

REGISTER

READ/WRITE

COMMENTS

A2 A1 A0

16C550 COMPATIBLE REGISTERS

0

0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

0

0 0

0 1

1 0

DLL - Divisor LSB

Read/Write

LCR[7] = 1, LCR ≠ 0xBF

0

DLM - Divisor MSB

DLD - Divisor Fractional

LCR[7] = 1, LCR ≠ 0xBF,

EFR[4] = 1

0

0 1

1 0

IER - Interrupt Enable Register

Read/Write

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

0

1

1 1

0 0

0 1

1 0

1 1

1 0

1 1

LCR - Line Control Register

MCR - Modem Control Register

LSR - Line Status Register

Read/Write

Read-only

Read/Write

Read-only

LCR ≠ 0xBF

MSR - Modem Status Register

SPR - Scratch Pad Register

TCR - Transmission Control Register

TLR - Trigger Level Register

FIFO Rdy - FIFO Ready Register

See Table 13

See Table 12

See Table 13

See Table 12

ENHANCED REGISTERS

0

1

1 0

0 0

0 1

1 0

1 1

EFR - Enhanced Function Register

Xon-1 - Xon Character 1

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

Read/Write

LCR = 0xBF

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REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

.

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

REG

READ/

ADDRESS

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

NAME WRITE

A2-A0

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

TX

Bit-0

WR

IER RD/WR

Modem RX Line

Stat. Int. Stat. Int. Empty

Enable Enable

RXData

Int.

Enable

CTS Int. RTS Int. Xoff Int. Sleep

Enable

Int

Enable

Mode

Enable

0 1 0

ISR

RD

FIFOs

Enabled Enabled

FIFOs

0/

INT

LCR[7]=0

Source Source Source Source

Bit-3

INT

Bit-2

Bit-1

Bit-0

Source Source

Bit-5

Bit-4

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0/

DMA TXFIFO

Mode

Enable

RX

FIFO

Reset

FIFOs

Enable

Reset

TXFIFO TXFIFO

Trigger Trigger

0 1 1

1 0 0

LCR RD/WR Divisor

Enable

Set TX Set Par-

Even

Parity

Enable

Stop

Bits

Word

Length Length

Word

Break

ity

Bit-1

Bit-0

MCR RD/WR

0/

Internal OP2#/

Lopback INT Out-

Enable

FIFO

Rdy

RTS#

Output Output

DTR#

Clock TCR and XonAny

Pres-

caler

put

Enable

Enable Control Control

TLR

ENable

(OP1#)

Select

LCR≠0xBF

1 0 1

1 1 0

LSR

RD

RXFIFO THR &

THR

Empty

RX

Over-

run

RXData

Ready

Global

Error

TSR

Empty

Break Framing Parity

Error

MSR

CD# RI# Input DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR#

Delta

CTS#

See Table 13

See Table 12

See Table 13

Input

1 1 1

1 1 0

SPR RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

TCR RD/WR Resume Resume Resume Resume

Bit-3 Bit-2 Bit-1 Bit-0

Halt

Bit-3

Bit-2

Bit-1

Bit-0

1 1 1

TLR RD/WR RX Trig RX Trig RX Trig RX Trig TX Trig TX Trig TX Trig TX Trig

See Table 12

Bit-3

Bit-2

Bit-1

Bit-0

Bit-3

Bit-2

Bit-1

Bit-0

FIFO

Rdy

RD

0

RXFIFO RXFIFO

B Status A Status

0

TXFIFO TXFIFO

B Status A Status

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

REG

READ/

ADDRESS

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

NAME WRITE

A2-A0

Baud Rate Generator Divisor

LCR[7]=1

0 0 0

0 0 1

0 1 0

DLL RD/WR

DLM RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR≠0xBF

LCR[7]=1

LCR≠0xBF

EFR[4]=1

DLD RD/WR IR Mode

Auto

4X Mode 8X Mode Bit-3

RS485

Direction

Control

Enhanced Registers

Enable

0 1 0

EFR RD/WR

Auto AutoRTS Special

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

CTS

Enable

Char

IER [7:4],

ISR [5:4],

FCR[5:4],

Enable

Select

MCR[7:5],

DLD

Bit-2

Bit-1

Bit-0

Bit-3

1 0 0 XON1 RD/WR

1 0 1 XON2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR=0XBF

1 1 0 XOFF RD/WR

1

1 1 1 XOFF RD/WR

2

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE ”RECEIVER” ON PAGE 17.

4.2 Transmit Holding Register (THR) - Write-Only

SEE ”TRANSMITTER” ON PAGE 15.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

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4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M752 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

• Logic 0 = Disable the receive data ready interrupt (default).

• Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when spaces in the FIFO is above the programmed trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

• Logic 0 = Disable Transmit Ready interrupt (default).

• Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the

character has been received. LSR bit-7 is set if any character in the RX FIFO has a parity or framing error, or is

a break character. LSR[4:2] always show the error status for the received character available for reading from

the RX FIFO. If IER[2] = 1, an LSR interrupt will be generated as long as LSR[7] = 1, ie. the RX FIFO contains

at lease one character with an error.

• Logic 0 = Disable the receiver line status interrupt (default).

• Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

• Logic 0 = Disable the modem status register interrupt (default).

• Logic 1 = Enable the modem status register interrupt.

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

• Logic 0 = Disable Sleep Mode (default).

• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).

• Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the RTS# interrupt (default).

REV. 1.1.1

• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the CTS# interrupt (default).

• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

low to high.

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3, 4 and 7.

• RXRDY is by RX trigger level.

• RXRDY Time-out is by a 4-char plus 12 bits delay timer.

• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).

• MSR is by any of the MSR bits 0, 1, 2 and 3.

• Receive Xoff/Special character is by detection of a Xoff or Special character.

• CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.

• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

4.4.2

Interrupt Clearing:

• LSR interrupt is cleared by reading all characters with errors out of the RX FIFO.

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

• Xoff interrupt is cleared when Xon character(s) is received.

• Special character interrupt is cleared by a read to ISR.

• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

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]

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).

ISR[4]: Xoff/Xon or Special Character Interrupt Status

This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of

the Xoff character(s). If this is an Xoff interrupt, it is cleared when XON is received. If it is a special character

interrupt, it is cleared by reading ISR.

ISR[5]: RTS#/CTS# Interrupt Status

This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

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REV. 1.1.1

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)

(logic 0 = default, TX trigger level = 8)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO

did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a

transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.

Table 10 shows the selections.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level = 8)

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when

the number of the characters in the FIFO is greater than the receive trigger level or when a receive data

timeout occurs (see “Section 2.10, Receiver” on page 17).

TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION

RECEIVE

TRIGGER LEVEL TRIGGER LEVEL

TRANSMIT

FCR

BIT-7

FCR

BIT-6

FCR

BIT-5

FCR

BIT-4

(CHARACTERS)

(SPACES)

0

1

0

1

0

1

8

16

32

56

0

1

0

1

0

1

8

16

56

60

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5

6 (default)

7

8

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

STOP BIT LENGTH

(BIT TIME(S))

WORD

LENGTH

BIT-2

0

1

5,6,7,8

5

1

1-1/2

6,7,8

2 (default)

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 11 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.

• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

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LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

• LCR BIT-5 = logic 0, parity is not forced (default).

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive

data.

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive

data.

TABLE 11: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

X

0

1

X

0

1

0

1

0

1

Odd parity

Even parity

Force parity to mark, “1”

Forced parity to space, “0”

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

• Logic 0 = No TX break condition (default).

• Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL, DLM and DLD) enable.

• Logic 0 = Data registers are selected (default).

• Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force DTR# output HIGH (default).

• Logic 1 = Force DTR# output LOW.

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by

EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control enabled by FCTR bit-

3. If the modem interface is not used, this output may be used as a general purpose output.

• Logic 0 = Force RTS# HIGH (default).

• Logic 1 = Force RTS# LOW.

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MCR[2]: OP1# / FIFO Rdy Enable

OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode

(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface

signal.

This bit is also used to select between the SPR, TLR and FIFO Rdy registers. All of these registers are

accessible at address offset 0x7 when LCR≠0xBF. However, LCR = 0xBF is required to access EFR.

TABLE 12: REGISTER AT ADDRESS OFFSET 0X7

EFR[4] MCR[6] MCR[4, 2]

Register at Address Offset 0x7

Scratchpad Register (SPR)

Trigger Level Register (TLR)

FIFO Ready Register (FIFO Rdy)

0

1

X

0

1

X

≠’01’

=’01’

MCR[3]: OP2# Output / INT Output Enable

This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used

as a general purpose output.

• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).

• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.

MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)

• Logic 0 = Disable Xon-Any function (default).

• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and

the M752 is programmed to use the Xon/Xoff flow control.

MCR[6]: TCR and TLR Enable (requires EFR bit-4=1 to write to this bit)

This bit enables the TCR and TLR registers at address offset 0x6 and 0x7, respectively. See Table 12 above

for the correct register setting to access the TLR register. See Table 13 below for the setting to access the

TCR register.

• Logic 0 = Reserved (default).

• Logic 1 = Enable access to the TCR and TLR registers.

TABLE 13: REGISTER AT ADDRESS OFFSET 0X6

EFR[4] MCR[6]

Register at Address Offset 0x6

Modem Status Register (MSR)

Trigger Control Register (TCR)

0

1

X

0

1

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MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit)

REV. 1.1.1

• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

Baud Rate Generator without further modification, i.e., divide by one (default).

• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host.

LSR[0]: Receive Data Ready Indicator

• Logic 0 = No data in receive holding register or FIFO (default).

• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Error Flag

• Logic 0 = No overrun error (default).

• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Tag

• Logic 0 = No parity error (default).

• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

• Logic 0 = No framing error (default).

• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

LSR[4]: Receive Break Error Tag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register are

used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem

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changes state. These bits may be used for general purpose inputs when they are not used with modem

signals.

MSR[0]: Delta CTS# Input Flag

• Logic 0 = No change on CTS# input (default).

• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

• Logic 0 = No change on DSR# input (default).

• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

• Logic 0 = No change on RI# input (default).

• Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

• Logic 0 = No change on CD# input (default).

• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto

CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the

modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has

finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of

the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The

CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

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4.10 Scratch Pad Register (SPR) - Read/Write

REV. 1.1.1

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. There are also

two other registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register.

See Table 12.

4.11 Transmission Control Register (TCR) - Read/Write (requires EFR bit-4 = 1)

This register replaces MSR and is accessible only when MCR[6] = 1. This 8-bit register is used to store the RX

FIFO threshold levels to halt/resume transmission during hardware or software flow control.

TCR[3:0]: RX FIFO Halt Level

A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX

FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used

or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that

this value is greater than the RX Trigger Level.

TCR[7:4]: RX FIFO Resume Level

A value of 0-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the Resume Level. When the

RX FIFO is less than or equal to this value, the RTS# output will be re-asserted if Auto RTS flow control is used

or the XON character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this

value is less than the RX Trigger Level.

4.12 Trigger Level Register (TLR) - Read/Write (requires EFR bit-4 = 1)

This register replaces SPR and is accessible under the conditions listed in Table 12. This 8-bit register is used

to store the RX and TX FIFO trigger levels used for interrupts.

TLR[3:0]: TX FIFO Trigger Level

A value of 4-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the TX FIFO Trigger Level.

When the number of available spaces in the TX FIFO is greater than or equal to this value, a Transmit Ready

interrupt is generated. For any non-zero value, TCR[3:0] will be used as the TX FIFO Trigger Level. If

TCR[3:0] = 0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4]. See Table 10.

TLR[7:4]: RX FIFO Trigger Level

A value of 4-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the RX FIFO Trigger Level.

When the number of characters received in the RX FIFO is greater than or equal to this value, a Receive Data

Ready interrupt is generated (a Receive Data Timeout interrupt is independent of the RX FIFO Trigger Level

and can be generated any time there is at least 1 byte in the RX FIFO and the RX input has been idle for the

timeout period described in “Section 2.10, Receiver” on page 17). For any non-zero value, TCR[7:4] will be

used as the RX FIFO Trigger Level. If TCR[7:4] = 0x0, then the RX FIFO Trigger Level is the value selected by

FCR[7:6]. See Table 10.

4.13 Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write

These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and

DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be

enabled via EFR bit-4 before it can be accessed. SEE ”PROGRAMMABLE BAUD RATE GENERATOR

WITH FRACTIONAL DIVISOR” ON PAGE 13.

DLD[5:4]: Sampling Rate Select

These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will

double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.

TABLE 14: SAMPLING RATE SELECT

DLD[5]

DLD[4]

SAMPLING RATE

0

16X

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TABLE 14: SAMPLING RATE SELECT

DLD[5]

DLD[4]

SAMPLING RATE

0

1

8X

4X

X

DLD[6]: Auto RS-485 Direction Control

• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register

becomes empty and transmit shift register is shifting data out. The RTS# output can be used as a general

purpose output or for Auto RTS flow control.

• Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its

output logic state from HIGH to LOW one bit time after the last stop bit of the last character is shifted out.

Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The

RTS# output pin will automatically return to a HIGH when a data byte is loaded into the TX FIFO. See

“Section 2.13, Auto RS485 Half-duplex Control” on page 18.

DLD[7]: Infrared Encoder/Decoder Enable

• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).

• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. While in this mode, the infrared TX output will be idling LOW. SEE ”INFRARED MODE” ON

PAGE 20.

4.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

CONT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

0

X

0

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

0

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

1

Transmit Xon1, Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

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REV. 1.1.1

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

CONT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR,

TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the

new values. This feature prevents legacy software from altering or overwriting the enhanced functions once

set. Normally, it is recommended to leave it enabled, logic 1.

• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-

7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,

MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).

• Logic 1 = Enables the above-mentioned register bits to be modified by the user.

EFR[5]: Special Character Detect Enable

• Logic 0 = Special Character Detect Disabled (default).

• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and

RTS de-asserts HIGH at the programmed HALT level. RTS# will return LOW when FIFO data falls below the

programmed RESUME level. The RTS# output must be asserted (LOW) before the auto RTS can take effect.

RTS# pin will function as a general purpose output when hardware flow control is disabled.

• Logic 0 = Automatic RTS flow control is disabled (default).

• Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

• Logic 0 = Automatic CTS flow control is disabled (default).

• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.

Data transmission resumes when CTS# returns LOW.

4.14.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.

For more details, see Table 8.

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TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B

REGISTERS

RESET STATE

DLM, DLL

DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.

They do not reset when the Reset Pin is asserted.

DLD

RHR

THR

IER

Bits 7-0 = 0x00

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x1D

Bits 7-0 = 0x00

Bits 7-0 = 0x60

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

SPR

Bits 7-0 = 0xFF. Only resets to these values during a power up. They do not

reset when the Reset Pin is asserted.

TCR

TLR

Bits 7-0 = 0x0F

Bits 7-0 = 0x00

Bits 7-0 = 0x03

Bits 7-0 = 0x00

FIFO Rdy

EFR

XON1

Bits 7-0 = 0x00. Only resets to these values during a power up. They do not

reset when the Reset Pin is asserted.

XON2

XOFF1

XOFF2

Bits 7-0 = 0x00. Only resets to these values during a power up. They do not

reset when the Reset Pin is asserted.

Bits 7-0 = 0x00. Only resets to these values during a power up. They do not

reset when the Reset Pin is asserted.

Bits 7-0 = 0x00. Only resets to these values during a power up. They do not

reset when the Reset Pin is asserted.

I/O SIGNALS

TX

RESET STATE

HIGH

OP2#

HIGH

RTS#

HIGH

DTR#

HIGH

RXRDY#

TXRDY#

INT

HIGH

LOW

Three-State Condition

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5.0 ELECTRICAL CHARACTERISTICS

REV. 1.1.1

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

4 Volts

Voltage at Any Pin

GND-0.3V to 4V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja =59^oC/W, theta-jc = 16^oC/W

Thermal Resistance (48-TQFP)

theta-ja = 33^oC/W, theta-jc = 22^oC/W

Thermal Resistance (32-QFN)

DC ELECTRICAL CHARACTERISTICS

o

TA= -40 to +85 C, Vcc is 1.62V to 3.63V

LIMITS

2.5V

LIMITS

SYMBOL

PARAMETER

1.8V

3.3V

UNITS

CONDITIONS

MIN

-0.3

1.4

MAX

MIN

MAX

MIN

MAX

V_ILCKClock Input Low Level

V_IHCKClock Input High Level

0.3

-0.3

1.8

0.6

-0.3

0.6

V

VCC

0.2

VCC

0.5

2.4

-0.3

2.0

VCC

0.8

V_IL

V_IH

V_OL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.3

1.4

-0.3

1.8

VCC

0.4

V

I_OL= 4 mA

0.4

I_OL= 2 mA

0.4

I_OL= 1.5 mA

V_OH

Output High Voltage

2.0

V

I_OH= -1 mA

1.8

I_OH= -400 uA

I_OH= -200 uA

1.4

I_IL

I_IH

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

±10

5

±10

5

±10

5

uA

pF

mA

uA

C_IN

I_CC

Power Supply Current

0.5

3

1

2

XTAL1 = 2 MHz

See Test 1

I_SLEEPSleep Current (16 Mode)

I_SLEEPSleep Current (68 Mode)

10

75

15

100

50

See Test 1

Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-

D7, IOR#, IOW#, CSA# (CS# in 68 Mode), CSB# and all modem inputs. Also, RXA and RXB inputs must idle

HIGH while asleep. Floating inputs will result in sleep currents in the mA range.

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AC ELECTRICAL CHARACTERISTICS

o

Unless otherwise noted: TA=-40 to +85 C, Vcc=1.62 - 3.63V, 70 pF load where applicable

LIMITS

SYMBOL

PARAMETER

1.8V ± 10%

2.5V ± 10%

3.3V ± 10%

UNIT

MIN

MAX MIN

MAX

XTAL1

ECLK

T_ECLK

UART Crystal Oscillator

24

32

24

50

24

64

MHz

ns

External Clock

External Clock Time Period

15

5

10

5

7

5

T_AS

T_AH

Address Setup Time (16 mode)

Address Hold Time (16 mode)

Chip Select Width (16 mode)

IOR# Strobe Width (16 mode)

Read Cycle Delay (16 mode)

Data Access Time (16 mode)

Data Disable Time (16 mode)

IOW# Strobe Width (16 mode)

Write Cycle Delay (16 mode)

Data Setup Time (16 mode)

Data Hold Time (16 mode)

Address Setup (68 Mode)

ns

0

T_CS

60

30

T_RD

T_DY

T_RDV

T_DD

55

20

25

20

25

10

0

60

15

5

0

30

10

5

0

30

10

5

T_WR

T_DY

T_DS

T_DH

T_ADS

T_ADH

T_RWS

T_RDA

T_RDH

T_WDS

T_WDH

T_RWH

5

Address Hold (68 Mode)

0

R/W# Setup to CS# (68 Mode)

Read Data Access (68 mode)

Read Data Disable (68 mode)

Write Data Setup (68 mode)

Write Data Hold (68 Mode)

5

55

20

25

20

25

10

15

5

10

5

10

5

CS# De-asserted to R/W# De-asserted (68

Mode)

5

T_CSL

T_CSD

T_WDO

T_MOD

T_RSI

CS# Width (68 Mode)

60

30

ns

CS# Cycle Delay (68 Mode)

Delay From IOW# To Output

50

1

50

1

50

1

ns

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

ns

T_SSI

Bclk

41

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

REV. 1.1.1

o

Unless otherwise noted: TA=-40 to +85 C, Vcc=1.62 - 3.63V, 70 pF load where applicable

LIMITS

SYMBOL

PARAMETER

1.8V ± 10%

2.5V ± 10%

3.3V ± 10%

UNIT

MIN

MAX MIN

MAX

T_RRI

T_SI

Delay From IOR# To Reset Interrupt

Delay From Stop To Interrupt

45

24

45

1

45

24

45

1

45

24

45

1

ns

T_INT

T_WRI

T_SSR

T_RR

Delay From Initial INT Reset To Transmit Start

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

Reset Pulse Width

8

Bclk

ns

Bclk

ns

45

8

45

8

45

8

T_WT

T_SRT

T_RST

Bclk

ns

Bclk

ns

40

Baud Clock

16X or 8X or 4X of data rate

Hz

FIGURE 14. CLOCK TIMING

T_ECLK

T_ECL

T_ECH

VIH

External

Clock

VIL

42

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B

IOW #

Active

T_{W DO}

RTS#

DTR#

Change of state

CD#

CTS#

DSR#

Change of state

T_MOD

INT

Active

T_RSI

IOR#

Active

T_MOD

Change of state

RI#

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_RD

IOR#

T_DD

T_RDV

D0-D7

Valid Data

RDTm

43

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_WR

IOW#

T_DH

T_DS

Valid Data

T_DS

Valid Data

D0-D7

16Write

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING

A0-A2

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

TRDH

TRDA

Valid Data

68Read

44

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING

A0-A2

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

T

WDH

TWDS

Valid Data

68Write

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

45

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

TX

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B

Start

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

46

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

47

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

S

D0:D7

S

D0:D7

T

D0:D7

S

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

48

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)

D

1

36

25

37

24

D

1

D

48

13

1

2

B

e

A

2

C

A

Seating

Plane

α

A

1

L

Note: The control dimension is the millimeter column

INCHES MILLIMETERS

MAX

SYMBOL

MIN

MAX

1.20

0.15

A

0.039

0.002

0.047

0.006

1.00

0.05

A₁

A₂

0.037

0.041

0.95

1.05

B

C

0.007

0.004

0.346

0.272

0.011

0.008

0.362

0.280

0.17

0.09

8.80

6.90

0.27

0.20

9.20

7.10

D

D₁

e

L

a

0.020 BSC

0.50 BSC

0.018

0.030

0.45

0.75

0°

7°

0°

7°

49

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)

Note: the actual center pad

is metallic and the size (D2)

is device-dependent with a

typical tolerance of 0.3mm

Note: The control dimension is in millimeter.

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.039

0.002

0.010

0.201

0.150

0.012

MIN

0.80

0.00

0.15

4.90

3.50

0.18

MAX

1.00

0.05

0.25

5.10

3.80

0.30

A

A1

A3

D

0.031

0.000

0.006

0.193

0.138

0.007

D2

b

e

0.0197 BSC

0.50 BSC

L

0.012

0.008

0.020

-

0.35

0.20

0.45

-

k

50

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

PACKAGE DIMENSIONS (49 PIN SHRINK THIN BALL GRID ARRAY - 4 X 4mm)

7

6

5

4

3

2

1

A1 corner

A

B

C

D

E

F

D

D1

G

D1

D

(A1 corner feature is mfger option)

Seating

Plane

b

A2

A

A1

e

Note: The control dimension is in millimeter.

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.046

0.011

0.035

0.161

MIN

MAX

1.18

0.28

0.90

4.10

A

A1

A2

D

0.035

0.007

0.028

0.154

0.88

0.18

0.70

3.90

D1

b

0.118 BSC

3.00 BSC

0.010

0.014

0.26

0.36

e

0.020 BSC

0.50 BSC

51

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REVISION HISTORY

DATE

July 2006

REVISION

P1.0.0

1.0.0

DESCRIPTION

Preliminary Datasheet.

September 2006

May 2007

Final Datasheet. Updated AC Electrical Characteristics.

1.0.1

Corrected pin names pin out assignment for 48-pin TQFP package for XR68M752 in

Motorola mode. Added GND center pad for QFN package to pin description. Added

Motorola mode Read/Write timing waveforms. Updated QFN package dimensions

drawing to show minimum "k" parameter.

May 2007

1.0.2

1.1.0

Updated pin description table, correct pin # of RXA in QFN-32 package.

December 2007

Added 49-pin STBGA package with these additional pins - PwrSave, ENIR# and

EN485#.

June 2009

1.1.1

Corrected page 30 FCR[7:6] and FCR[5:4] default trigger levels.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet June 2009.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

52

XR16M752/XR68M752

REV. 1.1.1

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................ 1

APPLICATIONS .............................................................................................................................................. 1

FEATURES.................................................................................................................................................... 1

FIGURE 1. XR16M752 BLOCK DIAGRAM .......................................................................................................................................... 1

FIGURE 2. PIN OUT ASSIGNMENT - TQFP AND QFN PACKAGES ....................................................................................................... 2

FIGURE 3. PIN OUT ASSIGNMENT - STBGA PACKAGE ...................................................................................................................... 3

ORDERING INFORMATION ............................................................................................................................... 3

PIN DESCRIPTIONS ........................................................................................................ 4

1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9

2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10

2.1 CPU INTERFACE .............................................................................................................................................. 10

FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS................................................................................................ 10

2.2 DEVICE RESET................................................................................................................................................. 11

2.3 CHANNEL A AND B SELECTION .................................................................................................................... 11

TABLE 1: CHANNEL A AND B SELECT IN 16 MODE .......................................................................................................................... 11

TABLE 2: CHANNEL A AND B SELECT IN 68 MODE .......................................................................................................................... 11

2.4 CHANNEL A AND B INTERNAL REGISTERS................................................................................................. 11

2.5 DMA MODE ....................................................................................................................................................... 12

TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 12

2.6 INTA AND INTB OUTPUTS............................................................................................................................... 12

TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 12

TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 12

2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13

FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 13

2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13

FIGURE 6. BAUD RATE GENERATOR ............................................................................................................................................... 14

TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 15

2.9 TRANSMITTER.................................................................................................................................................. 15

2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 16

2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................... 16

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 16

2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 16

2.10 RECEIVER....................................................................................................................................................... 17

2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 17

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 17

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 18

2.11 AUTO RTS (HARDWARE) FLOW CONTROL................................................................................................ 18

2.12 AUTO RTS HALT AND RESUME .................................................................................................................. 18

2.13 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 18

2.14 AUTO CTS FLOW CONTROL........................................................................................................................ 19

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19

2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20

2.16 SPECIAL CHARACTER DETECT.................................................................................................................. 20

2.17 INFRARED MODE........................................................................................................................................... 20

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 21

2.18 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE ........................................... 22

2.19 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 22

2.19.1 POWERSAVE FEATURE (49-PIN STBGA PACAKGE ONLY) ................................................................................. 22

2.20 INTERNAL LOOPBACK................................................................................................................................. 23

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 23

3.0 UART INTERNAL REGISTERS............................................................................................................. 24

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 24

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 25

4.0 INTERNAL REGISTER DESCRIPTIONS.............................................................................................. 26

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY.................................................................................. 26

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26

I

XR16M752/XR68M752

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 27

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28

4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28

4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 29

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 29

TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31

TABLE 11: PARITY SELECTION ........................................................................................................................................................ 32

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 32

TABLE 12: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 33

TABLE 13: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 33

4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 34

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 34

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36

4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1)..................... 36

4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 36

4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 36

TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 36

4.14 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 37

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37

4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38

TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39

5.0 ELECTRICAL CHARACTERISTICS...................................................................................................... 40

ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 40

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%).............................................. 40

DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40

AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 41

FIGURE 14. CLOCK TIMING............................................................................................................................................................. 42

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 43

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING................................................................................................................... 43

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 44

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 45

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 45

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 46

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 46

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 47

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 47

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 48

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................................................... 49

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)................................................................................ 50

PACKAGE DIMENSIONS (49 PIN SHRINK THIN BALL GRID ARRAY - 4 X 4mm) ................................................. 51

REVISION HISTORY...................................................................................................................................... 52

II


型号：	XR68M752IB49-F
厂家：	EXAR CORPORATION
描述：	暂无描述微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
文件：	总54页 (文件大小：1301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR68M752IB49-F [EXAR]

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