XRD5412AIP [EXAR]

5V, Low Power, Voltage Output Serial 8/10/12-Bit DAC Family; 5V ,低功耗,电压输出串行8月10日/ 12-位DAC系列
XRD5412AIP
型号: XRD5412AIP
厂家: EXAR CORPORATION    EXAR CORPORATION
描述:

5V, Low Power, Voltage Output Serial 8/10/12-Bit DAC Family
5V ,低功耗,电压输出串行8月10日/ 12-位DAC系列

转换器 光电二极管
文件: 总16页 (文件大小:929K)
中文:  中文翻译
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XRD5408/10/12  
5V, Low Power, Voltage Output  
Serial 8/10/12-Bit DAC Family  
May 2000-2  
FEATURES  
APPLICATIONS  
D 8/10/12-Bit Resolution  
D Digital Calibration  
D Operates from a Single 5V Supply  
D Buffered Voltage Output: 13µs Typical Settling Time  
D 240µW Total Power Consumption (typ)  
D Guaranteed Monotonic Over Temperature  
D Battery Operated Instruments  
D Remote Industrial Devices  
D Cellular Telephones  
D Motion Control  
D Flexible Output Range: 0V to V  
DD  
D 8 Lead SOIC and PDIP Package  
D Power On Reset  
D Serial Data Output for Daisy Chaining  
GENERAL DESCRIPTION  
The XRD5408/10/12 are low power, voltage output  
digital-to-analog converters (DAC) for +3V power supply  
operation. The parts draw only 70µA of quiescent current  
and are available in both an 8-lead PDIP and SOIC  
package.  
output allowing the user to daisy chain several of them  
together. The serial port will support both Microwiret,  
SPIt, and QSPIt standards.  
The outputs of the XRD5408/10/12 are set at a gain of +2.  
The output short circuit current is 7mA typical.  
The XRD5408/10/12 have a 3 wire serial port with an  
ORDERING INFORMATION  
Part No.  
Operating  
Package  
8 Lead 150 Mil JEDEC SOIC  
Temperature Range  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
XRD5408AID  
XRD5408AIP  
XRD5410AID  
XRD5410AIP  
XRD5412AID  
XRD5412AIP  
8 Lead 300 Mil PDIP  
8 Lead 150 Mil JEDEC SOIC  
8 Lead 300 Mil PDIP  
8 Lead 150 Mil JEDEC SOIC  
8 Lead 300 Mil PDIP  
Rev. 1.20  
E2000  
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017  
XRD5408/10/12  
BLOCK DIAGRAM  
V
REFIN  
n
2
Switch  
Matrix  
+
-
V
OUT  
R
R
AGND  
V
V
DD  
DD  
CS  
SCLK  
SDIN  
Shift Register  
DOUT  
Power On  
Reset  
Figure 1. Block Diagram  
PIN CONFIGURATION  
1
8
SDIN  
SCLK  
CS  
V
V
V
DD  
1
2
3
4
8
7
6
5
SDIN  
SCLK  
CS  
V
V
V
DD  
2
3
7
6
OUT  
REFIN  
OUT  
REFIN  
DOUT  
AGND  
4
5
DOUT  
AGND  
8 Lead SOIC (Jedec, 0.150”)  
8 Lead PDIP (0.300”)  
PIN DESCRIPTION  
Pin #  
Symbol  
SDIN  
Description  
1
2
3
4
5
6
7
8
Serial Data Input  
Serial Data Clock  
Chip Select (Active High)  
Serial Data Output  
Analog Ground  
SCLK  
CS  
DOUT  
AGND  
VREFIN  
VOUT  
VDD  
Voltage Reference Input  
DAC Output  
Supply Voltage  
Rev. 1.20  
2
XRD5408/10/12  
ELECTRICAL CHARACTERISTICS  
Test Conditions: V = 5V, GND= 0V, REFIN= 2.048V (External), R = 10k, C = 100pF, T = T  
to T  
,
MAX  
DD  
L
L
A
MIN  
Unless Otherwise Noted.  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Conditions  
Static Performance XRD5408  
N
Resolution  
8
Bits  
INL  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
0.25  
0.25  
3
0.5  
0.5  
8
LSB  
DNL  
LSB Guaranteed Monotonic  
VOS  
0
mV  
TCVOS  
PSRR  
Offset Tempco  
2
ppm/°C  
Offset-Error Power-Supply  
Rejection Ratio  
0.5  
1
mV  
4.5V ± VDD ± 5.5V  
GE  
Gain Error  
0.1  
10  
0.4  
%FS  
ppm/°C  
mV  
TCGE  
PSRR  
Gain-Error Tempco  
Power-Supply  
Rejection Ratio  
0.1  
1.25  
4.5V ± VDD ± 5.5V, Measured at  
FS  
Static Performance XRD5410  
N
Resolution  
10  
0
Bits  
INL  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
0.5  
0.25  
3
1
0.5  
8
LSB  
DNL  
LSB Guaranteed Monotonic  
VOS  
mV  
TCVOS  
PSRR  
Offset Tempco  
2
ppm/°C  
Offset-Error Power-Supply  
Rejection Ratio  
0.5  
1
mV  
4.5V ± VDD ± 5.5V  
GE  
Gain Error  
0.1  
10  
0.4  
%FS  
ppm/°C  
mV  
TCGE  
PSRR  
Gain-Error Tempco  
Power-Supply  
Rejection Ratio  
0.1  
1.25  
4.5V ± VDD ± 5.5V, Measured at  
FS  
Static Performance XRD5412  
N
Resolution  
12  
0
Bits  
LSB  
LSB  
LSB  
mV  
INL  
DNL  
Relative Accuracy  
Differential Nonlinearity  
2
4
-1  
0.5  
Guaranteed Monotonic  
+1.25  
8
VOS  
Offset Error  
3
2
TCVOS  
PSRR  
Offset Tempco  
ppm/°C  
mV  
Offset-Error Power-Supply  
Rejection Ratio  
0.5  
1
4.5V ± VDD ± 5.5V  
GE  
Gain Error  
0.1  
10  
0.4  
%FS  
ppm/°C  
mV  
TCGE  
PSRR  
Gain-Error Tempco  
Power-Supply  
Rejection Ratio  
0.1  
1.25  
4.5V ± VDD ± 5.5V, Measured at  
FS  
Rev. 1.20  
3
XRD5408/10/12  
ELECTRICAL CHARACTERISTICS (CONT’D)  
Test Conditions: V = 5V, GND= 0V, REFIN= 2.048V (External), R = 10k, C = 100pF, T = T  
to T  
,
MAX  
DD  
L
L
A
MIN  
Unless Otherwise Noted.  
Symbol Parameter  
Min.  
Typ.  
Max.  
Unit  
Conditions  
Voltage Output (VOUT) XRD5408/10/12  
V
--0.4  
VO  
VREG  
+ISC  
-ISC  
Output Voltage Range  
0
V
DD  
Output Load Regulation  
Short-Circuit Current, Sink  
Short-Circuit Current, Source  
2
13  
7
4
mV  
mA  
mA  
VOUT = 2V, RL=2kΩ  
VOUT = VDD  
VOUT = GND  
Voltage Reference Input (VREFIN) XRD5408/10/12  
Output Swing Limited, Not Code Dependent  
VREFIN  
RIN  
Voltage Range  
0
VDD  
V
Input Resistance  
Input Resistance Tempco  
Input Capacitance  
AC Feedthrough  
40  
65  
1500  
32  
kΩ  
TCRIN  
CIN  
ppm/°C  
pF  
40  
Not Code Dependent  
ACFT  
-80  
dB  
REFIN = 1kHz, 2Vp-p, SDIN=000h  
Digital Inputs (SDIN, SCLK, CS) XRD5408/10/12  
VIH  
VIL  
IIN  
Input High  
3.5  
V
V
Input Low  
1
Input Current  
Input Capacitance  
1  
µA  
pF  
VIN=0V or VDD  
CIN  
10  
Digital Output (DOUT) XRD5408/10/12  
VOH  
VOL  
Output High  
Output Low  
VDD-1  
0.13  
V
V
ISOURCE=4mA  
ISINK=4mA  
0.4  
15  
Dynamic Performance XRD5408/10/12  
SR  
ts  
Voltage-Output Slew Rate  
Voltage-Output Settling Time  
Digital Feedthrough  
0.21  
13  
1
V/µs  
µs  
TA=+25°C  
1/2LSB, VOUT=2V  
CS=VDD, SDIN=SCLK=100kHz  
DFT  
nV-s  
dB  
SINAD  
Signal-to-Noise Plus Distortion  
68  
VREFIN=1kHz, 2Vp-p F.S., SDIN=Full  
Scale, --3dB BW=250kHz  
Power Supply XRD5408/10/12  
VDD  
IDD  
Positive Supply Voltage  
Power Supply Current  
4.5  
5.5  
60  
V
35  
20  
µA  
All Inputs=0V or VDD, Output=No Load,  
IREF Not Included, VO=0V (Note 1  
)
Switching Characteristics XRD5408/10/12  
tCSS  
tCSH0  
tCSH1  
tCH  
CS Setup Time  
10  
5
ns  
ns  
ns  
ns  
ns  
SCLK Fall to CS Fall Hold Time  
SCLK Fall to CS Rise Hold TIme  
SCLK High Width  
0
20  
20  
35  
35  
tCL  
SCLK Low Width  
Notes:  
1 Total supply current consumption = IDD + IREF + (VO / 70K.)  
Rev. 1.20  
4
XRD5408/10/12  
ELECTRICAL CHARACTERISTICS (CONT’D)  
Test Conditions: V = 5V, GND= 0V, REFIN= 2.048V (External), R = 10k, C = 100pF, T = T  
to T  
,
MAX  
DD  
L
L
A
MIN  
Unless Otherwise Noted.  
Symbol  
tDS  
Parameter  
Min.  
10  
0
Typ.  
Max.  
Unit  
ns  
Conditions  
DIN Setup Time  
45  
tDH  
DIN Hold Time  
ns  
tDO  
DOUT Valid Propagation Delay  
CS High Pulse Width  
8
15  
ns  
CL= 50pF  
tCSW  
tCS1  
20  
10  
40  
20  
ns  
CS Rise to SCLK Rise Setup  
Time  
ns  
Specifications are subject to change without notice  
ABSOLUTE MAXIMUM RATINGS  
V
DD  
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +7V  
Package Power Dissipation Ratings (T = +70°C)  
A
PDIP (derate 9mW/°C above +70°C) . . . . 117mW  
SOIC (derate 6mW/°C above +70°C) . . . 155mW  
Operating Temperature Range . . . . . -40°C to + 85°C  
Storage Temperature Range . . . . . . -65°C to +165°C  
Lead Temperature (soldering, 10 sec) . . . . . . +300°C  
Digital Input Voltage to GND . . . . . . -0.3V, V +0.3V  
DD  
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, V +0.3V  
DD  
REFIN  
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V , GND  
OUT  
DD  
Continuous Current, Any Pin . . . . . . . . -20mA, +20mA  
Notes  
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a  
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating  
conditions for extended periods may affect device reliability.  
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps  
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short  
transients outside the supplies of less than 100mA for less than 100µs.  
Rev. 1.20  
5
XRD5408/10/12  
TIMING  
CS  
t
CSW  
t
CSH0  
t
t
t
t
CSH1  
CSS  
CH  
CL  
SCLK  
SDIN  
t
DH  
t
CS1  
t
DS  
t
D0  
DOUT  
Figure 2. Timing Diagram  
Input  
Output  
1111  
1000  
1000  
0111  
0000  
0000  
1111  
0001  
0000  
1111  
0001  
0000  
(0000)  
(0000)  
(0000)  
(0000)  
(0000)  
(0000)  
255  
+ 2 (VREFIN)  
256  
129  
256  
+ 2 (VREFIN)  
128  
256  
+ 2 (VREFIN)  
= + VREFIN  
127  
256  
+ 2 (VREFIN)  
1
256  
+ 2 (VREFIN)  
0V  
Note:  
Write 8-bit data words with four sub-LSB 0s because the DAC input latch  
is 12 bits wide.  
Table 1. Binary Code Table  
Rev. 1.20  
6
XRD5408/10/12  
THEORY OF OPERATION  
XRD5408/10/12 Description  
Fixed Gain +2 Voltage Output Amplifier  
A high open-loop gain operational amplifier buffers the  
resistor string with a stable, fixed gain of +2. The voltage  
output will settle within 13 s. The output is short circuit  
protected and can regulate an output load of 2V into 2k  
within 2mV at 25°C.  
The XRD5408/10/12 are micro-power, voltage output,  
serial daisy-chain programmable DACs operating from a  
single 5V power supply. The DACs are built on a 0.6  
micron CMOS process. The features of these DACs  
make it well suited for industrial control, low distortion  
audio, battery operated devices and cost sensitive  
designs that want to minimize pin count on ICs.  
While the reference input will accept a voltage from  
rail-to-rail, the linear input voltage range is constrained by  
the output swing of the fixed +2 closed-loop gain amplifier.  
Full scale output swing is achieved with an external  
reference of approximately 1/2 V  
voltage must be positive because the XRD5408/10/12  
DAC is non-inverting.  
.
The reference  
DD  
Resistor String DAC  
A resistor string architecture converts digital data using a  
switch matrix to an analog signal as shown in Figure 3.  
Serial Daisy-Chainable Digital Interface  
V
REFIN  
The three wire serial interface includes a DOUT to enable  
daisy-chaining of several DACs. This minimizes pin  
count necessary of digital asics or controllers to address  
multiple DACS. The serial interface is designed for  
CMOS logic levels. Timing is shown in Figure 2. The  
binary coding table (Table 1) shows the DAC transfer  
function.  
n
2
Switch  
Matrix  
+
-
V
OUT  
R
R
AGND  
V
V
DD  
DD  
CS  
SCLK  
SDIN  
Shift Register  
DOUT  
A power on reset circuit forces the DAC to reset to all “0”s  
on power up.  
Power On  
Reset  
APPLICATION NOTES  
Serial Interface  
Figure 3. XRD5408/10/12 DAC Architecture  
The resistor string architecture provides a non-inverted  
output voltage (V  
) of the reference input (V  
) for  
The XRD5408/10/12 family has a three wire serial  
interface that is compatible with Microwiret, SPIt and  
QSPIt standards. Typical configurations are shown in  
Figure 4 and Figure 5. Maximum serial port clock rate is  
OUT  
REFIN  
single supply operation while maintaininga constant input  
resistance. Unlike inverted R-2R architectures the  
reference input resistance will remain constant  
independent of code. This greatly simplifies the analog  
driving source requirements for the reference voltage and  
minimizes distortion. Similarly input capacitance varies  
only approximately 4pF over all codes.  
limited by the minimum pulse width of t  
and t .  
CL  
CH  
Feedthrough noise from the serial port to the analog  
output (V ) is minimized by lowering the frequency of  
OUT  
the serial port and holding the digital edges to >5ns.  
Rev. 1.20  
7
XRD5408/10/12  
+5V  
MP5010  
1.25V  
V
REFIN  
SK  
SO  
I/O  
SCLK  
SDIN  
CS  
XRD5412  
Microwiret  
V
0-2.5V  
OUT  
Port  
GND  
V
DD  
+5V  
0.1µF  
Figure 4. Typical Microwiret Application Circuit  
+5V  
MP5010  
1.25V  
V
REFIN  
SK  
MOSI  
I/O  
SCLK  
SDIN  
CS  
XRD5410  
SPI t  
Port  
V
0-2.5V  
OUT  
GND  
V
DD  
+5V  
0.1µF  
Figure 5. Typical SPIt Application Circuit  
Rev. 1.20  
8
XRD5408/10/12  
DAC  
n
DOUT  
SDIN  
MSB  
X
X
X
X
Figure 6. Shift Register Format  
The DACs are programmedby a 16 bit word of serial data.  
The format of the serial input register is shown in Figure 6.  
The leading 4 bits are not used to update the DAC. If the  
DAC is not daisy-chained then only a 12 bit serial word is  
needed to program the DAC. The next 8, 10 or 12 bits  
after the 4 leading bits are data bits. The XRD5408’s first  
8 bits are valid data and the trailing 4 bits must be set to 0.  
Figure 7 demonstrates the 16 bit digital word for the 8,  
10,12 bit DACs.  
AC Feedthrough (DAC Code = 0)  
FT  
AC Feedthrough from V  
to V  
is minimized with  
REFIN  
OUT  
low impedance grounding as shown in Figure 7. If the  
DAC data is set to all “0”s then V is a function of the  
OUT  
divider between the DAC string impedance and ground  
impedance. See the Power Supply and Grounding  
section for recommendations.  
feedthrough for a 1kHz 2Vpp signal with code = 0 is  
-80dB.  
The typical AC  
Leading  
Unused  
Bits  
Trailing  
“0”  
Bits  
Data Bits  
MSB LSB  
V
REFIN  
Part  
XRD5408/10/12  
XXXX  
XXXX  
XXXX  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
None  
00  
XRD5412  
XRD5410  
XRD5408  
R
IN  
0000  
--  
+
Table 2. 16-Bit Digital Word Register for XRD5408,  
XRD5410, XRD5412.  
V
OUT  
GND  
SCLK shouldbe held low when CS transitions low. Data is  
clocked in on the rising edge of SCLK when CS is low.  
SDIN data is held in a 16 bit serial shift register. The DAC  
is updated with the data bits on the rising edge of CS.  
When CS is high data is not shifted into the  
XRD5408/10/12.  
RGND  
Analog GND  
Daisy-Chaining  
Figure 7. AC Feedthrough Equivalent  
FT  
The digital output port (DOUT) has a 4mA drive for greater  
fan-out capability when daisy-chaining. DOUT allows  
cascading of multiple DACs with the same serial data  
stream. The data at SDIN appears at DOUT after 16 clock  
Circuit, DAC Code =0  
Compatible with MAX515 & MAX539  
cycles plus one clock width (t ) and a propagation delay  
CH  
The XRD5408/10/12 family of DACs are functionally  
campatible with the MAX515 & MAX539 while providing  
significant improvements. The XRD5408/10/12 DACs  
have lower power, faster serial ports, and a constant  
reference impedance to minimize the reference driving  
requirements and maximize system linearity. The DOUT  
(t ). DOUT remains in the state of the last data bit when  
DO  
CS is high. DOUT changes on the falling edge of SCLK  
when CS is low.  
Any number of DACs can be connected in this way by  
connecting DOUT of one DAC to SDIN of the next DAC.  
Rev. 1.20  
9
XRD5408/10/12  
port also has 4mA driving capability for greater fan-out  
when daisy-chaning to other digital inputs.  
Power Supply and Grounding  
Best parametric results are obtained by powering the  
XRD5408/10/12 family of DACs from an analog +5V  
power supply and analog ground. Digital power supplies  
and grounds should be separated or connected to the  
analog supplies and grounds only at the low-impedance  
power-supply source. This is best accomplished on a  
multilayer PCB with dedicated planes to ground and  
power. The DACs should be locally bypassed with both  
0.1 F and 2.2 F capacitors mounted as close as possible  
Monotonicity  
The XRD5408/10/12 family of DACs are monotonic over  
the entire temperature range.  
Micro-Power Operation  
The XRD5408 is the lowest power in their class. The  
quiescent current rating does not include the reference  
laddercurrent. Power can be saved whenthe part is not in  
use by setting the DAC code to all “0”s assuming the  
output load is referenced to ground. This minimizes the  
DAC output load current. An analog switch placed in  
series with the reference ladder can toggle the reference  
voltage off when the circuit is inactive to minimize power  
consumption.  
to the power supply pin (V ). Surface mount ceramic  
DD  
capacitors are recommended for low impedance, wide  
band power supply bypass. If only one +5V power supply  
is available for both analog and digital circuity isolate the  
analog power supply to the XRD5408/10/12 DAC with an  
inductor or ferrite bead before the local bypass  
capacitors.  
PERFORMANCE CHARACTERISTICS  
0.4  
0.2  
0
--0.2  
0
64  
128  
192  
255  
CODE  
Figure 8. XRD5408 INL  
0.35  
0.2  
0.0  
--0.1  
0
64  
128  
192  
255  
CODE  
Figure 9. XRD5408 DNL  
Rev. 1.20  
10  
XRD5408/10/12  
0
1mA/div  
10  
0
0
5
0.5V/div  
(V)  
5
V
OUT  
Figure 10. Output Source Current  
vs. Output Voltage  
--15  
1.5mA/div  
0
0.1V/div  
1
V
(V)  
OUT  
Figure 11. Output Sink Current  
vs. Output Voltage  
--14  
2mA/div  
0
7
0.1V/div  
0
V
(V)  
OUT  
Figure 12. Output Sink and Source Cur-  
rent vs. Output Volatge  
Rev. 1.20  
11  
XRD5408/10/12  
V
OUT  
CS  
Figure 13. Voltage Output Settling Time (t ),  
s
V
DD  
= 5V, V  
= 1V, No Load  
REFIN  
40  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
-40  
-20  
0
20  
Temp (°C)  
40  
60  
80  
100  
Figure 14. I vs. Temperature  
DD  
Rev. 1.20  
12  
XRD5408/10/12  
8
7
6
5
4
3
2
1
0
-1  
-2  
10  
100  
1000  
Frequency (KHz)  
Figure 15. Closed Loop Gain vs. Frequency  
0
-20  
-40  
-60  
-80  
-100  
-120  
10  
100  
1000  
Frequency (KHz)  
Figure 16. Closed Loop Phase vs. Frequency  
Microwiret is a trademark of National Semiconductor Corproation.  
SPIt and QSPIt are trademarks of Motorola Corporation.  
Rev. 1.20  
13  
XRD5408/10/12  
8 LEAD SMALL OUTLINE  
(150 MIL JEDEC SOIC)  
Rev. 1.00  
D
8
5
H
4
C
A
1
A
Seating  
Plane  
α
e
B
L
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
0.053  
0.004  
0.013  
0.007  
0.189  
0.150  
0.069  
0.010  
0.020  
0.010  
0.197  
0.157  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
A
B
1
C
D
E
e
0.050 BSC  
1.27 BSC  
H
L
0.228  
0.244  
0.050  
5.80  
0.40  
6.20  
1.27  
0.016  
α
0°  
8°  
0°  
8°  
Note: The control dimension is the millimeter column  
Rev. 1.20  
14  
XRD5408/10/12  
8 LEAD PLASTIC DUAL-IN-LINE  
(300 MIL PDIP)  
Rev. 2.00  
5
4
8
1
E
D
e
A
2
A
L
Seating  
Plane  
C
A
1
α
e
A
B
B
B
1
e
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
0.145  
0.015  
0.115  
0.014  
0.030  
0.008  
0.348  
0.300  
0.240  
0.210  
0.070  
0.195  
0.024  
0.070  
0.014  
0.430  
0.325  
0.280  
3.68  
0.38  
2.92  
0.36  
0.76  
0.20  
8.84  
7.62  
6.10  
5.33  
1.78  
4.95  
0.56  
1.78  
0.38  
10.92  
8.26  
7.11  
A
A
B
B
1
2
1
C
D
E
E
e
1
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
e
A
e
B
L
0.310  
0.430  
0.160  
7.87  
10.92  
4.06  
0.115  
2.92  
α
0°  
15°  
0°  
15°  
Note: The control dimension is the inch column  
Rev. 1.20  
15  
XRD5408/10/12  
NOTICE  
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-  
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-  
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are  
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary  
depending upon a user’s specific application. While the information in this publication has been carefully checked;  
no responsibility, however, is assumed for inaccuracies.  
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or  
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly  
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation  
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the  
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-  
stances.  
All trademarks and registered trademarks are property of their respective owners.  
Copyright 2000 EXAR Corporation  
Datasheet May 2000  
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.  
Rev. 1.20  
16  

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