XRD9855 [EXAR]
CCD Image Digitizers with CDS, PGA and 10-Bit A/D; 与CDS ， PGA和10位A / D转换的CCD图像数字化
| 型号： | XRD9855 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
| 文件： | 总35页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRD9855/9856
XRD98L55/98L56
CCD Image Digitizers with
CDS, PGA and 10-Bit A/D
July 2001
FEATURES
l 3-State Digital Outputs
l 10-Bit Resolution ADC
l ESD Protection to Over 2000V
l 18 - 27MHz Maximum Sampling Rate
l CorrelatedDoubleSampling(CDS)
l Programmable Gain from 6dB to 38dB (PGA)
l DigitallyControlledAnalogOffset-Calibration
l CCD Black Level Offset Compensation at Frame
Rate
APPLICATIONS
l DigitalVideoCamcorders
l Digital Still Cameras
l PC Video Teleconferencing
l DigitalCopiers
l CDS Clocks Sample Rising Edge or Falling Edge
l Single 5V or 3V Power Supply
l Infrared Image Digitizers
l CCD/CISImagerInterface
l CCTV/SecurityCamera
l 2D Bar Code Readers
l IndustrialCameras
l Low Power for Battery Applications:
XRD9855/56:
250/300mW @ V DD = 5.0V
XRD98L55/L56: 120/150mW @ VDD = 3.0V
l 50mA-Typ Current in Stand By Mode
GENERALDESCRIPTION
The XRD9855/XRD9856 are complete CCD Image
Digitizers for digital cameras. The products include a
highbandwidthdifferentialCorrelatedDoubleSampler
(CDS), 8-bit digitally Programmable Gain Amplifier
(PGA), 10-bit Analog-to-Digital Converter (ADC) and
digital controlled black level auto-calibration circuitry.
The PGA is digitally controlled with 8-bit resolution on
a linear dB scale, resulting in a gain range of 6dB to
38dB with 0.125dB per LSB of the gain code.
ThePGAandblacklevelauto-calibrationarecontrolled
through a simple 3-wire serial interface. The timing
circuitry is designed to enable users to select a wide
variety of available CCD and image sensors for their
applications.
TheCorrelatedDoubleSampler(CDS)subtractsthe
CCD output signal black level from the video level.
Commonmodesignalnoiseandpowersupplynoiseare
rejectedbythedifferentialCDSinputstage.CDSinputs
aredesigned to be used eitherdifferential orsingle-
ended.
TheXRD9855/XRD9856hasdirectaccesstothePGA
output and ADC input through the pin TESTVIN.
TheXRD9855/XRD9856arepackagedin48-leadsur-
face mount TQFP to reduce space and weight, and
suitable for hand-held and portable applications.
Theautocalibrationcircuitcompensatesforanyinter-
naloffsetoftheXRD9855/XRD9856aswellasblack
leveloffsetfrom theCCD.
ORDERINGINFORMATION
Operating
Maximum
Part No.
Package
Temperature Range PowerSupply Sampling Rate
XRD9855AIV
48 Lead TQFP (7 x 7 x 1.4 mm)
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
5.0V
3.0V
5.0V
3.0V
18 MSPS
18 MSPS
27 MSPS
27 MSPS
XRD98L55AIV 48 Lead TQFP (7 x 7 x 1.4 mm)
XRD9856AIV 48 Lead TQFP (7 x 7 x 1.4 mm)
XRD98L56AIV 48 Lead TQFP (7 x 7 x 1.4 mm)
Rev. 1.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRD9855/9856
XRD98L55/98L56
TESTVIN
VDD
VRBO
VRB
VRT
VRTO
VDD
GND
DVDD
In_Pos
In_Neg
ADC
Reg
DB[9:0]
PGA
CDS
DGND
SHD
SHP
Timing
Generator
RSTCCD
CLAMP
CLK_POL
SYNC
OVER
UNDER
Offset
Calibration
SCLK
SDI
Serial Port
Registers
LOAD
GND
STBY1
STBY2
RESET
EnableCal
OE
Figure 1. XRD9855/XRD9856 Simplified Block Diagram
Rev. 1.01
2
XRD9855/9856
XRD98L55/98L56
PINCONFIGURATION
36
25
24
37
SCLK
CLAMP
RESET
SHD
SHP
RSTCCD
GND
CLK_POL
STBY2
STBY1
Test
GND
VDD
EnableCal
VDD
OE
SYNC
UNDER
DB0
OVER
DB1
NC
DB9
DB8
48
13
1
12
48 Lead TQFP (7 x 7 x 1.0 mm)
PIN DESCRIPTION – 48 pin TQFP
Pin #
1
Symbol
NC
Description
No Connect.
2
NC
No Connect.
3
DB2
DB3
DB4
DGND
DVDD
DB5
DB6
DB7
NC
ADC Output. DB0 is the LSB, DB9 is the MSB.
ADC Output.
4
5
ADC Output.
6
DigitalOutputGround.
7
Digital Output Power Supply. Must be less than or equal to VDD.
8
ADC Output.
ADC Output.
ADC Output.
No Connect.
No Connect.
ADC Output.
ADC Output. MSB
9
10
11
12
13
14
15
NC
DB8
DB9
OVER
Over Range Output Bit. OVER goes high to indicate the ADC input voltage is
greater than VRT
.
Rev. 1.01
3
XRD9855/9856
XRD98L55/98L56
PIN DESCRIPTION – 48 pin TQFP (CONT’D)
Pin #
Symbol
Description
16
OE
Digital Output Enable (Three-State Control). Pull OE low to enable output
drivers. Pull OE high to put output drivers in high impedance state.
17
18
19
20
21
22
23
24
25
26
VDD
EnableCal
GND
Analog Power Supply.
Calibration Enable. Automatic offset calibration control.
AnalogGround.
TESTVIN
STBY1
STBY2
RESET
SCLK
ADC Test Input & PGA Test Output.
Standby Control 1. Pull low to put chip in power down mode.
Standby Control 2. Short to STBY1 pin if not using TESTVIN pin.
Chip Reset. Pull high to reset all internal registers.
Shift Clock. Shift register latches SDI data on rising edges of SCLK.
No Connect.
NC
LOAD
Data Load. Rising edge loads data from shift register to internal register. Load
must be low to enable shift register.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
SDI
VRT
Serial Data Input.
Top ADC Reference. Voltage at VRT sets full-scale of ADC.
Internal Bias for VRT. Short VRT to VRTO to use internal reference voltage.
Analog Power Supply.
VRTO
VDD
In_Neg
In_Pos
GND
CDS Inverting Input. Connect via capacitor to CCD video output.
CDS Non-inverting Input. Connect via capacitor to CCD supply.
AnalogGround.
VRBO
VRB
Internal Bias for VRB. Short VRB to VRB0 to use internal reference voltage.
Bottom ADC Reference. Voltage at VRB sets zero scale of the ADC.
No Connect.
NC
CLAMP
SHD
CDS DC Restore Clamp. Clamps In_Pos & In_Neg to internal bias voltage.
CDS Clock. Controls sampling of the pixel video level.
CDS Clock. Controls sampling of the pixel black level.
CCD Reset Pulse Disconnect. Used to decouple CDS during the reset pulse.
AnalogGround.
SHP
RSTCCD
GND
CLK_POL
VDD
Clock Polarity. Controls the polarity of SHP, SHD & CLAMP.
Analog Power Supply.
SYNC
UNDER
Digital output for Exar test purposes only. No connect.
Under Range Output Bit. UNDER goes high to indicate the ADC input voltage
is less than VRB
.
46
47
48
DBO
DB1
NC
ADC Output. LSB
ADC Output.
No Connect.
Rev. 1.01
4
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD9855andXRD9856
Unlessotherwisespecified: DV
= V = 5.0V, Pixel Rate = 18MSPS, V = 3.8V, V = 0.5V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
CDS Performance
CDSVIN
BW
Input Range
200 800 mVPP Pixel (Black Level - Video Level)
Small Signal Bandwidth (-3dB)
Slew Rate
60
40
MHz
V/µs
dB
SR
400mV Step Input
FT
Feed–through (Hold Mode)
-60
PGA Parameters
AVMIN
AVMAX
PGA n
Minimum Gain
3.5
5
37
8
6.5
dB
dB
Maximum Gain
Resolution
35.5
38.5
bits
Transfer function is linear steps in dB
(1LSB = 0.125dB)
GE
Gain Error
5
% FS
At maximum or minimum gain
setting
ADC Parameters (Measured Through TESTVIN)
ADC n
fs
Resolution
10
27
bits
MSPS
LSB
Max Sample Rate
Differential Non-Linearity
DNL
-1 +0.75 1.2
Up to 18MHz sample rate
(XRD9855)
DNL27
Differential Non-Linearity
-1
+1.3 2.0
LSB
Up to 27MHz sample rate
(XRD9856)
EZS
EFS
VIN
Zero Scale Error
Full Scale Error
DC Input Range
-50
50
4
mV
% FS
V
Measured relative to VRB
GND
VDD
VIN of the ADC can swing from GND
to VDD. Input range is limited by
the output swing of the PGA
VRT
VRB
Top Reference Voltage
1.5
0.3
3.8
0.5 VDD-1
3.3 VDD
VDD
V
V
V
VRT >VRB
VRT >VRB
Bottom Reference Voltage
DVREF
RL
Differential Reference Voltage 1.0
Ladder Resistance
280 400 520 Ohms
VRB = VDD
( )
VRB
Self Bias VRB
Self Bias VRT
0.4
3.5
0.5
3.8
0.6
4.1
V
V
VRB connected to VRBO
VRT connected to VRTO
10
VRT = VDD
( )
VRT
1.30
Rev. 1.01
5
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD9855and XRD9856(CONT'D)
Unless otherwise specified: DV = V = 5.0V, Pixel Rate = 18MSPS, V = 3.8V, V = 0.5V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
System Specifications
DNLS
System DNL
1.0
1.0
LSB
LSB
LSB
XRD9855 up to 18 MSPS
XRD9856 up to 27 MSPS
DNLS27
INLSMIN
System DNL 27 MSPS
INL @ Minimum Gain
INL error is dominated by CDS/PGA
linearity.
INLSMAX
INL @ Maximum Gain
LSB
mV
INL error is dominated by CDS/PGA
linearity.
VOS MINAV
Offset (Input Referred) @
Minimum Gain
5
1
Offset is defined as the input pixel
value-0.5 LSB required to cause the
ADC output to switch from “Zero
scale” to “Zero scale + 1LSB”.
Offset is measured after calibration.
Zero scale is the code in the offset
register.
VOS MAXAV Offset (Input Referred) @
Maximum Gain
mV
Offset depends on PGA gain code.
en
en
Input Referred Noise @
Maximum Gain
0.2
1.1
mVrms Noise depends upon gain setting of
the PGA.
MAXAV
MINAV
Input Referred Noise @
Minimum Gain
mVrms Noise depends upon gain setting of
the PGA.
DigitalInputs
VIH
Digital Input High Voltage
Digital Input Low Voltage
DC Leakage Current
Input Capacitance
2.0
V
V
VIL
0.7
IL
5
5
mA
Input Between GND and VDD.
CIN
pF
Digital Outputs
VOH
VOL
IOZ
Digital Output High Voltage
Digital Output Low Voltage
High-Z Leakage
DVDD-0.5
-10
V
V
While sourcing 2mA.
While sinking 2mA.
0.5
10
mA
OE=1 or STBY1= STBY2 = 0.
Output between GND & DVDD.
Rev. 1.01
6
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD9855and XRD9856(CONT'D)
Unless otherwise specified: DV = V = 5.0V, Pixel Rate = 18MSPS, V = 3.8V, V = 0.5V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
Digital I/O Timing
TDL
TPW1
TPW2
TPIX
TBK
Data Valid Delay
Pulse Width of SHD
20
25
ns
ns
ns
ns
ns
10
10
37
Pulse Width of SHD
Pixel Period
56
6
Sample Black Aperture Delay
Sample Video Aperture Delay
RSTCCD Switch Delay
VDD = 4.5V to 5.5V,
Temperature -40°C to 85°C range
VDD = 4.5V to 5.5V,
TVD
5
ns
ns
Temperature -40°C to 85°C range
VDD = 4.5V to 5.5V,
TRST
0
4
4
Temperature -40°C to 85°C range
TSC
TSET
Shift Clock Period
Shift Register Setup Time
Pipeline Delay
50
10
100
ns
ns
Latency
Power Supplies
VDD
cycles
Analog Supply Voltage
Digital Output Supply Voltage
Supply Current
4.5
2.7
5.0
5.0
50
55
50
5.5
5.5
75
V
DVDD
V
DVDD < VDD Always
IDD
mA
mA
mA
DVDD = VDD = 5.0V (XRD9855)
FS = 27MHz (XRD9856)
STBY1 = 0 and STBY2 = 0
IDD27
Supply Current @ 27MHz
Power Down Supply Current
85
IDDPD
100
Rev. 1.01
7
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD98L55and XRD98L56
Unless otherwise specified: DV = V = 2.7V, Pixel Rate = 18MSPS, V = 2.07V, V = 0.27V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
CDS Performance
CDSVIN
BW
Input Range
200 800 mVPP Pixel (Black Level - Video Level)
Small Signal Bandwidth (-3dB)
Slew Rate
60
40
MHz
V/µs
dB
SR
400mV Step Input
FT
Feed-through (Hold Mode)
-60
PGA Parameters
AVMIN
AVMAX
PGA n
Minimum Gain
3.5
5
37
8
6.5
dB
dB
Maximum Gain
Resolution
36.5
38.5
bits
Transfer function is linear steps in dB
(1LSB = 0.125dB)
GE
Gain Error
5
% FS
At maximum or minimum gain
setting
ADC Parameters (Measured Through TESTVIN)
ADC n
fs
Resolution
10
27
bits
MSPS
LSB
Max Sample Rate
Differential Non-Linearity
DNL
-1 +0.75 1.2
Up to 18MHz sample rate
(XRD98L55)
DNL27
Differential Non-Linearity
-1
+1.3 2.0
LSB
Up to 27MHz sample rate
(XRD98L56)
EZS
EFS
VIN
Zero Scale Error
Full Scale Error
DC Input Range
-50
50
4
mV
% FS
V
Measured relative to VRB
GND
VDD
VIN of the ADC can swing from GND to
V
DD. Input range is limited by
the output swing of the PGA
VRT
VRB
Top Reference Voltage
1.2
0.2
2.07 VDD
0.27 VDD-1
V
V
V
VRT >VRB
Bottom Reference Voltage
VRT >VRB
DVREF
RL
Differential Reference Voltage 1.0
Ladder Resistance
1.8
VDD
280 400 520 Ohms
VRB = VDD
( )
VRB
Self Bias VRB
Self Bias VRT
0.20 0.30 0.40
V
V
VRB connected to VRBO
10
VRT = VDD
( )
VRT
2.0
2.3
2.6
VRT connected to VRTO. TPW2
1.30
Rev. 1.01
8
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD98L55and XRD98L56(CONT'D)
Unless otherwise specified: DV = V = 2.7V, Pixel Rate = 18MSPS, V = 2.7V, V = 0.27V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
System Specifications
DNLS
System DNL
1.0
1.5
2
LSB
LSB
LSB
XRD98L55 up to 18 MSPS
XRD98L56 up to 27 MSPS
DNLS27
INLSMIN
System DNL 27 MSPS
INL @ Minimum Gain
INL error is dominated by CDS/PGA
linearity.
INLSMAX
INL @ Maximum Gain
2
5
LSB
mV
INL error is dominated by CDS/PGA
linearity.
VOS MINAV
Offset (Input Referred) @
Minimum Gain
Offset is defined as the input pixel
value -0.5 LSB required to cause the
ADC output to switch from “Zero
scale” to “Zero scale + 1LSB”.
Offset is measured after
calibration.
VOS MAXAV Offset (Input Referred) @
Maximum Gain
1
mV
Zero scale is the code in the offset
register.
Offset depends on PGA gain code.
en
en
Input Referred Noise @
Maximum Gain
0.2
0.7
mVrms Noise depends upon gain setting of
the PGA.
MAXAV
MINAV
Input Referred Noise @
Minimum Gain
mVrms Noise depends upon gain setting of
the PGA.
DigitalInputs
VIH
Digital Input High Voltage
Digital Input Low Voltage
DC Leakage Current
Input Capacitance
1.5
V
V
VIL
0.7
IL
5
5
mA
Input Between GND and VDD.
CIN
pF
Digital Outputs
VOH
VOL
IOZ
Digital Output High Voltage
Digital Output Low Voltage
High–Z Leakage
DV -0.5
V
V
While sourcing 2mA.
While sinking 2mA.
DD
0.5
10
-10
mA
OE=1 or STBY1= STBY2 = 0.
Output between GND & DVDD.
Rev. 1.01
9
XRD9855/9856
XRD98L55/98L56
DCELECTRICALCHARACTERISTICS–XRD98L55andXRD98L56(CONT'D)
Unless otherwise specified: DV = V = 2.7V, Pixel Rate = 18MSPS, V = 2.07V, V = 0.27V
DD
DD
RT
RB
Symbol
Parameter
Min. Typ. Max. Unit
Conditions
Digital I/O Timing
TDL
TPW1
TPW2
TPIX
TBK
Data Valid Delay
Pulse Width of SHD
28
35
ns
ns
ns
ns
ns
10
10
37
Pulse Width of SHD
Pixel Period
56
7
Sample Black Aperture Delay
Sample Video Aperture Delay
RSTCCD Switch Delay
VDD = 2.7V to 3.6V,
Temperature -40°C to 85°C range
VDD = 2.7V to 3.6V,
TVD
6
ns
ns
Temperature -40°C to 85°C range
VDD = 2.7V to 3.6V,
TRST
0
5
4
Temperature -40°C to 85°C range
TSC
TSET
Shift Clock Period
Shift Register Setup Time
Pipeline Delay
50
10
100
ns
ns
Latency
Power Supplies
VDD
cycles
Analog Supply Voltage
Digital Output Supply Voltage
Supply Current
2.7
2.7
3.0
3.0
40
45
50
3.6
3.6
55
V
DVDD
V
DVDD < VDD Always
IDD
mA
mA
mA
DVDD = VDD = 3.0 V (XRD9855)
FS = 27MHz (XRD9856)
STBY1 = 0 and STBY2 = 0
IDD27
Supply Current @ 27MHz
Power Down Supply Current
65
IDDPD
100
1, 2, 3
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)
LeadTemperature(Soldering10seconds)
MaximumJunctionTemperature
300°C
150°C
V
to GND
+7.0V
DD
V
V
& V
V
V
V
V
+0.5 to GND -0.5V
+0.5 to GND -0.5V
+0.5 to GND -0.5V
+0.5 to GND -0.5V
-65°Cto150°C
RT
RB
DD
DD
DD
DD
Package Power Dissipation Ratings (T = +70°C)
A
IN
TQFP
ESD
θ
= 54°C/W
JA
All Inputs
2000V
All Outputs
StorageTemperature
Notes:
1
Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode
clamps (HP5082–2835) from input pin to the supplies. All inputs have protection diodes which will protect the
device from short transients outside the supplies of less than 100mA for less than 100µs.
VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
2
3
Rev. 1.01
10
XRD9855/9856
XRD98L55/98L56
SYSTEM DESCRIPTION
Correlated Double Sample/Hold (CDS) &
Programmable Gain Amplifier (PGA); Gain [7:0]
During the black reference phase of each pixel the
SDRK switches are turned on, shorting the PGA1
The function of the CDS block, shown in Figure 2, is to
sense the voltage difference between the black level
and video level for each pixel. The CDS and PGA are
fully differential. The PGA output is converted to a
single ended signal, and then fed to the ADC. IN_POS
(CDS non-inverting input) should be connected, via a
capacitor, to the CCD "Common" voltage. This is
typicallytheCCDReferenceoutputorground. IN_NEG
(CDS inverting input) should be connected, via a ca-
pacitor, to the CCD output signal.
inputs to V . The sampling edge of SHP turns off the
DD
SDRK switches, sampling the black reference voltage
on capacitors C1 & C2.
DuringthevideophaseofeachpixeltheSPIXswitches
are turned on. The difference between the pixel refer-
ence level and video level is transmitted through ca-
pacitors C1 & C2 and converted to a fully differential
signalbythedifferentialamplifierPGA1. Thesampling
edge of SHD turns off the SPIX switches, sampling the
pixel value on capacitors C3 & C4.
CDS
PGA
VDD
Gain
Register
External
Coupling
Capacitors
SDRK
SPIX
RSTCCD
CCD
Supply
In_Pos
C1
C2
+
to
ADC
PGA1
-
PGA2
BUF
In_Neg
CCD
Signal
C3
C4
CLAMP
Offset
Calibration
VBIAS~0.8
ADC
Code
Enable Cal
Figure 2. Block Diagram of the CDS & PGA
Rev. 1.01
11
XRD9855/9856
XRD98L55/98L56
CCD
RSTCCD
SHP
SHD
(Internal Signals)
SDRK
SPIX
PGA1
Output
PGA2
Output
ADCLK
Hold
Track
Figure 3. Timing Diagram of the CDS Clocks
and Internal Signals, CLK_POL = 1, M2=0
PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x,
40
35
30
25
20
15
10
5
and 6.25x). The gain transitions occur at PGA gain
codes64dand128d(40h&80h). PGA2providesgain
from 6dB to 22dB (2x to 12.5x) with 0.125dB steps.
Figure 4 shows the measured PGA gain vs. Gain
Code. The combined PGA blocks provide a program-
mable gain range of 32dB. The minimum gain (code
00h) is 6dB. The maximum gain (code FFh) is 38dB.
The following equation can be used to compute PGA
gain from the gain code:
FS = 18MHz
VDD = 3.0V
VRT = 2.3V
VRB = 0.3V
TA = 25°C
0
code
æ
è
ö
÷
ø
0
64
128
192
256
Gain[dB] = 6 + 32 ´
ç
Gain Code
256
where code is between 0 and 255.
Figure 4. PGA Gain vs. Gain Code
Due to device mismatch the gain steps at codes 63-
64 and 127-128 may not be monotonic.
Rev. 1.01
12
XRD9855/9856
XRD98L55/98L56
Analog-to-DigitalConverter
AutomaticOffsetCalibration,Offset[7:0]
To get the maximum color resolution and dynamic
range, this part uses a digital controlled offset calibra-
tion system to compensate for external offset in the
CCDsignalaswellasinternaloffsetsoftheCDS, PGA
andADC.
The analog-to-digital converter is based upon a two-
step sub-ranging flash converter architecture with a
builtintrackandholdinputstage.TheADCconversion
iscontrolledbyaninternallygeneratedsignal, ADCLK
(see Figure 3). The ADC tracks the output of the CDS/
PGA while ADCLK is high and holds when ADCLK is
low. This allows maximum time for the CDS/PGA
output to settle to its final value before being sampled.
The conversion is then performed and the parallel
output is updated, after a 2.5 cycle pipeline delay, on
the rising edge of RSTCCD. The pipeline delay of the
entire XRD9855/XRD9856 is 4 clock cycles.
ThecalibrationisperformedeveryframewhentheCCD
outputs the Optical Black pixels, please see the
section on Frame Timing. The Calibration logic com-
pares the ADC output to the value stored in the serial
port offset register, and increments or decrements the
offset adjust DAC to make the ADC code equal to the
code in the offset register. The first adjustment re-
quires 8 pixels, then 6 pixels for subsequent adjust-
ments.Theoffsetregisteris8bitswide.TwoMSBsset
to00areaddedwhencomparedtothe10-bitADCcode.
After power-up the part may require up to 264 adjust-
ments to converge on the proper offset. These adjust-
ments can be made over many lines or frames. For
example, with 20 optical black pixels per line, the
calibration will make 3 adjustments per line, and initial
convergence will require at most 88 lines.
The internal reference values are set by a resistor
divider between V and GND. To enable the internal
DD
reference, connect V
to V and connect V
to
RTO
RT
RBO
V
. To maximize the performance of the XRD9855/
RB
XRD9856, the internal references should be used and
decoupled to GND. Although the internal references
have been set to maximize the performance of the
CDS/PGA channel, some applications may require
other reference values. To use external references,
drive the V
pin directly with the desired voltage.
RT
Connect V to V
. Do not drive V directly. The
RB
RBO
RB
ADCparalleloutputbusisequippedwithahighimped-
ance capability, controlled by OE. The outputs are
enabled when OE is low.
Graph 1. XRD9855 Typical Vdrk (CCD Offset)
Calibration Range @ 25°C
Rev. 1.01
13
XRD9855/9856
XRD98L55/98L56
IN_POS
10
CDS
PGA
ADC
DB[9:0]
XOE
IN_NEG
A
Up/Down
Counter
A-B
B
Offset Reg
State
Machine
EnableCal
ADCLOCK
Figure 5. Automatic Offset Calibration Loop
CCD
Input
Manual Global Offset, V [1:0]
DB[9:0]
CDS
+
PGA
ADC
In some systems the black level offset can be larger
than the Automatic Offset Calibration Range. The
XRD9855/XRD9856provideauserprogrammableglo-
bal offset adjustment which adds to the automatic
offset calibration. The global offset is applied at the
PGA input, so it’s input referred value does not change
withPGAgaincode,seeFigure6. Themagnitudeofthe
global offset is controlled by bits V[1:0] in the mode
register. (See Table 1.)
Automatic
Offset
Calibration
V[1:0]
Manual
Global Offset
Figure 6. Manual Global Offset & Automatic
OffsetCalibration
SerialInterface
V[1]
V[0]
Offset
A three wire serial interface, (LOAD, SCLK, and SDI),
is used to program the PGA gain register, the Calibra-
tion offset register, the Mode control register, and the
Aperture delay register. The shift register is 10 bits
long. The first two bits loaded are the address bits that
determine which of the four registers to update. The
following eight bits are the data bits (MSB first, LSB
last). When LOAD is high SCLK is internally disabled.
Since SCLK is gated by LOAD, SCLK can be a
continuouslyrunningclocksignal, butthiswillincrease
systemnoise. ToenabletheshiftregistertheLOADpin
must be pulled low. The data at SDI is strobed into the
shift register on the rising edges of SCLK. When the
LOADsignalgoeshighthedatabitswillbewrittentothe
register selected by the address bits (see Figure 7).
0
0
1
0
1
0
0mV
25mV (default)
50mV
1
1
75mV
Table 1. Manual Global
OffsetProgramming
Rev. 1.01
14
XRD9855/9856
XRD98L55/98L56
ADDRESS
DATA
(MSB)
Bit 7
(LSB)
Bit 0
SDI
AD1
AD0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Data Shifts on
Rising Edges
TSET=10ns min.
SCLK
LOAD
TSC=50ns min.
TSET=10ns min.
Load Internal Register
TSET=10ns min.
Figure 7. Serial Port Timing Diagram
Data
Address
Name AD1 AD0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Gain
0
0
1
1
0
1
0
1
Gain[7]
Gain[6]
Gain[5]
Gain[4]
Gain[3]
Gain[2]
Gain[1]
Gain[0]
Offset
Mode
Delay
Offset[7] Offset[6] Offset[5] Offset[4] Offset[3] Offset[2]
Offset[1] Offset[0]
V[1]
V[0]
M3
M2
Test3
Dd[1]
Test2
Dd[0]
M1
Reset
Dr[0]
Dp[2]
Dp[1]
Dp[0]
Dd[2]
Dr[1]
Table 2. Serial Interface Register Address Map
bit 7
bit 6
bit 5
bit 4
bit 3
Gain [7:0]
bit 2
bit 1
bit 0
0 0 0 0 0 0 0 0 - minimum gain (6dB) *
1 1 1 1 1 1 1 1 - maximum gain (38 dB)
Table 3. Gain Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Offset [7:0]
0 0 0 0 0 0 0 0 - do not use
0 0 0 0 0 0 0 1 - do not use
0 0 0 0 0 0 1 0 - minimum offset code
0 0 0 0 1 0 0 0 - default offset code, typical offset code 00100000
0 0 1 1 1 1 1 1 - maximum offset code
Table 4. Offset Register Bit Assignment
Rev. 1.01
15
XRD9855/9856
XRD98L55/98L56
bit 7
bit 6
bit 5
M3
bit 4
M2
bit 3
bit 2
Test2
bit 1
M1
bit 0
V[1:0]
Test3
Reset
0 0 - 0mV offset
0 1 - 25mV offset*
1 0 - 50mV offset
1 1 - 75mV offset
0 - Clamp only*
0 - RSTCCD* 0 - TestVin off*
0 - test off*
0 - auto detect* 0 - normal*
1 - Clamp & Cal 1 - no RSTCCD 1 - TestVin on 1 - factory test
1 - manual
1 - reset
Table 5. Mode Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Dp[2:0]
Dd[2:0]
Dr[1:0]
0 0 0 - SHP min delay *
1 1 1 - SHP max delay
0 0 0 - SHD min delay *
1 1 1 - SHD max delay
0 0 - RSTCCD min delay *
1 1 - RSTCCD max delay
Table 6. Delay Register Bit Assignment
Note:
* Indicates default value
SHP, SHD and RSTCCD Signals, M2 = 0
The SHP input to the XRD9855/XRD9856 determines
when the Black level of each pixel is sampled. For
CLK_POL=high timing mode, the black level is
sampled on the falling edge of SHP. For
CLK_POL=lowtimingmode,theblacklevelissampled
on the rising edge of SHP.
SHP (see Figure 8). This aperture delay is the time
from the sampling edge of SHP to the time the pixel
black level is actually sampled by the CDS. The
correct positioning of SHP will be 6-7 ns prior to where
theblacklevelhasadequatelysettled. Thisistypically
just before the CCD signal starts the transition to the
video level.
ThesamplingedgeofSHPshouldbepositionedsothat
it samples the pixel black level at a stable and repeat-
ablepoint. Theblacklevelshouldbesampledafterthe
CCD output has had time to settle from the reset pulse
andbeforetheoutputtransitionstothevideolevel(see
TheSHDinputtotheXRD9855/XRD9856 determines
when the Video level of each pixel is sampled. For
CLK_POL=high timing mode, the video level is
sampled on the falling edge of SHD. For
CLK_POL=lowtimingmode,thevideolevelissampled
on the rising edge of SHD.
Figure 8). Aperture delay T needs to be taken into
BK
consideration when positioning the sampling edge of
Rev. 1.01
16
XRD9855/9856
XRD98L55/98L56
ThesamplingedgeofSHDshouldbepositionedsothat
it samples the pixel video level at a stable and repeat-
ablepoint. Thevideolevelshouldbesampledafterthe
CCDoutputhassettledfromtheblacklevelandbefore
the output transitions to the reset pulse. Aperture
delay TVD needs to be taken into consideration when
positioning the sampling edge of SHD (see Figure
8). This aperture delay is the time from the sampling
edgeofSHDtothetimethepixelvideolevelisactually
sampled by the CDS. The correct positioning of SHD
will be 5-6 ns prior to where the video level has
adequately settled.
RSTCCDisintendedtooverlaptheresetpulseofeach
pixel. This is intended to eliminate the reset pulse
transients from getting into the CDS circuitry. Posi-
tioning of the RSTCCD signal so that it overlaps the
CCD signal reset pulse is not always practical due to
the timing generators being used or the frequency at
which the CCD is running. The most critical thing to
remember for RSTCCD is that it can not be high when
sampling either the black level or video level.
Reset Pulse
RSTCCD
Switch
Turn On
RSTCCD
Switch
Turn Off
T
BK
T
VD
CCD
Signal
Pixel Video Level
Sample Point
Pixel Black Level
Sample Point
T
RST
RSTCCD
SHP
SHD
Figure 8. CDS Timing Diagram
(CLK_POL = 1, M2 = 0)
Rev. 1.01
17
XRD9855/9856
XRD98L55/98L56
Pixel N
CCD
Signal
Sample Pixel
Video Level
Sample Pixel
Black Level
SHP
SHD
RSTCCD
TDL
Data N
DB[9:0]
(Output)
Data N-3
Data N-2
Data N-1
Data N-4
Figure 9. Conversion Timing Diagram Showing Pipeline Delay
(CLK_POL = 1, M2 = 0)
Rev. 1.01
18
XRD9855/9856
XRD98L55/98L56
CDS Clock Polarity
The CLK_POL pin is used to determine the polarity of
theCDSclocks(SHD, SHP, CLAMP). See Figures10
& 11, and Tables 7 & 8.
Event
Action
Event
Action
• RSTCCD
Disconnect CDS Inputs from Reset
Noise
• RSTCCD
Disconnect CDS Inputs from Reset
Noise
¯RSTCCD
Connect CDS Inputs and Track Black
Level
¯RSTCCD
Connect CDS Inputs and Track Black
Level
¯SHP
¯SHD
Hold Black Level and Track Video Level
Hold Video Level
• SHP
• SHD
Hold Black Level and Track Video Level
Hold Video Level
• SHP/SHD No Action
¯SHP/SHD No Action
Clamp High Activate DC Restore Clamp
Enable_Cal Activate Offset Calibration
High
Clamp Low Activate DC Restore Clamp
Enable_Cal Activate Offset Calibration
High
Table 7. Timing Event Description
Table Valid for CLK_POL=1, M2=0
Table 8. Timing Event Description
Table Valid for CLK_POL=0, M2=0
Line N
Line N+1
Active Video
pixels on
OB LINES
Active Video
pixels on
OB LINES
Dummy &
OB pixels
Vertical Shift
*
*
OB pixels
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded pixels.
Figure 10. CCD Line Timing, CLK_POL= 1, M2 = 0
Rev. 1.01
19
XRD9855/9856
XRD98L55/98L56
Line N+1
Dummy &
Line N
Vertical
Shift
Active Video Pixels
on Optical Black Lines
Active Video
OB*
Pixels
OB*
Pixels on OB line
Pixels
CCD
Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
CLK_POL=Low
* Note: OB = Optically Black or Shielded pixels.
Figure 11. CCD Line Timing with CLK_POL = 0, M2 = 0
No RSTCCD Pulse Timing, M2 = 1
To help simplify the timing required to drive the
XRD9855/XRD9856 we have included a timing mode
which does not require an active signal for RSTCCD.
To use this timing, bit M2 in the timing mode register
must be set high.
In this timing mode, RSTCCD must be kept low. No
changesarerequiredforthetimingoftheSHPandSHD
signals. The polarity of SHP, SHD and Clamp are still
controlled by the CLK_POL pin. The digital outputs
change on the sampling edge of SHD (see Figure 12).
This mode can be used with both the XRD4460 and
XRD9853 compatible timing as described in the Line
Timingsection.DataoutputDB[9:0}isdelayedasSHD
is delayed with the delay feature AD[1:0] = [1,1].
Pixel N
CCD Signal
1
RSTCCD
0
1
SHP
0
1
SHD
0
1
0
Data N-4
DB[9:0]
Data N-3
Data N-2
Data N-1
Data N
Figure 12. Timing for no RSTCCD Pulse,
M2=1 & CLK_POL=1, RSTCCD=0
Rev. 1.01
20
XRD9855/9856
XRD98L55/98L56
ProgrammableApertureDelays
Dp[2:0],Dd[2:0],Dr[1:0]
Dr[1]
Dr[0]
RSTCCD Aperture
Delay TRST (typ)
3ns (default)
7ns
To help fine tune the pixel timing, the XRD9855/
XRD9856 allows the system to adjust the aperture
0
0
1
1
0
1
0
1
delays associated with SHP (T ), SHD (T ) and
BK
VD
RSTCCD (T
) by programming the Aperture Delay
RST
11ns
serial port register. On power up these three aperture
delays are set to their minimum values.
15ns
Table 11. Programmable RSTCCD Delays
The SHP aperture delay is set by bits Dp[2:0]. Each
LSB adds approximately 2ns of delay. The SHD
aperture delay is set by bits Dd[2:0]. Each LSB adds
approximately 2ns of delay. The RSTCCD aperture
delay is set by bits Dr[1:0]. Each LSB adds approxi-
mately 4ns of delay.
Line Timing with Frame Calibration
At thebeginningand/orendofeveryCCDframethere
are a number of Optical black lines. The XRD9855/
XRD9856usestheoutputfromthesepixelsfortheDC
Restore Clamp and Black Level Offset Calibration
functions.ThesefunctionsarecontrolledbytheClamp
and/orEnableCalpins.
Dp[2]
Dp[1]
Dp[0]
SHP Aperture
Delay TBK (typ)
6ns (default)
8ns
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TheXRD9855/XRD9856isdesignedtobecompatible
with the Clamp Only timing of the XRD4460 or the
Clamp & EnableCal timing of the XRD9853. On power
up the chip will automatically detect which timing is
being used and make the necessary internal adjust-
ments. If EnableCal is high when Clamp is active, then
"Clamp Only" timing is selected (M3=0). If EnableCal
islowwhenClampisactive, then"Clamp&Cal"timing
isselected(M3=1).Ifrequired,theautomaticdetection
functioncanbedisabledthroughtheserialport,andthe
chip can be forced into one of the two timing modes by
programming mode register bits M3 & M1. Frame
clibration however, can only be used with m3=0.
10ns
12ns
14ns
16ns
18ns
20ns
Table 9. Programmable SHP Delays
Dd[2]
Dd[1]
Dd[0]
SHD Aperture
Delay TVD (typ)
5ns (default)
7ns
To maximize dynamic range in the dark areas of an
image the PGA black level output must be equal to
the bottom reference voltage of the ADC. This
ensures that a dark pixel input corresponds to a
desiredminimumcodeoutputfromtheXRD9855and
XRD9856.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9ns
11ns
13ns
The XRD9855 and XRD9856 use the Optically Black
(OB) pixels on a CCD array to calibrate for itself and
the CCD. Figure 13 shows the outline of a typical
CCD. The shaded region on the outside of the array
indicates the position of the optically black (OB)
pixels. The center region indicates the position of the
active pixels used for an image.
15ns
17ns
19ns
Table 10. Programmable SHD Delays
Rev. 1.01
21
XRD9855/9856
XRD98L55/98L56
Optically Black Pixels
(OB)
The XRD9855 and XRD9856 use a digital feedback
looptoachieveauto-calibration.TheoutputoftheADC
and a desired dark code programmed in the offset
register are compared during the OB pixel output from
theCCD. Therecommendedoffsetregistervalueis32
decimal. The difference determines whether the offset
adjustment DAC increments or decrements. This ad-
justs the offset of the PGA to achieve the desired ADC
output code for a dark pixel input.
Active Pixels
The first adjustment requires 8 cycles of SHP/SHD
clocks but every subsequent adjustment requires only
6 cycles: 1 cycle for CDS, 3 cycles for A/D conversion,
1cycleforlogic,and1cycleforDACupdate,seeFigure
14. When Enable_Cal pin is low, the offset calibration
logicisdisabled,andthecurrentstateoftheoffsetDAC
is held constant.
N+1
N
TheXRD9855 and XRD9856calibrationtimedepends
on the calibration method and the number of OB pixels
available. The time required to achieve calibration, in
frame calibration, depends on the number of OB pixels
present in each line.
Figure 13. Typical Outline of an Area Array
CCD.
The CCD has many OB pixels available for use in
calibration. Some are available at the start and end of
eachlinewhilewholelinesofOBpixelsareavailableat
the top and bottom of the array.
Using Frame calibration, calibration can be achieved
after several lines depending upon the number of OB
pixelsatthetoporbottomofanarray.Enable_Calmust
begeneratedbythetiminggeneratortoproperlyframe
the optical black lines.
The XRD9855 and XRD9856 take advantage of the
large number of OB pixels available at the top and
bottom of the CCD array to perform calibration before
any active pixels are processed.
OB Pixels
INNEG
RSTCCD
SHP
SHD
Enable_Cal
ADC Sample point
ADC Sample point
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
State
RESET
Enable
CDS
ADC
ADC
ADC Digcomp/ DAC
CDS
ADC
ADC
ADC Digcomp/ DAC
RESET
Cal on samples converts converts converts accum Update samples converts converts converts accum Update
settle input input
Figure 14. XRD9855 and XRD9856 Offset Calibration Timing, M3 = 1
Rev. 1.01
22
XRD9855/9856
XRD98L55/98L56
The timing needed for Frame Calibration Mode is
shown in Figure 16. In Frame Calibration Mode,
Enable_Cal needs to be active during the OB line
output from the CCD. Enable_Cal gates the XRD9855
and XRD9856’sauto-calibrationlogicandmustnever
behighwhenCLAMPisactive. Clampstillneedstobe
active once a line, either during start of line or end of
line OB pixels.
Frame calibration uses the OB lines available at the
startandendofthearray,seethedarkshadedregions
at the top and bottom of Figure 15, to perform its auto-
calibration.
The dark shaded regions of Figure 15 are the OB lines
at the start and end of the CCD array. Typically, these
OB lines are the largest blocks of OB pixels available
onthearray.UsingtheseareaswillallowtheXRD9855
and XRD9856toachievecalibrationbeforeanyactive
pixels are processed. This means that the XRD9855
and XRD9856 canachievecalibrationfortheveryfirst
frame if OB lines are used for calibration at the start of
Frame calibration is useful for applications where fast
calibration is needed. With frame calibration, the
XRD9855 and XRD9856 can achieve calibration be-
fore the first frame is started.
the array.
Active Pixels
Frame Calibration
(OB) Pixels
Optically Black
(OB) Pixels
N+1
N
Frame Calibration
(OB) Pixels
Figure 15. OB Lines Used For Frame Calibration on a Typical CCD Array
Line N
Line N+1
Dummy &
Active Video
pixels on
Active Video
pixels on
Vertical Shift
*
*
OB pixels
OB pixels
OB LINES
OB LINES
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded pixels.
Figure 16. Frame Calibration Mode Timing, CLK_POL= High
Rev. 1.01
23
XRD9855/9856
XRD98L55/98L56
Clamp Only Timing (XRD4460 compatible)
M1=1, M3=0, NOT RECOMMENDED
In this mode EnableCal is held high, and Clamp is
activated during the Optical Black pixels. While this
mode is available, it is not recommended for best
performance. This timing does not perform frame
calibration.
The Clamp signal is used to trigger a one-shot which
controlstheinternalDCrestoreswitchandthecalibra-
tion logic. The DC restore switch is turned on for two
pixels after Clamp is activated. Then the Calibration
logic is enabled and runs until Clamp is deactivated.
The chip can be forced into this timing mode by
programming the Mode control register bits M1=1 and
M3=0.
Line N
Line N+1
Dummy &
OB* Pixels
Signal
Pixels
Optical Black
Line
Vertical Shift
(Horizontal Clocking Off)
CCD Signal
1
EnableCal
0
Minimum 10 OB Pixels
1
Clamp
0
2 OB Pixels
Internal DC
Restore Switch
1
0
1
0
1
0
1
0
Internal Calibrate
RSTCCD
SHP
1
0
SHD
* Note: OB = Optically Black or Shielded pixels.
Figure 17. Clamp Only Line Timing
CLK_POL=1, EnableCal=1, M1=1, M3=0, M2=0
Clamp Only Mode
CCD
Input
CDS
PGA
ADC
DB[9:0]
DC Restore
Switch
Offset
Calibration
Bias
Control
Logic
Clk_Pol
Clamp
EnableCal
Figure 18. Clamp Only Mode (XRD4460 Compatible)
M1=1, M3=0
Rev. 1.01
24
XRD9855/9856
XRD98L55/98L56
Clamp&EnableCalTiming(XRD9853Compatible)
M1=1, M3=1
InthismodeEnableCalmustbeactiveduringthelarge
number of Optical Black pixels (usually at the end of
eachCCDlineoratthestartofaframe), Clampshould
be active during the Dummy pixels (usually at the
beginning of each CCD line).
The Clamp pin (polarity determined by CLK_POL)
controls only the DC restore switch at the CDS input.
EnableCal and Clamp must not be active at the same
time. Clamp must be used every line.
The chip can be forced into this timing mode by
programming the Mode control register bits M1=1 and
M3=1.
The EnableCal pin (always active high) directly con-
trols the calibration logic.
Line N
Line N+1
Signal
Pixels
Dummy &
OB Pixels
Signal
Pixels
OB* Pixels
Vertical Shift
(Horizontal Clocking Off)
CCD Signal
EnableCal
Min. 8 OB Pixels
Clamp
Min. 2 Pixels
RSTCCD
SHP
SHD
* Note: OB = Optically Black or Shielded Pixels.
Figure 19. Clamp & EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0
Rev. 1.01
25
XRD9855/9856
XRD98L55/98L56
Clamp & EnableCal Mode
CDS PGA
CCD
Input
ADC
DB[9:0]
DC Restore
switch
Offset
Calibration
bias
Clk_Pol
Clamp
EnableCal
Figure 20. Clamp & Enable Cal Mode (XRD9853 Compatible),
M1=1, M3=3
Stand-by Mode (Power Down)
The STBY1 and STBY2 pins are used to put the chip
into the Stand-by or Power down mode. In this mode
all sampling and conversion stops, The digital outputs
are put into the high impedance mode, and the power
supply current will drop to less than 50mA.
For most applications STBY1 and STBY2 should be
connectedtogetherandtreatedasasinglecontrolpin.
If an application uses the TestVin pin to access the
PGA output or the ADC input then STBY1 and STBY2
must be separately controlled, see the truth table
below.
CDS/
Clock Digital
STBY2 STBY1 PGA
ADC
Off
Inputs Outputs
0
1
0
1
0
0
1
1
Off
On
Off
On
Off
On
On
On
High-z
High-z
On
Off
On
On
On
Table 12. Stand-by Truth Table
Rev. 1.01
26
XRD9855/9856
XRD98L55/98L56
ChipReset
Register
Gain[7:0]
OS[7:0]
V[1:0]
M3
Default
Notes
The chip has an Internal Power-On-Reset function to
ensure all internal control registers start up in a known
state. Pulling the Reset pin high or writing a logic 1 to
the Mode Registers reset bit will also reset the chip to
the Power-up default conditions.
00000000 minimum gain
00001000 code 08 hex
01
0
25 mV offset
Clamp only
M2
0
RSTCCD required
Automatic timing detect On
Test modes off
M1
0
Test3
Test2
Reset
Dp[2:0]
Dd[2:0]
Dr[1:0]
0
0
Test modes off
0
reset bit will reset itself
minimum delay
minimum delay
minimum delay
000
000
00
Table 13. Reset Conditions
Using TestVin (Pin 20)
To use TestVin as an auxiliary ADC input force
STBY2=low and STBY1=high. This will disable the
CDS/PGA and leave the ADC operating. If M2=0, the
ADC clock is generated from RSTCCD and SHP (See
Figure 19). If M2=1, the ADC clock is generated from
SHP & SHD (See Figure 20).
The TestVin pin allows access to the input of the ADC,
or it can be used to monitor the CDS/PGA output. The
TestVin pin accesses the ADC input node through
switch S1 (see Figure 18). This switch is controlled by
Bit3 of the serial port Test register. When the TEST3
bit of the mode register is high, switch S1 is “ON” and
the TestVin pin can be used to access the ADC input/
PGA output. When the TEST3 bit of the mode register
is low, switch S1 is “OFF” and the TestVin pin is
disconnected from the ADC input/PGA output.
Rev. 1.01
27
XRD9855/9856
XRD98L55/98L56
TestVin
S1
CDS
PGA
ADC
Figure 21. Using TestVin to Access PGA Output & ADC Input
Mode Reg.
TestVin
AD1
1
1
AD0
0
0
V[1]
0
V[0]
0
M3
0
M2
1
Test3 Test2
M1
0
Reset
1
0
0
0
0
0
Normal
0
0
0
1
0
Table 14. Serial Port Data to Use TestVin
CCD
CCD
Signal
Signal
RSTCCD
RSTCCD
SHP
SHP
SHD
SHD
ADC Clock
(internal)
ADC Clock
Track
Track
Hold
Hold
(Internal)
ADC Data
ADC Data
Figure 23. ADC Clock Generation,
CLK_POL=1,M2=1
Figure 22. ADC Clock Generation,
CLK_POL=1,M2=0
Rev. 1.01
28
XRD9855/9856
XRD98L55/98L56
Digital Output Power Supplies
Power Supply Sequencing
There are no power supply sequencing issues if DV
The DV and DGND pins supply power to the digital
DD
DD
output drivers for pins DB[9:0], UNDER, and OVER.
andV oftheXRD9855/XRD9856aredrivenfromthe
DD
DV
is isolated from V
so it can be at a voltage
same supply.
separately, V
When DV
must come up at the same time or
and V
are driven
DD
DD
DD
DD
level less than or equal to V . This allows the digital
outputstointerfacewithadvanceddigitalASICsrequir-
ingreducedsupplyvoltages. ForexampleV canbe
5.0 or 3.3V, while DV is 2.5V.
DD
DD
before DV , and go down at the same time or after
DD
DV . If the power supply sequencing in this case is
DD
DD
notfollowed,thendamagemayoccurtotheproductdue
tocurrentflowthroughthesource-bodyjunctiondiodes
DD
between DV
and V . An external diode (5082-
DD
DD
2235) layed out close to the converter from DV to
DD
V
prevents damage from occurring when power is
DD
cycled incorrectly.
Note:V mustbegreaterthanorequaltoDV or the
DD
DD
source-body diodes will be forward based.
V
DD
DVDD
Source-Body
Junction Diode
Between DVDD
& VDD
Output
Register
Digital Output
Source-Body
Junction Diode
Between
DGND & GND
GND
DGND
Figure 24. DV & DGND Digital Output Power Supplies,
DD
V
> DV
DD
DD
Rev. 1.01
29
XRD9855/9856
XRD98L55/98L56
General Power Supply and Board Design Issues
Ingeneral,alltracesleadingtotheXRD9855/XRD9856
should be as short as possible to minimize signal
crosstalk and high frequency digital signals from feed-
ing into sensitive analog inputs. The two CCD inputs,
In_Pos and In_Neg, should be routed as fully differen-
tial signals and should be shielded and matched.
Efforts should be made to minimize the board leakage
currents on In_Pos and In_Neg since these nodes are
AC coupled from the CCD to the XRD9855/XRD9856.
Thedigitaloutputtracesshouldbeasshortaspossible
tominimizethecapacitiveloadingontheoutputdrivers
(see Figure25)
All of the GND pins, including DGND, should be con-
nected directly to the analog ground plane under the
XRD9855/XRD9856. The V ’s should be supplied
DD
from a low noise, well filtered regulator which derives
the power supply voltage from the CCD power supply.
All of the V
pins are analog power supplies and
DD
shouldbelocallydecoupledtothenearestGNDpinwith
a 0.1µF, high frequency capacitor. DV is the power
DD
supply for the digital outputs and should be locally
decoupled. DV should be connected to the same
DD
power supply network as the digital ASIC which re-
ceives data from the XRD9855/XRD9856.
12V
5V/3V
Regulator
5V/3V
Regulator
VDD
DVDD
DVDD
In_Neg
Digital
ASIC
CCD
DB[9:0]
DGND
In_Pos
GND
DGN
D
XRD9855/XRD9856
AGND
AGND
Figure 25. XRD9855/XRD9856 Power Supply Connections
ApplicationNote
If increasing the PGA Gain to code 128 (80h) or higher
causes a larger than expected offset increase in the
ADC digital output codes, the problem may be due to
the limited Automatic Offest Calibration range. This
problemmaybesolvedbyincreasingtheGlobalOffset
code, V[1:0], in the Mode Register. The default is
V[1:0] = 01 (binary). Try increasing to V[1:0] = 10, or
V[1:0] = 11.
For additional information on the XRD9855 feaures:
- Auto-detect
- EnableCal & Clamp Line Timing
- Clamp Only Line Timing
- Digital Clibration Loop
- Dark Voltage Calibration Range
Please see Application Notes XRDAN109,
XRDAN110,XRDAN112,XRDAN113and
XRDAN114.
Rev. 1.01
30
XRD9855/9856
XRD98L55/98L56
Serial
Interface
0.1m F
37
38
39
40
41
42
43
44
45
46
47
48
SCLK
24
23
CLAMP
SHD
From Clock
Signal
Generator
RESET
STBY2 22
SHP
VDD
STBY1
Test
21
20
19
RSTCCD
GND
GND
CLK_POL
VDD
0.1m F
from Clock Signal
Generator
XRD9855/XRD9856
EnableCal 18
VDD
0.1m F
VDD
VDD
OE
17
16
15
14
13
SYNC
UNDER
DB0
OVER
DB9
DB1
NC
DB8
Digital Data Bus
Figure 26. XRD9855/XRD9856 Application Schematic
CLK_POL=0
Rev. 1.01
31
XRD9855/9856
XRD98L55/98L56
2.4
2.2
A
V
V
= D
= 5.0V
VDD
VDD
= A
/1.3
VDD
RT
RB
2.0
= A
/10
VDD
30MHz
MODE = NON-RSTCCD
1.8
27MHz
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
25MHz
18MHz
12MHz
0
32
64
96
128
160
192
224
255
GAIN CODES
Figure 27. Input Reference Noise vs. PGA Gain Codes
Rev. 1.01
32
XRD9855/9856
XRD98L55/98L56
XRD98L55 INPUT REFERRED NOISE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
A
V
V
= D
= 3.0V
VDD
VDD
= A
/1.3
VDD
RT
RB
= A
/10
VDD
MODE = NON-RSTCCD
30MHz
25MHz
27MHz
18MHz
12MHz
255
0
32
64
96
128
160
192
224
GAIN CODES
Figure 28. XRD98L55 Input Referred Noise
Rev. 1.01
33
XRD9855/9856
XRD98L55/98L56
48 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
rev. 2.00
D
D1
36
25
37
24
D1
D
48
13
1
2
1
B
e
A2
C
A
Seating
Plane
a
A1
L
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.063
0.006
0.057
0.011
0.008
0.362
0.280
MIN
MAX
1.60
0.15
1.45
0.27
0.20
9.20
7.10
A
A1
A2
B
C
D
0.055
0.002
0.053
0.007
0.004
0.346
0.272
1.40
0.05
1.35
0.17
0.09
8.80
6.90
D1
e
0.020 BSC
0.50 BSC
L
a
0.018
0×
0.030
7×
0.45
0×
0.75
7×
Rev. 1.01
34
XRD9855/9856
XRD98L55/98L56
NOTICE
EXARCorporationreservestherighttomakechangestotheproductscontainedinthispublicationinordertoimprove
design,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuitsdescribed
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmayvarydepending
upon a user’s specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
ormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantly
affectitssafetyoreffectiveness. ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright2001 EXARCorporation
Datasheet July 2001
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.01
35
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