XRK32510 [EXAR]
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS; 10个时钟输出3.3V锁相环时钟驱动器
| 型号： | XRK32510 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS |
| 文件： | 总7页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
OCTOBER 2005
REV. 1.0.1
FEATURES
GENERAL DESCRIPTION
• Spread Spectrum Clock Compatible
• Operating frequency range: 25MHz to 175MHz
• Low noise
• Low jitter internal PLL
• No external RC filter components required
The XRK32510 is a high performance, low jitter, low
skew clock driver. The XRK32510 uses phase-lock
loop (PLL) tecnology to synthesize the CLK_IN signal
into 10 output signals (QA), synchronized in both
phase and frequency. XRK32510 features low skew,
low jitter and 50% duty cycle making it a perfect fit in
dual in line memory module (DIMM) board clocking,
PC133 SDRAM designs and other server
applications.
• Meets or exceeds DPC133 registered DIMM
specification 1.1
• Output Enable (OE) pin can be used to disable the
The 10 outputs can be disabled using the Output
Enable (OE) pin.
CLCK_OUT pins
• Operating supply of 3.3V VDD
• Plastic 24 Pin TSSOP package
By connecting the Feedback Output (FB_OUT) signal
to the Feedback Input (FB_IN) signal, the
propagation delay from CLK_IN to the 10 buffered
Outputs is nearly zero.
FIGURE 1. BLOCK DIAGRAM OF THE XRK32510
FB_OUT
QA0
QA1
QA2
QA3
CLK_IN
FB_IN
0
Ref
QA4
PLL
1
QA5
QA6
QA7
QA8
QA9
AVDD
OE
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK32510CG
24 Pin TSSOP
0°C to +70°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK32510
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3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REV. 1.0.1
FIGURE 2. PIN OUT OF THE XRK32510
AGND
VDD
QA0
QA1
QA2
GND
GND
QA3
QA4
1
2
3
4
5
6
7
8
9
24 CLK_IN
23 AVDD
22 VDD
21 QA9
20 QA8
19 GND
18 GND
17 QA7
16 QA6
15 QA5
14 VDD
13 FB_IN
VDD 10
OE 11
FB_OUT 12
2
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XRK32510
REV. 1.0.1
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
PIN DESCRIPTIONS
PIN #
PIN NAME
TYPE
PIN DESCRIPTION
1
AGND
****
****
Analog Ground
2
VDD
VDD
VDD
3.3V Power Supply
10
14
11
OE
INPUT
Output Enable:
"High" = Normal operation, Clock outputs (QA[0:9]) enabled
"Low" = Clock outputs (QA[0:9]) disabled
12
13
FB_OUT
FB_IN
OUTPUT
Feedback Output:
When this pin is connected to FB_IN, the propagation delay from
CLK_IN to any of the 10 QA pins will be nearly zero.
INPUT
Feedback Input
3
4
QA0
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
QA9
OUTPUT(S)
Buffered Clock Outputs:
These 10 outputs provide low-skew, low jitter, 50% duty cycle renditions
of CLK_IN
5
8
9
15
16
17
20
21
22
23
VDD
****
****
3.3V Digital Power Supply
3.3V Analog Supply:
AVDD
If this pin is connected to ground, the PLL is disabled and will be
bypassed and the CLK_IN signal will be connected directly to the output
buffers of the 10 QA pins.
24
CLK_IN
INPUT
Reference Clock Input
FUNCTIONAL OPERATION
INPUTS
OUTPUTS
PLL
CONDITION
OE
0
AVDD
QA[0:9]
FB_OUT
Driven
SOURCE
PLL
3.3V
3.3V
0
ON
ON
1
Driven
Driven
PLL
BUFFER MODE
0
1
0
0
0
Driven
Driven
CLK_IN
CLK_IN
OFF
OFF
Driven
3
XRK32510
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3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REV. 1.0.1
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage (AVDD)
Supply Voltage (VDD)
AVDD < (VDD +0.7V)
4.3V
Logic Inputs
GND- 0.5V to VDD + 0.5V
0°C to +70°C
Ambient Operating Temperature Range
Storage Temperature Range
-65°C to +150°C
ELECTRICAL CHARACTERISTICS -OUTPUT
TA = 0 - 70°C, VDD = AVDD = 3.3V +/- 10%, CL = 20 - 30pF, RL = 470Ω, (unless otherwise stated)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
RDSP
Output Impedance
36
Ω
VO = VDD/2
VO = VDD/2
RDSN
VOH
VOL
Output Impedance
Output High Voltage
Output Low Voltage
32
3.0
0.2
-33
-48
28
Ω
2.4
V
IOH = -8mA
IOL = 8mA
-13.6
-22
VOH = 2.4V
IOH
Output High Current
Output Low Current
mA
mA
VOH = 2.0V
19
13
VOL = 0.8V
IOL
19
VOL =0.55V
Rise Time1
Fall Time1
Duty Cycle1
Tr
Tf
Dt
0.5
0.5
45
0.8
0.9
50
2.1
2.7
55
ns
ns
%
VOH = 2.0V, VOL = 0.8V
VOL = 0.8V, VOH = 2.0V
VT = 1.5V, CL = 30pF
28.7
25
100
75
@66 - 100MHz, loaded outputs
@133MHz, loaded outputs
10,000 cycles, CL = 30 pF
Cycle to Cycle Jitter1
Tcyc-cyc
ps
Absolute Jitter1
Skew1
TjABS
Tsk
57
ps
ps
ps
ps
ns
29
150
150
50
VT = 1.5V (Window) Output to Output
VT = VDD/2, CLK_IN to FB_IN
Phase Error1
Phase Error Jitter1
Tpe
-150
-50
Tpej
DR1
35
VT = VDD/2, CLK_IN to FB_IN, Delay Jitter
VT = 1.5V, PLL Disabled (AVDD = 0)
Delay Input to
Output1
3.5
3.7
NOTE:
1. Guaranteed by design, not 100% tested in production
4
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XRK32510
REV. 1.0.1
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
ELECTRICAL CHARACTERISTICS - INPUT AND SUPPLY
TA = 0 - 70°C, VDD= AVDD = 3.3V +/- 10% (unless otherwise stated)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
VIH
Input High Voltage
2
VDD +
0.3
V
VIL
Input Low Voltage
GND -
0.3
0.8
V
IIH
IIL
Input High Current
Input Low Current
Operating Current
Input Capacitance
Output Capacitance
0.1
19
140
4
100
50
µA
µA
mA
pF
VIN = VDD
VIN = 0V
IDD
CIN
CO
170
CL = 0pF, FIN = 66MHz
Logic Inputs
8
pF
Logic Outputs
5
XRK32510
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3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REV. 1.0.1
FIGURE 3. PACKAGE OUTLINE DRAWING
6
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XRK32510
REV. 1.0.1
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REVISIONS
REV. #
1.0.0
1.0.1
DATE
DESCRIPTION OF CHANGES
9/23/05
10/06/05
Initial issue.
Product ordering information: Remove "F" product numbers and Lead Free column.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet October 2005.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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