XRK39910CD-5 [EXAR]
3.3V LOW SKEW PLL CLOCK DRIVER; 3.3V低偏移PLL时钟驱动器
| 型号： | XRK39910CD-5 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 3.3V LOW SKEW PLL CLOCK DRIVER |
| 文件： | 总9页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
JULY 2006
REV. 1.0.0
FEATURES
FUNCTIONAL DESCRIPTION
• Eight zero delay outputs
The XRK39910 is a high fanout phase locked-loop
clock driver intended for high performance computing
and data-communications applications. It has eight
zero delay LVTTL outputs.
When the OE pin is held low, all the outputs are syn-
chronously enabled. However, if OE is held high, all
the outputs except Q2 and Q3 are synchronously dis-
abled.
Furthermore, when the PE is held high, all the outputs
are synchronized with the positive edge of the CLKIN.
When PE is held low, all the outputs are synchronized
with the negative edge of CLKIN.
The FB_IN signal is compared with the input CLKIN
signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to
adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the
VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or
frequency variation) while still providing accurate
responses to input frequency changes.
• 12mA balanced drive outputs
• Output frequency: 15MHz to 85MHz
• <250ps of output to output skew
• Low Jitter: <200ps peak-to-peak
• 3 skew grades
• External feedback, internal loop filter
• Selectable
synchronization
• Synchronous output enable
positive
or
negative
edge
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• Available in SOIC package
FIGURE 2. PIN CONFIGURATION
1
24
CLKIN
VDDPLL
FSEL
nc
GND
Bypass
nc
2
23
22
21
20
19
18
17
16
15
14
13
3
4
OE
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
5
PE
VDD
6
VDD
Q0
Q7
Q0
XRK39910
7
Q6
H
M
L
Q1
Q2
Q3
Q4
Q5
Q6
Q7
8
Q1
GND
Q5
CLKIN
FB_IN
Ref
VCO
9
GND
Q2
PLL
10
11
12
Q4
Feedback
Q3
VDD
VDD
FB_IN
FSEL*
PE
Bypass*
OE
* Tri-Level inputs
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
REV.1.0.0
TABLE 1: ORDERING INFORMATION
PRODUCT NUMBER
XRK39910CD-2
XRK39910ID-2
XRK39910CD-5
XRK39910ID-5
XRK39910CD-7
XRK39910ID-7
ACCURACY
250ps
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
250ps
500ps
500ps
750ps
750ps
(1)
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL
DESCRIPTION
MAX
UNIT
Supply Voltage to Ground
-0.5 to +7
V
V
V
DC Input Voltage
-0.5 to VDD+0.5
I
CLKIN Input Voltage
-0.5 to +5.5
530
V
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
mW
°C
TSTG
-65 to +150
NOTE: (1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum-rated
conditions for extended periods may affect device reliability.
TABLE 3: CAPACITANCE (TA= +25°C, f= 1MHZ, VIN= 0V)
PARAMETER
DESCRIPTION
TYP
MAX
UNIT
CIN
Input Capacitance
5
7
pF
NOTE: Capacitance applies to all inputs except BYPASS and FSEL. It is characterized but not production tested
.
TABLE 4: PIN DESCRIPTIONS
PIN NAME
CLKIN
PIN NUMBER TYPE
DESCRIPTION
1
2
3
IN
Reference Clock Input
VDDPLL
PWR Power supply for phase locked loop and other internal circuitry.
(1,3)
IN
IN
Frequency range select:
FSEL = GND:15 to 35MHz
FSEL
FSEL = MID (or open): 25 to 60MHz
FSEL = VDD: 40 to 85MHz
PE
5
Selectable positive or negative edge control. When LOW/HIGH the outputs are
synchronized with the negative/positive edge of the reference clock.
VDD
6,12,14,20 PWR Power supply for output buffers.
2
XRK39910
REV. 1.0.0
3.3V LOW SKEW PLL CLOCK DRIVER
TABLE 4: PIN DESCRIPTIONS
PIN NAME
PIN NUMBER TYPE
DESCRIPTION
Q0 - Q7
7,8,10,11,
OUT Eight clock output.
15,16,18,19
GND
9,17,24
13
PWR Ground.
FB_IN
IN
IN
Feedback Input
(2)
21
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and
Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain
phase lock. Set OE LOW for normal operation.
OE
(1,2)
23
IN
When MID or HIGH, disable PLL (except for conditions of Note 2). CLKIN goes to
all outputs. Set LOW for normal operations.
BYPASS
NOTE:
1. Tri-Level Input
2. When BYPASS = MID and OE = HIGH, PLL remains active.
3. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the
outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
TABLE 5: RECOMMENDED OPERATING RANGE
XRK39910-2, -5, -7
(INDUSTRIAL)
XRK39910-2, -5, -7
(COMMERCIAL)
SYMBOL
DESCRIPTION
UNIT
MIN.
3
MAX.
3.6
MIN.
3
MAX.
3.6
VDD
TA
Power Supply Voltage
V
Ambient Operating Temperature
-40
+85
0
+70
°C
TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VIH
Input HIGH Voltage
Guranteed Logic HIGH
2
V
(CLKIN, FB_IN, OE, PE Inputs
Only)
VIL
Input LOW Voltage
Input HIGH Voltage
Guaranteed Logic LOW
0.8
V
(CLKIN, FB_IN, OE, PE Inputs
Only)
(1)
VIHH
VIMM
VILL
IIN
3-Level Inputs Only
(FSEL, BYPASS)
VDD-0.6
V
V
(1)
3-Level Inputs Only
(FSEL, BYPASS)
VDD/2-0.3 VDD/2+0.3
Input MID Voltage
(1)
3-Level Inputs Only
(FSEL, BYPASS)
0.6
+5
V
Input LOW Voltage
Input Leakage Current
VIN = VDD or GND
VDD = Max.
μA
(CLKIN, FB_IN Inputs Only)
3
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
REV.1.0.0
TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
+400
+200
+400
+100
+100
UNIT
I3
3-Level Input DC Current (BYPASS, FSEL) VIN = VDD
HIGH Level
MID Level
LOW Level
μA
VIN = VDD/2
VIN = GND
IPU
IPD
Input Pull-Up current (PE)
Input Pull-Down Current (OE)
Output HIGH Voltage
VDD = Max., VIN = GND
VDD= Max., VIN = VDD
VDD = Min., IOH = -12mA
VDD = Min., IOL = 12mA
μA
μA
V
VOH
VOL
2.4
Output LOW Voltage
0.55
V
NOTE: (1) These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected
inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL
may require an additional tLOCK time before all datasheet limits are achieved.
TABLE 7: POWER SUPPLY CHARACTERISTICS
(1)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
TEST CONDITIONS
IDDQ
Quiescent Power Supply Current
VDD=Max., BYPASS=MID, CLKIN=LOW
VDD/PE=LOW, OE=LOW,
8
25
mA
All outputs unloaded
(1)
ITOT
Total Power Supply Current
34
42
76
mA
VDD=3.3V, FREF=25MHz, CL=160pF
(1)
VDD=3.3V, FREF=33MHz, CL=160pF
(1)
VDD=3.3V, FREF=66MHz, CL=160pF
NOTE: (1) For eight outputs, each loaded with 20pF.
TABLE 8: INPUT TIMING REQUIREMENTS
(1)
SYMBOL
MIN.
MAX.
UNIT
DESCRIPTION
tR, tF
tPWC
DH
Maximum input rise and fall times, 0.8V to 2V
10
ns/V
ns
Input clock pulse, HIGH or LOW
Input duty cycle
3
10
15
90
85
%
Ref
Reference Clock Input
MHz
NOTE: (1) Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
4
XRK39910
REV. 1.0.0
3.3V LOW SKEW PLL CLOCK DRIVER
TABLE 9: SWITCHING CHARACTERISTICS OVER OPERATING RANGE
XRK39910-2 XRK39910-5
XRK39910-7
SYMBOL
PARAMETER
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
FREF CLKIN Frequency Range
FSEL = LOW
FSEL = MED
FSEL = HIGH
15
25
40
3
35
60
85
15
25
40
3
35
60
85
15
25
40
3
35
60
85
MHz
tRPWH CLKIN Pulse Width HIGH
tRPWL CLKIN Pulse Width LOW
ns
ns
ns
3
3
3
[1, 3, 4]
tSKEW
tDEV
0.1 0.25
0.75
0.25 0.5
1.25
0.3 0.75
1.65
Output Skew (All Outputs)
[1, 2, 5]
ns
ns
ns
ns
ns
ms
ps
Device-to-Device Skew
[1, 7]
tPD
-0.25
-1.2
0
0
1
1
0.25 -0.5
1.2 -1.2
1.2 0.15
1.2 0.15
0.5
0
0
1
1
0.5 -0.7
1.2 -1.2
0
0
0.7
1.2
CLKIN Input to FB_IN Propagation Delay
[1]
tODCV
tORISE
tOFALL
tLOCK
tJR
Output Duty Cycle Variation from 50%
[1]
0.15
0.15
1.5 0.15 1.5 2.5
1.5 0.15 1.5 2.5
Output Rise Time
[1]
Output Fall Time
[1,6]
0.5
0.5
PLL Lock Time
Cycle-to-Cycle Output Jit- RMS
25
25
25
[1]
ter
200
200
200
Peak-to-Peak
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outputs. See AC TEST LOADS.
4. For XRK39910-2 tSKEW is measured with CL = 0pF; for CL = 20pF, tSKEW = 0.35ns Max.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions.
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at CLKIN or FB_IN until tPD is within specified limits.
7. tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V ) of 1ns.
5
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
REV.1.0.0
FIGURE 3. AC TIMING DIAGRAM (PE= HIGH TIMING)
tREF
tRPWH
tRPWL
CLKIN
tODCV
tODCV
tPD
FB_IN
tJR
Qx output
tSKEW
tSKEW
Other Qx output
FIGURE 4. AC TIMING DIAGRAM (PE= LOW TIMING)
tREF
tRPWH
tRPWL
CLKIN
tODCV
tODCV
tPD
FB_IN
Qx output
tJR
tSKEW
tSKEW
Other Qx output
NOTE:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with
20pF and terminated with 75Ω to VDD/2.
tDEV: The output-to-output skew between any two devices operating under the same conditions (VDD, ambient
temperature, air flow, etc.).
tODCV: The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at CLKIN or FB_IN until tPD is within specified limits.
6
XRK39910
REV. 1.0.0
3.3V LOW SKEW PLL CLOCK DRIVER
FIGURE 5. AC TEST LOADS AND WAVEFORMS
VDD
150Ω
Output
150Ω
20pF
AC Test Loads
<1ns
<1ns
3.0V
2.0V
Vth = 1.5V
0.8V
0V
LVTTL Input Test Waveform
tORISE
tOFALL
2.0V
0.8V
LVTTL Output Waveform
7
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
REV.1.0.0
PACKAGE DIMENSIONS
24 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
rev. 1.00
D
24
13
E
H
1
12
C
A
Seating
Plane
α
e
B
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
2.35
0.10
0.33
0.23
15.20
7.40
MAX
2.65
0.30
0.51
0.32
15.60
7.60
A
0.093
0.004
0.013
0.009
0.598
0.291
0.104
0.012
0.020
0.013
0.614
0.299
A
1
B
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.394
0.016
0°
0.419
0.050
8°
10.00
0.40
0°
10.65
1.27
8°
α
8
XRK39910
REV. 1.0.0
3.3V LOW SKEW PLL CLOCK DRIVER
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
1.0.0
July 18, 2006
Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet July 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
9
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