XRP7720ILBTR-XXXX-F [EXAR]
Quad Output Universal Customizable PMIC with PFM;
| 型号： | XRP7720ILBTR-XXXX-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Quad Output Universal Customizable PMIC with PFM 集成电源管理电路 |
| 文件： | 总28页 (文件大小：1320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRP7720
Quad Output Universal Customizable PMIC with PFM
January 2014
Rev. 1.0.0
GENERAL DESCRIPTION
FEATURES
Pin Compatible to XRP7724
The XRP7720 is a quad output universal
customizable PMIC comprised of a quad
channel Digital Pulse Width Modulated (DPWM)
Step down (buck) controller and 5V LDO. A
wide 4.75V to 5.5V and 5.5V to 18V input
voltage dual range allows for single supply
operation from standard power rails. It is pin
compatible to the popular XRP7724 and
provides full flexibility during the development
phase while offering a cost effective option for
high volume production units.
SMBus Compliant I2C Interface available
on XRP7720ILB-DEV Only
Supported by PowerArchitect™ 5.1
XRP7720ILB-DEV Only
Quad Channel Step-down Controller
Digital PWM 105kHz-1.23MHz Operation
Individual Channel Frequency Selection
Patented digital PFM with Ultrasonic Mode
Integrated MOSFET Drivers
With integrated FET gate drivers, it can
operate from 105kHz to 1.23MHz with
Programmable 5 coefficient PID control
4.75V to 18V Input Voltage
independent
programmable
channel-to-channel
operating frequency, the
4.75V-5.5 and 5.5V-18V Input Range
0.6V to 5.5V Output voltage
XRP7720 reduces overall component count
and solution footprint while optimizing
conversion efficiencies.
A selectable digital
3 x 15V Capable PSIOs + 2 x GPIOs
Full Start/Stop Sequencing Support
Pulse Frequency Mode (DPFM) and low
operating current result in better than 80%
efficiency down to 10mA load provides support
for portable and Energy Star compliant
applications. Each XRP7720 output channel is
Built-in Thermal, Over-Current, UVLO
and Output Over-Voltage Protections
On Board 5V Standby LDO
7x7mm TQFN44 Package
individually
programmable
down
to
a
minimum 0.6V with a resolution of 2.5mV, and
configurable for precise soft start and soft stop
sequencing, including delay and ramp control.
APPLICATIONS
During development, the XRP7720ILB-DEV is
configured using PowerArchitectTM 5.1 (PA 5.1)
through an I2C interface, allowing for short
development of the power system and short
time to market for the entire system. Once
development is completed and volume
production is ready to commence, Exar will
assign a unique part suffix and deliver a
customized XRP7720.
Blade Servers
Micro Servers
Network Adapter Cards
Switches/Routers
Video Surveillance Systems
Built-in independent output over voltage, over
temperature, over-current and under voltage
lockout protections ensure safe operation
under abnormal operating conditions.
The XRP7720 is offered in a RoHS compliant,
“green”/halogen free 44-pin TQFN package.
Exar Corporation
48720 Kato Road, Fremont CA 94538, USA
www.exar.com
Tel. +1 510 668-7000 – Fax. +1 510 668-7001
XRP7720
Quad Output Universal Customizable PMIC with PFM
January 2014
Rev. 1.0.0
TYPICAL APPLICATION DIAGRAM
5V
+
VOUT1
+
1.5V
600kHz
LDO5
5V
+
VIN
VCC
LDO5
VOUT2
GH2
BST2
1.05V
V5EXT
5V (optional)
LX2
1.2MHz
+
GL2
DVDD(1.8V)
AVDD(1.8V)
GL_RTN2
VIN
EN
XRP7720
VOUT1
VOUT2
VOUT3
VOUT4
+
VOUT3
GH3
BST3
3.3V
LX4
+
300kHz
GL3
GL_RTN3
VCCD3-4
LDO5
VIN
+
VOUT4
5V
+
300kHz
Figure 1 XRP7720 Application Diagram
Exar Corporation
48720 Kato Road, Fremont CA 94538, USA
www.exar.com
Tel. +1 510 668-7000 – Fax. +1 510 668-7001
XRP7720
Quad Output Universal Customizable PMIC with PFM
FEATURES AND BENEFITS
PowerArchitect™ 5.1 Design and
Configuration Software
Programmable Power Benefits
Wizard quickly generates a base design
Calculates all configuration registers
Projects can be saved and recalled
Fully Configurable
Output set point
Feedback compensation
Frequency set point
Under voltage lock out
GPIOs can be configured easily and
intuitively
“Dashboard” Interface can be used for
real-time monitoring and debug (-DEV
ONLY)
Reduced Development Time with
XRP7720-DEV
Configurable and re-configurable for
different Vout, Iout, Cout, and Inductor
values
System Integration Capabilities
Single supply operation
No need to change external passives for a
5 GPIO pins with a wide range of
new output specification.
configurability
Fault reporting (including UVLO
Warn/Fault, OCP Warn/Fault, OVP,
Temperature, Soft-Start in progress,
Power Good, System Reset)
Higher integration and Reliability
Many external circuits used in the past
can be eliminated thereby significantly
improving reliability.
Allows a Logic Level interface with other
Pin Compatible to XRP7724
ICs or as logic inputs to other devices
Provides easy migration path to a full
featured programmable power
management system with dynamic
control and telemetry
Selectable switching frequency between
105kHz and 1.2MHz
Internal MOSFET Drivers
Internal FET drivers (4Ω/2Ω) per channel
Built-In Automatic Dead-time adjustment
30ns Rise and Fall times
4 Independent SMPS channels and
Standby LDO in a 7x7mm TQFN
© 2014 Exar Corporation Confidential
3/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
These are stress ratings only and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
Input Voltage Range VCC ...............................5.5V to 18V
Input Voltage Range VCC = LDO5 ................4.75V to 5.5V
VOUT1, 2, 3, 4 ......................................................5.5V
Junction Temperature Range....................-40°C to 125°C
JEDEC Thermal Resistance θJA ..........................30.2°C/W
VCCD, LDO5, GLx, VOUTx ..........................-0.3V to 7.0V
ENABLE, 5V_EXT.......................................-0.3V to 7.0V
GPIO0/1, SCL, SDA ............................................... 6.0V
PSIOs Inputs ......................................................... 18V
DVDD, AVDD ........................................................ 2.0V
VCC ....................................................................... 23V
LX#.............................................................-1V to 23V
BSTx, GHx....................................................VLXx + 6V
Storage Temperature.............................. -65°C to 150°C
Junction Temperature ..........................................150°C
Power Dissipation................................ Internally Limited
Lead Temperature (Soldering, 10 sec) ...................300°C
ESD Rating (HBM - Human Body Model).................... 2kV
ELECTRICAL SPECIFICATIONS
Specifications with standard type are for an Operating Junction Temperature of TJ = 25°C only; limits applying over the full
Operating Junction Temperature range are denoted by a “•”. Typical values represent the most likely parametric norm at TJ
= 25°C, and are provided for reference purposes only. Unless otherwise indicated, VCC = 5.5V to 18V, 5V EXT open.
QUIESCENT CURRENT
Parameter
Min.
Typ.
Max.
Units
Conditions
EN = 0V, VCC = 12V
µA
VCC Supply Current in SHUTDOWN
ENABLE Turn On Threshold
10
20
V
0.95
10
VCC = 12V Enable Rising
EN=5V
0.82
-10
uA
uA
ENABLE Pin Leakage Current
VCC Supply Current in STANDBY
EN=0V
all channels disabled
µA
440
600
GPIOs programmed as inputs
VCC =12V,EN = 5V
4 channels on set at 5V, VOUT forced to
5.1V, no load, non-switching, Ultra-sonic
off, VCC=12V, No I2C activity.
mA
mA
VCC Supply Current 4ch PFM
VCC Supply Current ON
4.0
18
All channels enabled, Fsw=600kHz, gate
drivers unloaded, No I2C activity.
© 2014 Exar Corporation
4/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
INPUT VOLTAGE RANGE AND UNDERVOLTAGE LOCKOUT
Parameter
Min.
Typ.
Max.
Units
Conditions
•
•
18
V
V
5.5
VCC Range
5.5
With VCC connected to LDO5
4.75
VOLTAGE FEEDBACK ACCURACY AND OUTPUT VOLTAGE SET POINT RESOLUTION
Parameter
Min.
Typ.
Max.
Units
Conditions
5
20
7.5
22.5
15
45
20
50
30
90
40
100
5.5
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
V
-5
-20
-7.5
-22.5
-15
-45
-20
-50
-30
-90
-40
-100
0.6
VOUT Regulation Accuracy
Low Output Range
0.6V to 1.6V
0.6 ≤ VOUT ≤ 1.6V
•
•
•
•
•
0.6 ≤ VOUT ≤ 1.6V
VCC=LDO5
PWM Operation
VOUT Regulation Accuracy
Mid Output Range
0.6V to 3.2V
0.6 ≤ VOUT ≤ 3.2V
0.6 ≤ VOUT ≤ 3.2V
VCC=LDO5
PWM Operation
VOUT Regulation Accuracy
High Output Range
0.6V to 5.5V
0.6 ≤ VOUT ≤ 5.5V
0.6 ≤ VOUT ≤ 4.2V
VCC=LDO5
PWM Operation
•
•
VOUT Regulation Range
2.5
5
10
Low Range
Mid Range
High Range
VOUT Set Point Resolution1
mV
kΩ
120
90
75
Low Range
Mid Range
High Range
VOUT Input Resistance
10
1
0.67
Low Range
Mid Range
High Range
VOUT Input Resistance in PFM
Operation
MΩ
mV
mV
157.5
315
630
Low Range
Mid Range
High Range
-155
-310
-620
Power Good and OVP Set Point
Range (from set point)
5
10
20
Low Range
Mid Range
High Range
-5
-10
-20
Power Good and OVP Set Point
Accuracy
Note 1: Fine Set Point Resolution not available in PFM
© 2014 Exar Corporation
5/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
FAULTS AND WARNINGS
Parameter
Min.
Typ.
Max.
Units
Conditions
Low Range (≤120mV)
-60mV applied
±1.25
3.75
10
5
mV
mV
mV
mV
mV
mV
mV
-3.75
-10
-5
•
•
Current Limit Accuracy
±2.5
High Range (≤280mV)
-150mV applied
+12.5
-12.5
1.25
2.5
Low Range (≤120mV)
High Range (≤280mV)
Low Range (≤120mV)
High Range (≤280mV)
Current Limit Set Point
Resolution
20
40
-120
-280
Current Limit Set Point
Range
VCC UVLO Set Point Range
18
V
4.6
VCC UVLO Set Point
Resolution
200
mV
VCC WARN and FAULT Set
Point Accuracy
400
mV
V
-400
4.4
VCC UVLO WARN (Note 2)
4.72
UVLO WARN set point 4.6V, VCC=LDO5
Over Temperature Set Point
Resolution
5
°C
°C
Over Temperature Set Point
Accuracy
10
-10
Note 2: This test is only performed when WARN is programmed to 4.6V.
LINEAR REGULATOR
Parameter
Min.
Typ.
Max.
Units
Conditions
5.5V ≤ VCC ≤ 18V
0mA < ILDO5OUT < 130mA, LDO3_3 Off
LDO5 Output Voltage
5.0
5.15
V
4.85
•
•
•
LDO5 Current Limit
125
150
mA
V
LDO5 Fault Set
VCC Rising
105
LDO5 UVLO
4.74
LDO5 PGOOD Hysteresis
LDO5 Bypass Switch Resistance
375
1.1
mV
Ω
VCC Falling
1.5
2.5
Bypass Switch Activation
Threshold
•
%
V5EXT Rising, % of threshold setting
V5EXT Falling
2.5
Bypass Switch Activation
Hysteresis
150
mV
ENABLE transition from logic low to
high. Once LDO5 in regulation above
limits apply.
Maximum total LDO loading
during ENABLE start-up
30
mA
© 2014 Exar Corporation
6/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
PWM GENERATORS AND OSCILLATOR
Parameter
Min.
Typ.
Max.
Units
Conditions
Steps defined in table
Switching Frequency (fsw)
Range
1230
5
kHz
%
105
fsw Accuracy
–5
GPIOS3
Parameter
Min.
Typ.
Max.
Units
Conditions
Input Pin Low Level
0.8
V
V
Input Pin High Level
Input Pin Leakage Current
Output Pin Low Level
Output Pin High Level
Output Pin High Level
2.0
1
µA
V
0.4
ISINK = 1mA
V
ISOURCE = 1mA
ISOURCE = 0mA
2.4
3.3
3.6
10
V
Output Pin High-Z leakage
Current (GPIO pins only)
µA
Maximum Sink Current
I/O Frequency
1
mA
Open Drain Mode
30
MHz
Note 3: 3.3V CMOS logic compatible, 5V tolerant.
PSIOS4
Parameter
Min.
Typ.
Max.
Units
Conditions
Input Pin Low Level
0.8
V
V
Input Pin High Level
Input Pin Leakage Current
Output Pin Low Level
2.0
1
µA
V
0.4
ISINK = 3mA
Open Drain. External pull-up resistor to
user supply
Output Pin High Level
15
V
Output Pin High-Z leakage
Current (PSIO pins only)
10
5
µA
I/O Frequency
MHz
Note 4: 3.3V/5.0V CMOS logic compatible, maximum rating of 15.0V
GATE DRIVERS
Parameter
GH, GL Rise Time
Min.
Typ.
Max.
Units
Conditions
17
11
ns
ns
At 10-90% of full scale, 1nF Cload
GH, GL Fall Time
GH, GL Pull-Up On-State Output
Resistance
4
2
5
Ω
Ω
GH, GL Pull-Down On-State
Output Resistance
2.5
GH, GL Pull-Down Resistance in
Off-Mode
50
9
kΩ
Ω
VCC = VCCD = 0V.
@ 10mA
Bootstrap diode forward
resistance
Minimum On Time
Minimum Off Time
50
ns
ns
1nF of gate capacitance
1nF of gate capacitance
125
© 2014 Exar Corporation
7/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
BLOCK DIAGRAM
BST1
Channel 1
GH1
LX1
Feedback
ADC
Digital
PID
Hybrid
DPWM
VOUT1
Gate
Driver
GL1
PreScaler
1/2/4
Dead
Time
GL_RTN1
VCC
VREF
DAC
Current
ADC
SS & PD
VCCD1-2
VOUT3
VOUT3
VOUT4
Channel 2
Channel 3
VCCD3-4
Channel 4
4uA
ENABLE
Internal
POR
GPIO 0-1
Vtj
GPIO
PSIO
NVM
Sequencing
Fault
Handling
OTP
UVLO
OCP
MUX
PSIO 0-2
SDA,SCL
VCC
PWR
Good
Configuration
Registers
LDO5
OVP
5V LDO
I2C
(-DEV Only)
LOGIC
CLOCK
Figure 2 XRP7720 Block Diagram
LDO BLOCK DIAGRAM
VCCD3-4 VCCD1-2
LDO5
DVDD
AVDD
Figure 3 XRP7720 LDO Block Diagram
8/28
© 2014 Exar Corporation
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
PIN ASSIGNMENT
N/C
1
2
33
32
31
30
29
28
27
26
25
24
23
GL_RTN2
GL2
AGND
N/C
3
LX2
AVDD
4
GH2
VOUT1
VOUT2
VOUT3
VOUT4
GPIO0
5
BST2
GL_RTN3
GL3
XRP7720
TQFN
7mm X 7mm
6
7
8
LX3
9
GH3
Exposed Pad: AGND
10
11
BST3
VCCD3-4
GPIO1
GND (SDA)
Figure 4 XRP7720 Pin Assignment (-DEV ONLY)
PIN DESCRIPTION
Name
Pin Number
Description
Input voltage. Place a decoupling capacitor close to the controller IC. This input is used
in UVLO fault generation.
41
VCC
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling
capacitor close to the controller IC.
16
DVDD
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail (for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch.
VCCD1-2
VCCD3-4
23,34
2
Analog ground pin. This is the small signal ground connection.
AGND
Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
39,33, 28,22
GL_RTN1-4
Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
38,32, 27,21
GL1-GL4
© 2014 Exar Corporation
9/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
Name
Pin Number
Description
Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
36,30, 25,19
GH1-GH4
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching
node at the junction between the two external power MOSFETs and the inductor. These
pins are also used to measure voltage drop across bottom MOSFETs in order to provide
output current information to the control engine.
37,31, 26,20
LX1-LX4
High side driver supply pin(s). Connect BST to the external capacitor as shown in the
Typical Application Circuit on page 2. The high side driver is connected between the
BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each
cycle.
35,29, 24,18
9,10
BST1-BST4
GPI0-GPIO1
These pins may be configured as inputs or outputs to implement custom flags, power
good signals, enable/disable controls and synchronization to an external clock.
Open drain, these pins may be used to control external power MOSFETs to switch loads
on and off, shedding the load for fine-grained power management. They may also be
configured as standard logic outputs or inputs just as any of the GPIOs can be
configured, but as open drains they will require an external pull-up when configured as
outputs.
13,14,15
PSIO0-PSIO2
11, 12
11,12
XRP7720ILB-XXXX-F. These pins should be tied to ground.
GND
XRP7720ILB-DEV-F Only.
SMBus/I2C serial interface communication pins for
communication to PowerArchitectTM 5.1 using XRP77XXEVB-XCM (Exar Configuration
Module). Accommodation should be made in the board layout to tie these pins to
ground for production.
SDA, SCL
Connect to the output of the corresponding power stage. The output is sampled at least
once every switching cycle
5,6,7,8
44
VOUT1-VOUT4
LDO5
Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of
the IC is in standby mode. This LDO is also used to power the internal Analog Blocks.
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,
registers configuration loaded, etc.). The pin must be held low for the XRP7720 to be
placed into shutdown.
40
17
43
4
ENABLE
DGND
V5EXT
AVDD
Digital ground pin. This is the logic ground connection, and should be connected to the
ground plane close to the PAD.
External 5V that can be provided. If one of the output channels is configured for 5V,
then this voltage can be fed back to this pin for reduced operating current of the chip
and improved efficiency.
Output of the internal 1.8V LDO. A decoupling capacitor should be placed between
AVDD and AGND close to the chip.
This is the die attach paddle, which is exposed on the bottom of the part. Connect
externally to the ground plane.
45
PAD
N/C
1,3,42
No Connect
ORDERING INFORMATION
Temperature
Packing
Quantity
Part Number
Marking
Package
Note 1
Range
XRP7720ILB
YYWW
Halogen Free
XRP7720ILB-DEV-F
Tray
-40°C≤TJ≤+125°C
Lot#
XRP7720ILB
YYWW
44-pin TQFN
2.5K/Tape &
Reel
Halogen Free
XRP7720ILBTR-XXXX-F*
-40°C≤TJ≤+125°C
Lot#
XRP7720EVB Power Board Only
XRP7720EVB-DEMO-1
XRP7720EVB Power Board, USB Stick, XRP77XXEVB-XCM, USB Cable, Ribbon Connector
XRP7720EVB-DEMO-1-KIT
“YY” = Year – “WW” = Work Week
*Minimum order requirements apply; please contact your Exar representative.
© 2014 Exar Corporation
10/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
TYPICAL PERFORMANCE CHARACTERISTICS
All data taken at VCC = 12V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from XRP7724EVB. See
XRP7724EVB-DEMO-1 Manual.
Figure 2 PWM to PFM Transition
Figure 1 PFM to PWM Transition
Figure 4 LDO5 Brown Out Recovery, No Load
Figure 3 PFM Zero Current Accuracy
Figure 5 0-6A Transient 300kHz
© 2014 Exar Corporation
11/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
Figure 6 Simultaneous Start-up
Figure 7 Sequential Start-up
Figure 8 Simultaneous Shut Down
Figure 9 Sequential Shut Down
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
Vcc
=25V
Rising
Vcc
=25V
Falling
Vcc=4.75
V Rising
Vcc
=4.75
V Falling
-40°C
25°C
85°C
125°C
Figure 10 Enable Threshold Over Temp
© 2014 Exar Corporation
12/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
circuitry. There is also a 1.8V linear regulator
which is for internal use only and should not
be used externally.
FUNCTIONAL OVERVIEW
The XRP7720 is a quad-output digital pulse
width modulation (DPWM) controller with
A key feature of the XRP7720 is its powerful
power management and time to market
integrated
gate
drivers
for
use
with
synchronous buck switching regulators. Each
output voltage can be programmed from 0.6V
to 5.5V without the need for an external
capabilities
through
the
use
of
the
XRP7720ILB-DEV. During development, all
four outputs are independently programmable
which provides full control of the delay, ramp,
and sequence during power up and power
voltage
divider.
The
wide
range
of
programmable DPWM switching frequency
(from 105 kHz to 1.2 MHz) enables the user to
optimize for efficiency or component sizes.
Since the digital regulation loop requires no
down.
Additionally, this programmability
allows control of the interaction of the outputs
and power down in the event of a fault,
including active ramp down of the output
voltages to remove an output voltage as
quickly as possible. The outputs may also be
defined and controlled as groups.
external
passive
components,
loop
performance is not compromised due to
external component variation or operating
condition.
The XRP7720 provides a number of critical
The
XRP7720ILB-XXXX-F provide two different
types of programmable memory. The
XRP7720ILB-DEV
and
standard
safety
features,
such
as
Over-Current
Protection (OCP), Over-Voltage Protection
(OVP), Over Temperature Protection (OTP)
plus input Under Voltage Lockout (UVLO). In
addition, a number of key health monitoring
features including warning level flags for the
safety functions and various Power Good
(PGOOD) functions which may be configured
to the GPIOs for hardware monitoring. The
above are all programmable during the
development phase through PA 5.1 when
using the XRP7720ILB-DEV.
XRP7720ILB-DEV has a rewritable Non-Volatile
Flash Memory (NVFM) that allows multiple re-
configurations
during
development.
In
production, the XRP7720ILB-XXXX-F is factory
programmed in a one-time programmable
memory.
The XRP7720 brings an extremely high level of
functionality
and
performance
to
a
programmable
power
system.
Ever
decreasing product budgets require the
designer to quickly make good
For hardware communication, the XRP7720
has two logic level General Purpose Input-
Output (GPIO) pins, three 15V, open drain,
Power System Input-Output (PSIO) pins, and
an ENABLE pin. Two pins are dedicated to the
SMBus data (SDA) and clock (SCL) which are
available in the XRP7720ILB-DEV but are
eliminated in the production version. If full
dynamic control and telemetry are desired in
the production system, the pin compatible
XRP7724 is available.
cost/performance tradeoffs to be truly
successful. By incorporating four switching
channels, an LDO, and internal gate drivers in
a single package, the XRP7720 allows for
extremely cost effective power system
designs. The key cost factor to consider in
cost tradeoffs is the flexibility of the
XRP7720ILB-DEV during systems reliability
testing. The programmable versatility of the
XRP7720ILB-DEV along with the lack of hard
wired and on board configuration components
allows for minor and major changes during
development to be made in circuit and on the
board, by simply reprogramming with PA 5.1.
In addition to providing four switching outputs,
the XRP7720 also provides a stand-by linear
regulator that produce 5V for a total of 5
customer usable supplies in a single device.
The 5V LDO is used for internal power and is
also optionally available to power external
© 2014 Exar Corporation
13/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
THEORY OF OPERATION
CHIP ARCHITECTURE
REGULATION LOOPS
Vin
(VCC)
Vdrive
(VCCD)x
AFE
Vref
DAC
Vin Feed
Forward
Fine
Adjust
GHx
GLx
LXx
Scalar
÷1,2,4
Error
Amp
AFE
ADC
Error
Register
Gate
Driver
VFB
(VOUTx)
PID
DPWM
Window
Comp.
Current
ADC
PFM/
Ultrasonic
PWM-
PFM Sel
Figure 11 XRP7720 Regulation Loops
Figure 11 shows a simplified functional block
diagram of the regulation loops for one output
channel of the XRP7720. There are 3 separate
parallel control loops; Pulse Width Modulation
(PWM), Pulse Frequency Modulation (PFM),
and Ultrasonic. Each of these loops is fed by
the Analog Front End (AFE) as shown at the
left of the diagram. The AFE consist of an
input voltage scalar, a programmable Voltage
Reference (Vref) DAC, Error Amplifier, and a
window comparator. Some of the function
blocks are common and shared by each
channel by means of a multiplexer.
range) the scalar gain is 1/2 and for voltages
greater than 3.2V (high range) the gain is 1/4.
This results in the low range having an output
voltage resolution of 12.5mV, mid range of
25mV and the high range having a resolution
of 50mV. The error amp has a gain of 4 and
compares the output voltage of the scalar to
Vref to create an error voltage on its output.
This is converted to a digital error term by the
AFE ADC which is stored in the error register.
The error register has a fine adjust function
that can be used to improve the output
voltage set point resolution by a factor of 5
resulting in a low range resolution of 2.5mV,
mid range resolution of 5mV and a high range
resolution of 10mV. The output of the error
register is then used by the Proportional
Integral Derivative (PID) controller to manage
the loop dynamics.
PWM Loop
The PWM loop operates in Voltage Control
Mode (VCM) with optional Vin feed forward
based on the voltage at the VCC pin. The
reference voltage (Vref) for the error amp is
created by a 0.15V to 1.6V DAC that has
12.5mV resolution. In order to get a 0.6V to
5.5V output voltage range an input scalar is
used to reduce feedback voltages for higher
output voltages to bring them within the 0.15V
to 1.6V control range. For output voltages up
to 1.6V (low range) the scalar has a gain of 1.
For output voltages from 1.6V to 3.2V (mid
The XRP7720 PID is a 17-bit five coefficient
control engine that calculates the correct duty
cycle under the various operating conditions
and feeds it to the Digital Pulse Width
Modulator (DPWM). Besides the normal
coefficients, the PID also uses the Vin voltage
to provide a feed forward function.
© 2014 Exar Corporation
14/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
The XRP7720 DPWM includes a special delay
high side FET is turned on, the inductor
current ramps up which charges up the output
capacitors and increasing their voltage. After
the completion of the high side and low side
on-times, the lower FET is turned off to inhibit
any inductor reverse current flow. The load
current then discharges the output capacitors
until the output voltage falls below Vref and
the normal comparator is activated this then
triggers the DPWM to start the next switching
cycle. The time from the end of the switching
cycle to the next trigger is referred to as the
dead zone.
timing loop that gives a timing resolution that
is 16 times the master oscillator frequency
(103MHz) for a timing resolution of 607ps for
both the driver pulse width and dead time
delays. The DWPM creates and drives the
Gate High (GH) and Gate Low (GL) signals.
The maximum and minimum on times and
dead time delays are programmable by
configuration resisters.
PFM mode loop
The XRP7724 has a PFM loop that can be
enabled to improve efficiency at light loads.
By reducing switching frequency and operating
in the discontinuous conduction mode (DCM),
both switching and I2R losses are minimized.
When PFM mode is initially entered the
switching duty cycle is the same that it was in
PWM mode. The result is the inductor ripple
current will remain the same as it was in PWM
mode. During operation the PFM duty cycle is
calculated based on the ratio of the output
voltage to VCC. This method ensures that the
output voltage ripple is well controlled and is
much lower than in other architectures which
use a “burst” methodology.
Figure 12 shows a functional diagram of the
PFM logic.
# Cycles Reg
Default = 20
A
CHx Fsw
COUNTER
A<B
Clk
PFM Current
Threshold Reg
Clear
A
B
If the output voltage ever goes outside the
high/low windows, PFM mode is exited and the
PWM loop is reactivated.
A<B
IADC
B
PWM MODE
PFM MODE
Q
Q
S
R
VOUT
Although the PFM mode does a good job in
improving efficiency at light load, at very light
loads the dead zone time can increase to the
point where the switching frequency can enter
the audio hearing range. When this happens
some components, like the output inductor
and ceramic capacitors, can emit audible
noise. The amplitude of the noise depends
mostly on the board design and on the
manufacturer and construction details of the
components. Proper selection of components
can reduce the sound to very low levels. In
general Ultrasonic Mode is not used unless
required as it reduces light load efficiency.
+
-
VREF HIGH
PFM EXIT
TRIGGER PULSE
-
+
VREF
-
+
VREF LOW
Figure 12 PFM Enter/Exit Functional Diagram
The PFM loop works in conjunction with the
PWM loop and is entered when the output
current falls below a programmed threshold
level for a programmed number of cycles.
When PFM mode is entered, the PWM loop is
disabled and instead, the scaled output
voltage is compared to Vref with a window
comparator. The window comparator has three
thresholds; normal (Vref), high (Vref +
%high) and low (Vref - %low). The %high and
%low values are programmable and track
Vref.
Ultrasonic Mode
Ultrasonic mode is an extension of PFM to
ensure that the switching frequency never
enters the audible range. When this mode is
entered, the switching frequency is set to
30kHz and the duty cycle of the upper and
lower FETs, which are fixed in PFM mode, are
decreased as required to keep the output
In PFM mode, the normal comparator is used
to regulate the output voltage. If the output
voltage falls below the Vref level, the
comparator is activated and triggers the
DPWM to start a switching cycle. When the
© 2014 Exar Corporation
15/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
voltage in regulation while maintaining the
30kHz switching frequency.
See ANP-32 “Practical Layout Guidelines for
PowerXR Designs”
Under extremely light or zero load currents,
the GH on time pulse width can decrease to its
minimum width. When this happens, the lower
FET on time is increased slightly to allow a
small amount of reverse inductor to flow back
into Vin to keep the output voltage in
regulation while maintaining the switching
frequency above the audio range.
LDOS
The XRP7720 has an internal Low Drop Out
(LDO) linear regulator that generates 5.0V
(LDO5) for both internal and external use.
Additionally it has a 1.8V regulator that
supplies power for the XRP7720 internal
circuits. Figure 3 shows a block diagram of the
linear power supplies. LDO5 is the main power
input to the device and is supplied by an
external 5.5V to 18V (VCC) supply. The output
of LDO5 should be bypassed by a good quality
capacitor connected between the pin and
ground close to the device. The 5V output is
used by the XRP7720 as a standby power
supply and is also used to power the 3.3V and
1.8V linear regulators inside the chip and can
also supply power to the 5V gate drivers. The
total output current that the 5V LDO can
provide is 100mA. The XRP7720 consumes
approximately 20mA and the rest can be used
INTERNAL DRIVERS
The internal high and low gate drivers use
totem pole FETs for high drive capability. They
are powered by two external 5V power pins
(VCCD1-2) and (VCCD3-4), VCCD1-2 powers
the drivers for channels 1 and 2 and VCCD3-4
powers channels 3 and 4. The drivers can be
powered by the internal 5V LDO by connecting
their power pins to the LDO5 output through
an RC filter to avoid conducted noise back into
the analog circuitry.
To minimize power dissipation in the 5V LDO,
it is recommended to power the drivers from
an external 5V power source either directly or
by using the V5EXT input. Good quality 1uF to
4.7uF capacitors should be connected directly
between the power pins to ground to optimize
driver performance and minimize noise
coupling to the 5V LDO supply.
by the gate drive currents.
power up, the maximum external load should
be limited to 30mA.
During initial
The AVDD pin is the 1.8V regulator output and
needs to be connected externally to the DVDD
pin on the device. A good quality capacitor
should be connected between this pin and
ground close to the package.
The driver outputs should be connected
For operation with a VCC of 4.75V to 5.5V, the
LDO5 output needs to be connected directly to
VCC on the board.
directly
to
their
corresponding
output
switching FETs, with the Lx output connected
to the drain of the lower FET for the best
current monitoring accuracy.
© 2014 Exar Corporation
16/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
CLOCKS AND TIMING
Freg Mult Reg
DPWM
PLL
System Clock
SEL
Base Frequency
2x
4x
CH1 Timing
x4/x8
Reg
Frequency
Set Reg
Sequencer
To Channels 2®4
Figure 13 XRP7720 Timing Block Diagram
Base Frequency
Figure 13 shows a simplified block diagram of
the XRP7720 timings. Again, please note that
the function blocks and signal names used are
chosen for ease of understanding and do not
necessarily reflect the actual design.
Available 2x
Frequencies kHz
Available 4x
Frequencies kHz
kHz
422.1
429.2
436.4
444.0
451.8
459.8
468.2
476.9
485.8
495.2
504.9
515.0
525.5
536.5
547.9
559.8
572.2
585.2
598.8
613.1
628.0
643.8
660.3
677.6
695.9
715.3
735.7
757.4
780.3
804.7
830.6
858.3
887.9
919.6
953.7
990.4
1030.0
1072.9
1119.6
1170.5
1226.2
105.5
107.3
109.1
111.0
112.9
115.0
117.0
119.2
121.5
123.8
126.2
128.8
131.4
134.1
137.0
139.9
143.1
146.3
149.7
153.3
157.0
160.9
165.1
169.4
174.0
178.8
183.9
189.3
195.1
201.2
207.7
214.6
222.0
229.9
238.4
247.6
257.5
268.2
279.9
292.6
306.5
211.1
214.6
218.2
222.0
225.9
229.9
234.1
238.4
242.9
247.6
252.5
257.5
262.8
268.2
273.9
279.9
286.1
292.6
299.4
306.5
314.0
321.9
330.1
338.8
348.0
357.6
367.9
378.7
390.2
402.3
415.3
429.2
444.0
459.8
476.9
495.2
515.0
536.5
559.8
585.2
613.1
The system timings are generated by a
103MHz internal system clock (Sys_Clk). The
basic timing architecture is to divide the
Sys_Clk down to create a fundamental
switching frequency (Fsw_Fund) for all the
output channels that is settable from 105kHz
to 306kHz. The switching frequency for a
channel (Fsw_CHx) can then be selected as 1
times, 2 times or 4 times the fundamental
switching frequency.
To set the base frequency for the output
channels a “Fsw_Set” value representing the
base frequency shown in Table 1, is entered
into the switching frequency configuration
register. Note that the Fsw_Set value is
basically equal to the Sys_Clk divided by the
base frequency. The system timings are then
created by dividing down Sys_Clk to produce
a base frequency clock, 2X and 4X times the
base frequency clocks, and sequencing timing
to position the output channels relative to
each other. Each output channel then has its
own frequency multiplier register that is used
to select its final output switching frequency.
Table 1 shows the available channel switching
frequencies for the XRP7720 device. In
practice the PA 5.1 design tool handles all the
details and the user only has to enter the
fundamental switching frequency and the 1x,
2x, 4x frequency multiplier for each channel.
Table 1
© 2014 Exar Corporation
17/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
Power Group Enable
–
controls
SUPERVISORY AND CONTROL
enabling and disabling of Group 1 and
Group 2
Power system design with XRP7720 is
accomplished using PowerArchitect™ design
tool version 5.1 (PA 5.1). All figures
referenced in the following sections are taken
from PA 5.1.
Power Channel Enable – controls
enabling and disabling of an individual
channel.
Power OK – indicates that selected
channels have reached their target levels
and have not faulted. Multiple channel
selection is available in which case the
resulting signal is the AND logic function
of all channels selected
DIGITAL I/O
XRP7720 has two General Purpose Input
Output (GPIO) and three Power System Input
Output (PSIO) user configurable pins.
ResetOut – is delayed Power OK. Delay
is programmable in 1msec increments
with the range of 0 to 255 msec
Low Vcc – indicates when Vcc has fallen
below the UVLO fault threshold and
when the UVLO condition clears (Vcc
voltage rises above the UVLO warning
level)
Low Vcc, Power OK and ResetOut signals can
only be forwarded to a single GPIO/PSIO.
In addition, the following are functions that
are unique to GPIO0 and GPIO1.
GPIOs are 3.3V CMOS logic compatible
and 5V tolerant.
PSIO configured as outputs are open
drain and require external pull-up
resistor. These I/Os are 3.3V and 5V
CMOS logic compatible, and up to 15V
capable.
The polarity of the GPIO/PSIO pins is set in
PA 5.1.
Configuring GPIO/PSIOs
The following functions can be controlled from
or forwarded to any GPIO/PSIO:
HW Flags – these are hardware monitoring
functions forwarded to GPIO0 only. The
functions include Under-Voltage Warning,
Over- Temperature Warning, Over-Voltage
Fault, Over-Current Fault and Over -Current
Warning for every channel. Multiple selections
will be combined using the OR logic function.
© 2014 Exar Corporation
18/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
HW Power Good – the Power Good
all channels if the supply drops to critical
levels.
hardware monitoring function. It can only
be forwarded to GPIO1. It is an output
voltage monitoring function that is a
hardware comparison of channel output
voltage against its user defined Power
Good threshold limits (Power Good
minimum and maximum levels). It has no
hysteresis. Multiple channel selections will
be combined using the AND logic function
of all channels selected.
Over Temperature Protection (OTP)
monitors temperature of the chip and will
cause the controller to shutdown all
channels if temperature rises to critical
levels.
Over
Voltage
Protection
(OVP)
monitors regulated voltage of a channel
and will cause the controller to react in a
user specified way if the regulated voltage
surpasses threshold level.
Over
Current
Protection
(OCP)
monitors current of a channel and will
cause the controller to react in a user
specified way if the current level
surpasses threshold level.
The Power Good minimum and maximum
levels are expressed as percentages of the
target voltage.
Start-up
Time-out
Fault
monitors
whether a channel gets into regulation in
a user defined time period
LDO5 Over Current Protection (LDO5
OCP) monitors current drawn from the
regulator and will cause the controller to
be reset if the current exceeds LDO5 limit
(155mA typical)
“PGood Max” is the upper window and
“PGood Min” is the lower window. The
minimum and maximum for each of these
values can be calculated with the following
equation:
UVLO
Both UVLO warning and fault levels are user
programmable and set at 200mV increments
in PA 5.1.
푁 ∗ 퐿푆퐵(푚푉) ∗ 105
( )
푃퐺푂푂퐷 % =
푉푡푎푟푔푒푡 (푉)
Where N =1 to 63 for the PGOOD Max
value and N=1 to 62 for the PGOOD Min
When the warning level is reached the
controller will generate a flag if GPIO0 is so
configured (see the Digital I/O section).
value.
For example, with the target
voltage of 1.5V and set point resolution of
2.5mV (LSB), the Power Good min and
max values can range from 0.17% to
10.3% and 0.17% to 10.5% respectively.
A user can effectively double the range by
changing to the next higher output
voltage range setting, but at the expense
of reduced set point resolution.
When an under voltage fault condition occurs
the XRP7720 outputs are shut down.
In
addition, the host can be informed by
forwarding the Low Vcc signal to any
GPIO/PSIO (see the Digital I/O section). This
signal transitions when the UVLO fault occurs.
Once the UVLO condition clears (Vcc voltage
rises above or to the user-defined UVLO
warning level) the Low Vcc signal will
transition and the controller will be reset.
FAULT HANDLING
There are seven different types of fault
handling:
Special attention needs to be paid in the case
when Vcc = LDO5 = 4.75V to 5.5V. Since the
input voltage ADC resolution is 200mV the
UVLO warning and fault set points are coarse
Under
Voltage
Lockout
(UVLO)
monitors voltage supplied to the Vcc pin
and will cause the controller to shutdown
© 2014 Exar Corporation
19/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
for a 5V input. Therefore, setting the warning
channel and perform auto-restart of the
channel, or to restart the chip.
level at 4.8V and the fault level at 4.6V may
result in the outputs not being re-enabled
until a full 5.0V is reached on Vcc. Setting the
warning level to 4.6V and the fault level at
4.4V will allow UVLO handing as desired.
However, at a fault level below 4.6V, the
device has a hardware UVLO on LDO5 to
ensure proper shutdown of the internal
circuitry of the controller. This means the
4.4V UVLO fault level will never occur.
WARNING:
option during
Choosing the “Restart Chip”
development is NOT
recommended as it makes debug efforts
difficult.
OTP
User defined OTP warning, fault and restart
levels are set at 5°C increments in PA 5.1.
When the warning level is reached the
controller will assert HW Flags on GPIO0 (see
the Digital I/O section).
In the case of shutting down the faulting
channel and auto-restarting, the user has an
option to specify startup timeout (the time in
which the fault is validated) and hiccup
timeout (the period after which the controller
will try to restart the channel) periods in 1
msec increments with a maximum value of
255 msec.
When an OTP fault condition occurs, the
XRP7720 outputs are shut down.
Once temperature reaches a user defined OTP
Restart Threshold level, the controller will
reset.
OVP
A user defined OVP fault level is set in PA 5.1
and is expressed in percentages of a
regulated target voltage.
Resolution is the same as for the target
voltage (expressed in percentages). The OVP
minimum and maximum values are calculated
by the following equation where the range for
N is 1 to 63:
푁 ∗ 퐿푆퐵(푚푉) ∗ 105
( )
푂푉푃 % =
푉푡푎푟푔푒푡 (푉)
When the OVP level is reached and the fault is
generated, it can be monitored through
GPIO0.
Note: The Channel Fault Action response is
the same for either the OVP or OCP event.
A user can choose one of three options on
how to react to an OVP event: to shutdown
the faulting channel, to shut down faulting
© 2014 Exar Corporation
20/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
OCP
A user defined OCP fault level is set with
10mA increments in PA 5.1. PA 5.1 uses
calculations to give the user the approximate
DC output current entered in the current limit
field. However the actual current limit trip
value programmed into the part is limited to
280mV
as
defined
in
the
electrical
characteristics. The maximum value the user
can program is limited by Rdson of the
synchronous
Power
FET
and
current
monitoring ADC range. For example, using a
synchronous FET with Rdson of 30mΩ and
wider ADC range the maximum current limit
programmed would be:
In the case of Shutdown and Auto-restart
Channel the user has an option to specify
startup timeout (the time in which the fault is
validated) and hiccup timeout (the period
after which the controller will try to restart
the channel) periods in 1 msec increments
with a maximum value of 255 msec.
280푚푉
( )
푂퐶푃 푀푎푥 퐴 =
= 9.33퐴
30푚Ω
The current is sampled approximately 30ns
before the low side MOSFET turns off so the
actual measured DC output current in this
example would be 9.33A plus approximately
half the inductor ripple.
Note: The Channel Fault Action response is
the same for either the OVP or OCP event.
Start-up Time-out Fault
An OCP Fault is considered to have occurred
only if the fault threshold has been tripped in
four consecutive switching cycles. When the
switching frequency is set to the 4x multiplier
the current is sampled every other cycle. As
a result it can take as many as 8 switching
cycles for an over current event to be
detected. When operating in 4x mode an
inductor with a soft saturation characteristic is
recommended.
A channel will be at Start-up Time-out Fault if
it does not come-up in a time period specified
in the “Startup Timeout” box. In addition a
channel is at Start-up Timeout Fault if its pre-
bias configuration voltage is within a defined
value too close to the target.
LDO5 OCP
When current is drawn from the LDO5 that
exceeds the LDO5 current limit the controller
will be reset.
In addition, OCP fault can be monitored
through HW Flags on GPIO0. The OCP
warning level is calculated by PA 5.1 as 85%
of the OCP fault level.
V5EXT SWITCHOVER
The V5EXT gives the user an opportunity to
supply an external 5 Volt rail to the controller
in order to reduce the controller’s power
dissipation. The 5 Volt rail can be an
independent power rail present in a system or
any of 7720 channels regulated to 5 Volts and
routed back to the V5EXT pin. It is important
to note that voltage to Vcc must be applied all
the time even after the switchover, in which
A user can choose one of three options in
response to an OCP event: shut down the
faulting channel, shut down faulting channel
and perform auto-restart of the channel, or
restart the chip.
The output current reported by the XRP7720
is processed through a 7 sample median filter
in order to reduce noise. The OCP limit is
compared against unfiltered ADC output.
© 2014 Exar Corporation
21/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
case the current drawn from Vcc supply will
be minimal.
Channels can be controlled independently by
any GPIO/PSIO. Channels will start-up or
shut-down following transitions of signals
applied to GPIO/PSIOs set to control the
If the function is not used, it is recommended
that the pin either be grounded or left
floating. in conjunction, the function must be
disabled through register settings.
channels.
In
development,
using
the
XRP7720ILB-DEV and PA 5.1, control can
always be overridden.
V5EXT switchover control
Regardless of whether the channels are
controlled independently or are in a group the
ramp rates will be followed as specified (see
the Power Sequencing section).
The V5EXT function is enabled in PA 5.1. The
switchover thresholds are programmable in
50mV steps with a total range of 200mV. The
V5EXT switchover has a 150mV hysteresis.
LDO5 automatically turns off when the
external voltage is switched in and turns on
when the external voltage drops below the
lower threshold.
POWER SEQUENCING
All four channels can be grouped together and
will start-up and shut-down in a user defined
sequence.
Selecting none means channel(s) will not be
assigned to any group and therefore will be
controlled independently.
Group Selection
CHANNEL CONTROL
There are three groups:
Group 0 – is controlled by the chip
ENABLE. Channels assigned to this group
will come up with the ENABLE signal being
high (plus an additional delay needed to
load configuration from Flash to runtime
registers), and will go down with the
ENABLE signal being low.
Since it is recommended to leave the
ENABLE pin floating in the applications
when Vcc = LDO5 = 4.75V to 5.5V, please
contact Exar for how to configure the
channels to come up at the power up in
this scenario.
Group 1 – can be controlled by any
GPIO/PSIO. Channels assigned to this
group will start-up or shut-down following
transitions of a signal applied to the
GPIO/PSIO set to control the group.
Group 2 – can be controlled by any
GPIO/PSIO. Channels assigned to this
group will start-up or shut-down following
© 2014 Exar Corporation
22/28
Rev. 1.0.0
XRP7720
Quad Output Universal Customizable PMIC with PFM
transitions of a signal applied to the
GPIO/PSIO set to control the group.
the Stop Threshold level. The stop
threshold level is fixed at 600mV.
Delay – additional time delay a user can
specify to postpone a channel shut-down
with respect to the previous channel in the
order. The delay is expressed in
milliseconds with a range of 0 msec to
255 msec.
Start-up
PROGRAMMING XRP7720
XRP7720ILB-DEV is a FLASH based device
which means its configuration can be
programmed into FLASH NVM and re-
programmed a number of times. The purpose
of this feature is to provide a means to fast
development times.
For each channel within a group a user can
specify the following start-up characteristics:
Ramp Rate – expressed in milliseconds
per Volt.
Order –position of a channel to come-up
within the group
Programming of FLASH NVM is done through
PA 5.1.
Wait PGOOD? – selecting this option for
a channel means the next channel in the
order will not start ramping-up until this
channel reaches the target level and its
Power Good flag is asserted.
Delay – an additional time delay a user
can specify to postpone a channel start-up
with respect to the previous channel in the
order. The delay is expressed in
milliseconds with a range of 0 msec to
255 msec.
Shut-down
For each channel within a group a user can
specify
the
following
shut-down
characteristics:
Ramp Rate – expressed in milliseconds
per Volt.
Order –position of a channel to come-
down within the group
Wait Stop Thresh? – selecting this
option for a channel means the next
channel in the order will not start
ramping-down until this channel reaches
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XRP7720
Quad Output Universal Customizable PMIC with PFM
By clicking on the Flash button the user will
start programming sequence of the design
configuration into the Flash NVM. After the
programming sequence completes the chip
will reset (if automatically reset After Flashing
box is checked) and boot the design
configuration from the Flash.
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XRP7720
Quad Output Universal Customizable PMIC with PFM
ENABLING XRP7720
XRP7720 has a weak internal pull-up ensuring
it gets enabled as soon as internal voltage
supplies have ramped up and are in
regulation.
Driving the Enable pin low externally will keep
the controller in the shut-down mode. A
simple open drain pull down is the
recommended way to shut the XRP7720
down.
If the Enable pin is driven high externally to
control the XRP7720 coming out of the shut-
down mode care must be taken to ensure the
Enable pin is driven high after Vcc gets
supplied to the controller.
No load on LDO5, blue trace. Recovery time
after ENABLE logic high is approximately
40ms.
In the configuration, when Vcc = LDO5 =
4.75V to 5.5V, disabling the device by
grounding
the
Enable
pin
is
not
recommended. It is recommended to leave
the Enable pin floating and place the
controller in the “Standby Mode” instead in
this scenario. The standby mode is defined as
the state when all switching channels are
disabled, all GPIO/PSIOs are programmed as
inputs, and system clock is disabled. In this
state chip consumes 440uA typical.
Short duration Enable pin toggled low
Short duration shutdown pulses to the
ENABLE pin of the XRP7720, which does not
provide sufficient time for the LDO5 voltage
to fall below 3.5V, can result in significant
delay in re-enabling of the device. Some
examples below show LDO5 and ENABLE
pins:
Adding a 200 ohm load on LDO5 pulls voltage
below 3.5V and restart is short.
Note that as VCC increases, the restart time
falls as well. 5.5V input is shown as the worst
case.
Since the ENABLE pin has an internal current
source, a simple open drain pull down is the
recommended way to shut down the
XRP7720. A diode in series with a resistor
between the LDO5 and ENABLE pins may
offer a way to more quickly pull down the
LDO5 output when the ENABLE pin is pulled
low.
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XRP7720
Quad Output Universal Customizable PMIC with PFM
system, then the power loss will increase
significantly and proper thermal design
APPLICATION INFORMATION
becomes critical.
For lower power levels
THERMAL DESIGN
using properly sized MOSFETs and the use of
the internal 5V regulator as a gate drive
supply is considered appropriate.
As a 4 channel controller with internal
MOSFET drivers and 5V gate drive supply all
in one 7x7mm 44pin TQFN package, there is
the potential for the power dissipation to
exceed the package thermal limitations. The
XRP7720 has an internal LDO which supplies
5V to the internal circuitry and MOSFET
LAYOUT GUIDELINES
Refer to application note ANP-32 “Practical
Layout Guidelines for PowerXR Designs”, as
well as ANP-35 for routing long distance gate
drive traces.
drivers during startup.
It is generally
expected that either one of the switching
regulator outputs is 5V or another 5V rail is
available in the system and connected to the
5VEXT pin. If there is no 5V available in the
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XRP7720
Quad Output Universal Customizable PMIC with PFM
PACKAGE SPECIFICATION
44-PIN 7X7MM TQFN
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XRP7720
Quad Output Universal Customizable PMIC with PFM
REVISION HISTORY
Revision
Date
Description
01/31/2014
Initial Release [ECN: 1406-02]
1.0.0
FOR FURTHER ASSISTANCE
Email:
customersupport@exar.com
powertechsupport@exar.com
Exar Technical Documentation:
http://www.exar.com/TechDoc/default.aspx?
EXAR CORPORATION
HEADQUARTERS AND SALES OFFICES
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Fremont, CA 94538 – USA
Tel.: +1 (510) 668-7000
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www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,
is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in
writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all
such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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