XRP7725ILBTR-F [EXAR]
Power Management System;
| 型号： | XRP7725ILBTR-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Power Management System |
| 文件： | 总34页 (文件大小：3596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
January 2014
Rev. 1.0.0
GENERAL DESCRIPTION
FEATURES
• Quad Channel Step-down Controller
− Digital PWM 105kHz-1.23MHz Operation
− Individual Channel Frequency Selection
− Patented digital PFM with Ultrasonic mode
− Patented Over Sampling Feedback
The XRP7725 is a quad channel Digital Pulse
Width Modulated (DPWM) Step down (buck)
controller. A wide 4.75V to 5.5V and 5.5V to
25V input voltage dual range allows for single
supply operation from standard power rails.
With integrated FET gate drivers, two LDOs for
standby power and a 105kHz to 1.23MHz
independent channel to channel programmable
constant operating frequency, the XRP7725
reduces overall component count and solution
footprint and optimizes conversion efficiencies.
A selectable digital Pulse Frequency Mode
(DPFM) and low operating current result in
better than 80% efficiency down to 10mA load
provides support for portable and Energy Star
compliant applications. Each XRP7725 output
channel is individually programmable down to
a minimum 0.6V with a resolution of 2.5mV,
and configurable for precise soft start and soft
stop sequencing, including delay and ramp
control.
• Instantaneous current monitoring –
Intel® Node Manager Compatible
• 4.75V to 25V Input Voltage
− 4.75V-5.5V and 5.5V-25V Input Ranges
− 0.6V to 5.5V Output Voltage
• SMBus Compliant - I2C Interface
− Full Power Monitoring and Reporting
• 3 x 15V Capable PSIO + 2 x GPIOs
• Full Start/Stop Sequencing Support
• Built-in Thermal, Over-Current, UVLO
and Output Over-Voltage Protections
• On Board 5V and 3.3V Standby LDOs
• On Board Non-volatile Memory
• Supported by PowerArchitect™ 5
The XRP7725 operation is fully controlled via
an SMBus-compliant I2C interface allowing for
advanced local and/or remote reconfiguration,
full performance monitoring and reporting as
well as fault handling.
APPLICATIONS
• Blade Servers
• Micro Servers
Built-in independent output over voltage, over
temperature, over-current and under voltage
lockout protections insure safe operation
under abnormal operating conditions.
• Network Adapter Cards
• Base Stations
• Switches/Routers
• Broadcast Equipment
• Industrial Control Systems
• Automatic Test Equipment
The XRP7725 is offered in a RoHS compliant,
“green”/halogen free 44-pin TQFN package.
TYPICAL APPLICATION DIAGRAM
XRP7725
Figure 1: XRP7725 Application Diagram
Exar Corporation
48720 Kato Road, Fremont CA 94538, USA
www.exar.com
Tel. +1 510 668-7000 – Fax. +1 510 668-7001
XRP7725
Intel Node Manager Compatible Programmable Power
Management System
FEATURES AND BENEFITS
System Integration Capabilities
• Single supply operation
• I2C interface allows:
Programmable Power Benefits
• Fully Configurable
− Output set point
− Intel Node Manager Compatible as well as
other Power Management systems
− Feedback compensation
− Frequency set point
− Under voltage lock out
− Input voltage measurement
− Gate drive dead time
− Modification or reading of internal
registers that control or monitor:
− Output Current
− Input and Output Voltage
− Soft-Start/Soft-Stop Time
− Power Good
• Reduced Development Time
− Configurable and re-configurable for
different Vout, Iout, Cout, and Inductor
values
− Part Temperature
− Enable/Disable Outputs
− Over Current
− No need to change external passives for a
new output specification.
− Over Voltage
− Temperature Faults
• Higher integration and Reliability
− Adjusting fault limits and
disabling/enabling faults
− Packet Error Checking (PEC) on I2C
− Many external components used in the
past can be eliminated thereby
significantly improving reliability.
communication
PowerArchitect™ 5.1 Design and
Configuration Software
• 5 GPIO pins with a wide range of
configurability
− Wizard quickly generates a base design
− Calculates all configuration registers
− Projects can be saved and/or recalled
− Fault reporting (including UVLO
Warn/Fault, OCP Warn/Fault, OVP,
Temperature, Soft-Start in progress,
Power Good, System Reset)
− GPIOs can be configured easily and
intuitively
− Allows a Logic Level interface with other
non-digital IC’s or as logic inputs to other
devices
− Dashboard interface can be used for real-
time monitoring and debug
• Frequency and Synchronization
System Benefits
Capability
• Intel Node Manager Compatible current
− Selectable switching frequency between
monitoring.
105kHz and 1.2MHz
− Main oscillator clock and DPWM clock can
• Ability to perform remote configuration
be synchronized to external sources
updates.
− ‘Master’, ‘Slave’ and ‘Stand-alone’
• Ability to analyze operating history, perform
diagnostics and if required, take the supply
off-line after making other system
adjustments.
configurations are possible
• Internal MOSFET Drivers
− Internal FET drivers (4Ω/2Ω) per channel
− Built-In Automatic Dead-time adjustment
− 30ns Rise and Fall times
• 4 Independent SMPS channels and 2
LDOs in a 7x7mm TQFN
© 2012 Exar Corporation Confidential
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
These are stress ratings only and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
Input Voltage Range VCC ...............................5.5V to 25V
Input Voltage Range VCC = LDO5 ................4.75V to 5.5V
VOUT1, 2, 3, 4 ......................................................5.5V
Junction Temperature Range....................-40°C to 125°C
JEDEC Thermal Resistance θJA ..........................30.2°C/W
VCCD, LDO5, LDO3_3, GLx, VOUTx .............-0.3V to 7.0V
ENABLE, 5V_EXT.......................................-0.3V to 7.0V
GPIO0/1, SCL, SDA ............................................... 6.0V
PSIOs Inputs, BFB.................................................. 18V
DVDD, AVDD ........................................................ 2.0V
VCC ....................................................................... 28V
LX#.............................................................-1V to 28V
BSTx, GHx....................................................VLXx + 6V
Storage Temperature..............................-65°C to 150°C
Junction Temperature ..........................................150°C
Power Dissipation................................Internally Limited
Lead Temperature (Soldering, 10 sec) ...................300°C
ESD Rating (HBM - Human Body Model).................... 2kV
ELECTRICAL SPECIFICATIONS
Specifications with standard type are for an Operating Junction Temperature of TJ = 25°C only; limits applying over the full
Operating Junction Temperature range are denoted by a “•”. Typical values represent the most likely parametric norm at TJ
= 25°C, and are provided for reference purposes only. Unless otherwise indicated, VCC = 5.5V to 25V, 5V EXT open.
QUIESCENT
CURRENT
Parameter
Min.
Typ.
Max.
Units
Conditions
EN = 0V, VCC = 12V
µA
VCC Supply Current in SHUTDOWN
ENABLE Turn On Threshold
10
20
V
0.95
10
VCC = 12V Enable Rising
EN=5V
0.82
-10
uA
uA
ENABLE Pin Leakage Current
VCC Supply Current in STANDBY
EN=0V
LDO3_3 disabled, all channels disabled
GPIOs programmed as inputs
VCC =12V,EN = 5V
µA
440
3.1
600
2 channels on and set at 5V, VOUT forced
to 5.1V, no load, non-switching, Ultra-
sonic off, VCC =12 V, No I2C activity.
mA
VCC Supply Current 2ch PFM
4 channels on and set at 5V, VOUT forced
to 5.1V, no load, non-switching, Ultra-
sonic off, VCC =12V, No I2C activity.
mA
mA
VCC Supply Current 4ch PFM
VCC Supply Current ON
4.0
18
All channels enabled, Fsw=600kHz, gate
drivers unloaded, No I2C activity.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
INPUT
VOLTAGE
RANGE AND UNDERVOLTAGE LOCKOUT
Parameter
Min.
Typ.
Max.
Units
Conditions
•
•
25
V
V
5.5
VCC Range
5.5
With VCC connected to LDO5
4.75
VOLTAGE
F
EEDBACK
ACCURACY AND
OUTPUT
VOLTAGE
SET
POINT
RESOLUTION
Parameter
Min.
Typ.
Max.
Units
Conditions
5
20
7.5
22.5
15
45
20
50
30
90
40
100
5.5
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
V
-5
-20
-7.5
-22.5
-15
-45
-20
-50
-30
-90
-40
-100
0.6
VOUT Regulation Accuracy
Low Output Range
0.6V to 1.6V
0.6 ≤ VOUT ≤ 1.6V
•
•
•
•
•
0.6 ≤ VOUT ≤ 1.6V
VCC =LDO5
PWM Operation
VOUT Regulation Accuracy
Mid Output Range
0.6V to 3.2V
0.6 ≤ VOUT ≤ 3.2V
0.6 ≤ VOUT ≤ 3.2V
VCC =LDO5
PWM Operation
VOUT Regulation Accuracy
High Output Range
0.6V to 5.5V
0.6 ≤ VOUT ≤ 5.5V
0.6 ≤ VOUT ≤ 4.2V
VCC =LDO5
PWM Operation
•
•
VOUT Regulation Range
Without external divider network
12.5
25
50
Low Range
Mid Range
High Range
VOUT Native Set Point
Resolution
mV
mV
kꢀ
2.5
5
10
Low Range
Mid Range
High Range
VOUT Fine Set Point Resolution1
VOUT Input Resistance
120
90
75
Low Range
Mid Range
High Range
10
1
0.67
Low Range
Mid Range
High Range
VOUT Input Resistance in PFM
Operation
Mꢀ
mV
mV
157.5
315
630
Low Range
Mid Range
High Range
-155
-310
-620
Power Good and OVP Set Point
Range (from set point)
5
10
20
Low Range
Mid Range
High Range
-5
-10
-20
Power Good and OVP Set Point
Accuracy
BFB Set Point Range
BFB Set Point Resolution
BFB Accuracy
16
V
V
V
9
1
0.5
-0.5
Note 1: Fine Set Point Resolution not available in PFM
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
C
URRENT AND AUX ADC (MONITORING ADC
S)
Parameter
Min.
Typ.
Max.
Units
Conditions
Low Range (≤120mV)
-60mV applied
±1.25
3.75
10
5
mV
mV
mV
mV
LSB
-3.75
-10
-5
•
•
Current Sense Accuracy
±2.5
High Range (≤280mV)
-150mV
+12.5
-12.5
Current Sense ADC INL
DNL
±0.4
0.27
1.25
Current Limit Set Point
Resolution and Current
Sense ADC Resolution
mV
mV
mV
Low Range (≤120mV)
High Range (≤280mV)
2.5
20
40
Low Range (≤120mV)
High Range (≤280mV)
-120
-280
Current Sense ADC Range
15
30
60
Low Range
Mid Range
High Range
VOUT ADC Resolution
mV
VOUT ADC Accuracy
VCC ADC Range
1
LSB
V
-1
25
Note 2
4.6
UVLO WARN SET
4.72
4.72
4.55
V
V
UVLO WARN set point 4.6V, VCC =LDO5
UVLO WARN set point 4.6V, VCC =LDO5
UVLO FAULT set point 4.4V, VCC =LDO5
4.4
4.4
4.2
UVLO WARN CLEAR
UVLO FAULT SET (Note 3)
VCC ADC Resolution
VCC ADC Accuracy
V
200
5
mV
LSB
°C
°C
1
Vin <= 20V
-1
Die Temp ADC Resolution
Die Temp ADC Range
156
Output value is in Kelvin
-44
Note 2: Although Range of VCC ADC is 0V to 25V, operation below 4.55 is not supported.
Note 3: This test ensures an UVLO FAULT flag will be given before the LDO5 hardware UVLO trips.
L
INEAR
R
EGULATORS
Parameter
Min.
Typ.
Max.
Units
Conditions
5.5V ≤ VCC ≤ 25V
0mA < ILDO5OUT < 130mA, LDO3_3 Off
LDO5 Output Voltage
5.0
5.15
V
4.85
•
•
•
LDO5 Current Limit
155
180
mA
V
LDO5 Fault Set
VCC Rising
135
LDO5 UVLO
4.74
LDO5 PGOOD Hysteresis
LDO5 Bypass Switch Resistance
375
1.1
mV
Ω
VCC Falling
1.5
2.5
Bypass Switch Activation
Threshold
•
%
V5EXT Rising, % of threshold setting
V5EXT Falling
2.5
Bypass Switch Activation
Hysteresis
150
3.3
mV
4.6V ≤ LDO5 ≤ 5.5V
0mA < ILDO3_3OUT < 50mA
•
•
LDO3_3 Output Voltage
LDO3_3 Current Limit
3.45
85
V
3.15
53
mA
LDO3_3 Fault Set
ENABLE transition from logic low to
high. Once LDO5 in regulation above
limits apply.
Maximum total LDO loading
during ENABLE start-up
30
mA
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
PWM GENERATORS AND
Parameter
OSCILLATOR
Min.
Typ.
Max.
Units
Conditions
Switching Frequency (fsw)
Range
1230
5
kHz
%
Steps defined in Table 1
105
–5
fsw Accuracy
CLOCK IN
Synchronization Frequency
When synchronizing to an external clock
(Range 1)
25.7
12.8
31
MHz
20
CLOCK IN
Synchronization Frequency
When synchronizing to an external clock
(Range 2)
15.5
MHz
10
GPIOS4
Parameter
Min.
Typ.
Max.
Units
Conditions
Input Pin Low Level
0.8
V
V
Input Pin High Level
Input Pin Leakage Current
Output Pin Low Level
Output Pin High Level
Output Pin High Level
2.0
1
µA
V
0.4
ISINK = 1mA
V
ISOURCE = 1mA
ISOURCE = 0mA
2.4
3.3
3.6
10
V
Output Pin High-Z leakage
Current (GPIO pins only)
µA
Maximum Sink Current
I/O Frequency
1
mA
Open Drain Mode
30
MHz
Note 4: 3.3V CMOS logic compatible, 5V tolerant.
PSIOS5
Parameter
Min.
Typ.
Max.
Units
Conditions
Input Pin Low Level
0.8
V
V
Input Pin High Level
Input Pin Leakage Current
Output Pin Low Level
2.0
1
µA
V
0.4
ISINK = 3mA
Open Drain. External pull-up resistor to
user supply
Output Pin High Level
15
V
Output Pin High-Z leakage
Current (PSIO pins only)
10
5
µA
I/O Frequency
MHz
Note 5: 3.3V/5.0V CMOS logic compatible, maximum rating of 15.0V
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
SMBUS (I2C) INTERFACE
Parameter
Min.
Typ.
Max.
Units
Conditions
VIO = 3.3 V ±10%
Input Pin Low Level, VIL
Input Pin High Level, VIH
0.3 VIO
V
V
VIO = 3.3 V±10%
0.7 VIO
Hysteresis of Schmitt Trigger
inputs, Vhys
V
VIO = 3.3 V±10%
0.05 VIO
Output Pin Low Level (open
drain or collector), VOL
0.4
10
250
1
V
ISINK = 3mA
Input leakage current
µA
Ns
pF
Input is between 0.1 VIO and 0.9 VIO
-10
Output fall time from VIHmin to
VILmax
With a bus capacitance (Cb)from 10 pF to
400 pF
20 + 0.1
Cb
Internal Pin Capacitance
G
ATE
DRIVERS
Parameter
Min.
Typ.
Max.
Units
Conditions
GH, GL Rise Time
GH, GL Fall Time
17
11
Ns
Ns
At 10-90% of full scale, 1nF Cload
GH, GL Pull-Up On-State Output
Resistance
4
2
5
ꢀ
ꢀ
GH, GL Pull-Down On-State
Output Resistance
2.5
GH, GL Pull-Down Resistance in
Off-Mode
50
9
kꢀ
ꢀ
VCC = VCCD = 0V.
@ 10mA
Bootstrap diode forward
resistance
Minimum On Time
Minimum Off Time
50
ns
ns
1nF of gate capacitance.
1nF of gate capacitance
125
Minimum Programmable Dead
Time
20
ns
us
ps
Does not include dead time variation from
driver output stage
Tsw=switching period
Maximum Programmable Dead
Time
Tsw
607
Programmable Dead Time
Adjustment Step
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
BLOCK DIAGRAM
BST1
Channel 1
GH1
LX1
Feedback
ADC
Digital
PID
Hybrid
DPWM
VOUT1
Gate
Driver
GL1
PreScaler
1/2/4
Dead
Time
GL_RTN1
VCC
VREF
DAC
Current
ADC
SS & PD
VCCD1-2
VOUT3
VOUT3
VOUT4
Channel 2
Channel 3
VCCD3-4
Channel 4
Vout1
4uA
Vout2
Vout3
Vout4
Vtj
ENABLE
GPIO 0-1
Internal
POR
MUX
NVM
(FLASH)
GPIO
PSIO
I2C
Sequencing
BFB
VCC
Fault
Handling
OTP
UVLO
OCP
PSIO 0-2
SDA,SCL
PWR
Good
Configuration
Registers
LDO5
OVP
5V LDO
LOGIC
CLOCK
LDO3_3
3.3V LDO
Figure 2: XRP7725 Block Diagram
LDO BLOCK DIAGRAM
Figure 3: XRP7725 LDO Block Diagram
8/34
© 2014 Exar Corporation
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
PIN ASSIGNMENT
LDO3_3
1
2
33
32
31
30
29
28
27
26
25
24
23
GL_RTN2
GL2
AGND
CPLL
3
LX2
AVDD
VOUT1
VOUT2
VOUT3
VOUT4
GPIO0
GPIO1
SDA
4
GH2
5
BST2
GL_RTN3
GL3
XRP7725
TQFN
7mm X 7mm
6
7
8
LX3
9
GH3
Exposed Pad: AGND
10
11
BST3
VCCD3-4
Figure 4: XRP7725 Pin Assignment
PIN DESCRIPTION
Name
Pin Number
Description
Input voltage. Place a decoupling capacitor close to the pin. This input is used in UVLO
fault generation.
41
VCC
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling
capacitor close to the pin.
16
DVDD
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail (for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible etch.
VCCD1-2
VCCD3-4
23,34
2
Analog ground pin. This is the small signal ground connection.
AGND
Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
39,33, 28,22
GL_RTN1-4
Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
38,32, 27,21
36,30, 25,19
GL1-GL4
GH1-GH4
Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Name
Pin Number
Description
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching
node at the junction between the two external power MOSFETs and the inductor. These
pins are also used to measure voltage drop across bottom MOSFETs in order to provide
output current information to the control engine.
37,31, 26,20
LX1-LX4
High side driver supply pin(s). Connect BST to the external capacitor as shown in the
Typical Application Circuit on page 2. The high side driver is connected between the
BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each
cycle.
35,29, 24,18
9,10
BST1-BST4
GPI0-GPIO1
PSIO0-PSIO2
These pins can be configured as inputs or outputs to implement custom flags, power
good signals, enable/disable controls and synchronization to an external clock.
Open drain, these pins can be used to control external power MOSFETs to switch loads
on and off, shedding the load for fine grained power management. They can also be
configures as standard logic outputs or inputs just as any of the GPIOs can be
configured, but as open drains require an external pull-up when configured as outputs.
13,14,15
SMBus/I2C serial interface communication pins.
11,12
SDA, SCL
Connect to the output of the corresponding power stage. The output is sampled at least
once every switching cycle
5,6,7,8
VOUT1-VOUT4
Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of
the IC is in the stand-by mode. This LDO is also used to power the internal Analog
Blocks.
44
1
LDO5
Output of the 3.3V standby LDO. This is a micro power LDO that can remain active
while the rest of the IC is in shutdown.
LDO3_3
ENABLE
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,
registers configuration loaded, etc.). The pin must be held low for the XRP7725 to be
placed into shutdown.
40
Input from the 15V output created by the external boost supply. When this pin goes
below a pre-defined threshold, a pulse is created on the low side drive to charge this
output back to the original level. If not used, this pin should be connected to GND.
42
BFB
Digital ground pin. This is the logic ground connection, and should be connected to the
ground plane close to the PAD.
17
3
DGND
CPLL
Connect to a 2.2nF capacitor to GND.
External 5V that can be provided. If one of the output channels is configured for 5V,
then this voltage can be fed back to this pin for reduced operating current of the chip
and improved efficiency.
43
V5EXT
Output of the internal 1.8V LDO. A decoupling capacitor should be placed between
AVDD and AGND close to the chip.
4
AVDD
PAD
This is the die attach paddle, which is exposed on the bottom of the part. Connect
externally to the ground plane.
45
ORDERING INFORMATION
Temperature
Part Number
Packing
Quantity
I2C Default
Address
Marking
Package
Note 1
Range
XRP7725ILB
YYWW
XRP7725ILB-F
260/Tray
Halogen Free
Halogen Free
-40°C≤TJ≤+125°C
-40°C≤TJ≤+125°C
0x28 (7Bit)
44-pin TQFN
XRP7725ILBTR-F
2.5K/Tape & Reel
Lot #
Evaluation kit includes XRP7725EVB-DEMO-1 Evaluation Board with Power
XRP7725EVB-DEMO-1-KIT
XRP7725EVB-DEMO-1
Architect software and XRP77XXEVB-XCM (USB to I2C Exar Configuration Module)
XRP7725 Evaluation Board
“YY” = Year – “WW” = Work Week
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
TYPICAL PERFORMANCE CHARACTERISTICS
All data taken at VCC = 12V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from XRP7725EVB. See
XRP7725EVB-DEMO-1 Manual.
Figure 1: PWM to PFM Transition
Figure 5: PFM to PWM Transition
Figure 2: 0-6A Transient 300kHz PWM only
Figure 3: 0-6A Transient 300kHz with OVS ±5.5%
Figure 4: Sequential Start-up
Figure 5: Sequential Shut Down
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Example
Figure 6: Simultaneous Start-up
Figure 7: Simultaneous Shut Down
Figure 9: LDO5 Brown Out Recovery, No Load
Figure 8: PFM Zero Current Accuracy
Vcc
Vcc
Vcc
Vcc
C
Figure 10: Enable Threshold Over Temp
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
external circuitry. The 3.3V LDO is solely for
customer use and is not used by the chip.
There is also a 1.8V linear regulator which is
for internal use only and should not be used
externally.
FUNCTIONAL OVERVIEW
The XRP7725 is a quad-output digital pulse
width modulation (DPWM) controller with
integrated
gate
drivers
for
use
with
synchronous buck switching regulators. Each
output voltage can be programmed from 0.6V
to 5.5V without the need for an external
A key feature of the XRP7725 is its advinced
power management capabilities. All four
outputs are independently programmable and
provide the user full control of the delay,
ramp, and sequence during power up and
power down. The user may also control how
the outputs interact and power down in the
event of a fault. This includes active ramp
down of the output voltages to remove an
output voltage as quickly as possible. Another
useful feature is that the outputs can be
defined and controlled as groups.
voltage
divider.
The
wide
range
of
programmable DPWM switching frequency
(from 105 kHz to 1.2 MHz) enables the user to
optimize for efficiency or component sizes.
Since the digital regulation loop requires no
external
passive
components,
loop
performance is not compromised due to
external component variation or operating
condition.
The XRP7725 provides a number of critical
The XRP7725 has two main types of
programmable memory. The first type is
runtime registers that contain configuration,
control and monitoring information for the
chip. The second type is rewritable Non-
Volatile Flash Memory (NVFM) that is used for
permanent storage of the configuration data
along with various chip internal functions.
During power up, the run time registers are
loaded from the NVFM allowing for standalone
operation.
safety
features,
such
as
Over-Current
Protection (OCP), Over-Voltage Protection
(OVP), Over Temperature Protection (OTP)
plus input Under Voltage Lockout (UVLO). In
addition, a number of key health monitoring
features such as warning level flags for the
safety functions, Power Goods (PGOOD), etc.,
plus full monitoring of system voltages and
currents. The above are all programmable
and/or readable from the SMBus and many
are steerable to the GPIOs for hardware
monitoring.
The XRP7725 brings an extremely high level of
functionality
programmable
decreasing product budgets require the
designer to quickly make good
cost/performance tradeoffs to be truly
successful. By incorporating four switching
channels, two user LDOs, a charge pump
boost controller, along with internal gate
drivers, all in a single package, the XRP7725
allows for extremely cost effective power
system designs. Another key cost factor that
is often overlooked is the unanticipated
and
power
performance
system.
to
a
Ever
For hardware communication, the XRP7725
has two logic level General Purpose Input-
Output (GPIO) pins and three, 15V, open
drain, Power System Input-Output (PSIO)
pins. Two pins are dedicated to the SMBus
data (SDA) and clock (SCL). Additional pins
include Chip Enable (Enable), Aux Boost
Feedback (BFB) and External PLL Capacitor
(CPLL).
In addition to providing four switching outputs,
the XRP7725 also provides control for an Aux
boost supply, and two stand-by linear
regulators that produce 5V and 3.3V for a total
of seven customer usable supplies in a single
device.
Engineering
Change Order (ECO). The
programmable versatility of the XRP7725,
along with the lack of hard wired configuration
components, allows for minor and major
changes to be made in circuit by simple
reprogramming.
The 5V LDO is used for internal power and is
also available for customer use to power
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
THEORY OF OPERATION
C
HIP
ARCHITECTURE
R
EGULATION
L
OOPS
Vin
Vdrive
(VCC)
(VCCD)x
AFE
Vref
DAC
Vin Feed
Forward
Fine
Adjust
GHx
GLx
LXx
Scaler
÷1,2,4
Error
Amp
AFE
ADC
Error
Register
Gate
Driver
VFB
(VOUTx)
PID
DPWM
Window
Comp.
Current
ADC
OVS
PFM/
Ultrasonic
PWM-
PFM Sel
Figure 16: XRP7725 Regulation Loops
Figure 16 shows a simplified functional block
diagram of the regulation loops for one output
channel of the XRP7725. There are four
separate parallel control loops; Pulse Width
1. For output voltages from 1.6V to 3.2V (mid
range) the scaler gain is 1/2 and for voltages
greater than 3.2V (high range) the gain is 1/4.
This results in the low range having an output
voltage resolution of 12.5mV, the mid range
having a resolution of 25mV and the high
range having a resolution of 50mV. The error
amp has a gain of 4 and compares the output
voltage of the scaler to Vref to create an error
voltage on its output. This is converted to a
digital error term by the AFE ADC and is
stored in the error register. The error register
has a fine adjust function that can be used to
improve the output voltage set point
resolution by a factor of 5 resulting in a low
range resolution of 2.5mV, a mid range
resolution of 5mV and a high range resolution
of 10mV. The output of the error register is
then used by the Proportional Integral
Derivative (PID) controller to manage the loop
dynamics.
Modulation
(PWM),
Pulse
Frequency
Modulation (PFM), Ultrasonic, and Over
Sampling (OVS). Each of these loops is fed by
the Analog Front End (AFE) as shown at the
left of the diagram. The AFE consist of an
input voltage scaler, a programmable Voltage
Reference (Vref) DAC, Error Amplifier, and a
window comparator. Some of the functional
blocks are common and shared by each
channel by means of a multiplexer.
PWM Loop
The PWM loop operates in Voltage Control
Mode (VCM) with optional VIN feed forward
based on the voltage at the VCC pin. The
reference voltage (Vref) for the error amp is
generated by a 0.15V to 1.6V DAC that has
12.5mV resolution. In order to provide a 0.6V
to 5.5V output voltage range, an input scaler
is used to reduce feedback voltages for higher
output voltages to bring them within the 0.15V
to 1.6V control range. So for output voltages
up to 1.6V (low range) the scaler has a gain of
The XRP7725 PID is a 17-bit five-coefficient
control engine that calculates the required
duty cycle under the various operating
conditions and feeds it to the Digital Pulse
Width Modulator (DPWM). Besides the normal
© 2014 Exar Corporation
14/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
coefficients the PID also uses the VCC voltage
to provide a feed forward function.
# Cycles Reg
Default = 20
A
A<B
B
CHx Fsw
COUNTER
Clear
Clk
PFM Current
The XRP7725 DPWM includes a special delay
timing loop that provides a timing resolution
that is 16 times the master oscillator
frequency (103MHz) for a timing resolution of
607ps for both the driver pulse width and dead
time delays. The DWPM produces the Gate
High (GH) and Gate Low (GL) signals for the
driver. The maximum and minimum on-times
and dead time delays are programmable by
configuration resisters.
A
A<B
B
Threshold Reg
IADC
PWM MODE
PFM MODE
S
R
Q
Q
VOUT
+
-
VREF HIGH
PFM EXIT
TRIGGER PULSE
-
+
VREF
-
+
VREF LOW
Figure 17: PFM Enter/Exit Functional Diagram
To provide current information, the output
inductor current is measured by a differential
amplifier that reads the voltage drop across
the RDS of the lower FET during its on time.
There are two selectable ranges, a low range
with a gain of 8 for a +20mV to -120 mV
range, and a high range with a gain of 4 for a
+40mV to -280mV range. The optimum range
to use will depend on the maximum output
current and the RDS of the lower FET. The
measured voltage is then converted to a
digital value by the current ADC block. The
resulting current value is stored in a readable
register, and also used to determine when
PWM to PFM transitions should occur.
The PFM loop works in conjunction with the
PWM loop and is entered when the output
current falls below a programmed threshold
level for a programmed number of cycles.
When PFM mode is entered, the PWM loop is
disabled and instead, the scaled output
voltage is compared to Vref with a window
comparator. The window comparator has three
thresholds; normal (Vref), high (Vref +
%high) and low (Vref - %low). The %high and
%low values are programmable and track
Vref.
In PFM mode, the normal comparator is used
to regulate the output voltage. If the output
voltage falls below the Vref level, the
comparator is activated and triggers the
DPWM to start a switching cycle. When the
high side FET is turned on, the inductor
current ramps up which charges up the output
capacitors and increases their voltage. After
the completion of the high side and low side
on-times, the lower FET is turned off to inhibit
any inductor reverse current flow. The load
current then discharges the output capacitors
until the output voltage falls below Vref and
the normal comparator is activated. This
triggers the DPWM to start the next switching
cycle. The time from the end of the switching
cycle to the next trigger is referred to as the
PFM mode loop
The XRP7725 has a PFM loop that can be
enabled to improve efficiency at light loads.
By reducing switching frequency and operating
in the discontinuous conduction mode (DCM),
both switching and conduction losses are
minimized.
Figure 17 shows a functional diagram of the
PFM logic.
dead zone.
When PFM mode is initially
entered the switching duty cycle is equal to
the steady-state PWM duty cycle. This will
cause the inductor ripple current to be at the
same level that it was in PWM mode. During
operation the PFM duty cycle is calculated
based on the ratio of the output voltage to
VCC. This method ensures that the output
© 2014 Exar Corporation
15/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
voltage ripple is well controlled and is much
lower than in other architectures which use a
“burst” methodology.
outside the set high or low limits, the OVS
control electronics can immediately modify the
pulse width of the GH or GL drivers to respond
accordingly, without having to wait for the
next cycle to start. OVS has two types of
response depending on whether the high limit
is exceeded during an unloading transient
(Over Voltage), or the low limit is exceeded
during a loading transient (Under Voltage).
If the output voltage goes outside the
high/low windows, PFM mode is exited and the
PWM loop is reactivated.
Although the PFM mode is effective at
improving efficiency at light load, at very light
loads the dead zone time can increase to the
point where the switching frequency can enter
the audio hearing range. When this happens
some components, like the output inductor
and ceramic capacitors, can emit audible
noise. The amplitude of the noise depends
mainly on the board design and on the
manufacturer and construction details of the
components. Proper selection of components
can reduce the sound to very low levels. In
general Ultrasonic Mode is not used unless
required as it reduces light load efficiency.
Under Voltage OVS: If there is an increasing
current load step, the output voltage will drop
until the regulator loop adapts to the new
conditions to return the voltage to the correct
level. Depending on where in the switching
cycle the load step happens there can be a
delay of up to one switching cycle before the
control loop can respond. With OVS enabled if
the output voltage drops below the lower
level, an immediate GH pulse will be
generated and sent to the driver to increase
the output inductor current toward the new
load level without having to wait for the next
cycle to begin. If the output voltage is still
below the lower limit at the beginning of the
next cycle, OVS will work in conjunction with
the PID to insert additional GH pulses to
quickly return the output voltage back within
its regulation band. The result of this system
is transient response capabilities on par or
exceeding those of a constant on-time control
loop.
Ultrasonic Mode
Ultrasonic mode is an extension of PFM to
ensure that the switching frequency never
enters the audible range. When this mode is
entered, the switching frequency is set to
30kHz and the duty cycle of the upper and
lower FETs, which are fixed in PFM mode, are
decreased as required to keep the output
voltage in regulation while maintaining the
30kHz switching frequency.
Over Voltage OVS: When there is a step load
current decrease, the output voltage will
increase (bump up) as the excess inductor
current that is no longer used by the load
flows into the output capacitors causing the
Under extremely light or zero load currents,
the GH on time pulse width can decrease to its
minimum width. When this happens, the lower
FET on time is increased slightly to allow a
small amount of reverse inductor current to
flow back into VIN to keep the output voltage
in regulation while maintaining the switching
frequency above the audio range.
output voltage to rise.
The voltage will
continue to rise until the inductor current
decreases to the new load current. With OVS
enabled, if the output voltage exceeds the
high limit of the window comparator, a
blanking pulse is generated to truncate the GH
signal. This causes inductor current to
immediately begin decreasing to the new load
Oversampling OVS Mode
Oversampling (OVS) mode is a feature added
to the XRP7725 to improve transient
responses. This mode can only be enabled
when the channel switching frequency is
operating in 1x frequency mode. In OVS mode
the output voltage is sampled four times per
switching cycle and is monitored by the AFE
window comparators. If the voltage goes
level.
The GH signal will continue to be
blanked until the output voltage falls below
the high limit. Again, since the output voltage
is sampled at four times the switching
frequency, over shoot will be decreased and
the time required to get back into the
regulation band is also decreased.
© 2014 Exar Corporation
16/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
OVS can be used in conjunction with both the
(LDO5) and 3.3V (LDO3_3) for both internal
and external use. Additionally it also has a
1.8V regulator that supplies power for the
XRP7725 internal circuits. Figure 3 shows a
block diagram of the linear power supplies.
LDO5 is the main power input to the device
and is supplied by an external 5.5V to 25V
(VCC) supply. The output of LDO5 should be
PWM and PFM operating modes. When it is
activated it can noticeably decrease output
voltage excursions when transitioning between
PWM and PFM modes.
INTERNAL DRIVERS
The internal high and low gate drivers use
totem pole FETs for high drive capability. They
are powered by two external 5V power pins
(VCCD1-2) and (VCCD3-4), VCCD1-2 powers
the drivers for channels 1 and 2 and VCCD3-4
powers channels 3 and 4. The drivers can be
powered by the internal 5V LDO by connecting
their power pins to the LDO5 output through
an RC filter to avoid conducted noise back into
the analog circuitry.
bypassed by
a
good quality capacitor
connected between the pin and ground close
to the device. The 5V output is used by the
XRP7725 as a standby power supply and is
also used to power the 3.3V and 1.8V linear
regulators inside the chip and can also supply
power to the 5V gate drivers. The total output
current that the 5V LDO can provide is 130mA.
The XRP7725 consumes approximately 20mA
and the rest is shared between LDO3_3 and
the gate drive currents. During initial power
up, the maximum external load should be
limited to 30mA.
To minimize power dissipation in the 5V LDO it
is recommended to power the drivers from an
external 5V power source either directly or by
using the V5EXT input. Good quality 1uF to
4.7uF capacitors should be connected directly
between the power pins to ground to optimize
driver performance and minimize noise
coupling to the 5V LDO supply.
The 3.3V LDO output available on the LDO3_3
pin is solely for customer use and is not used
internally. This supply may be turned on or off
by the configuration registers. Again a good
bypass capacitor should be used.
The driver outputs should be connected
The AVDD pin is the 1.8V regulator output and
needs to be connected externally to the DVDD
pin on the device. A good quality capacitor
should be connected between this pin and
ground close to the package.
directly
to
their
corresponding
output
switching FETs, with the Lx output connected
to the drain of the lower FET for the best
current monitoring accuracy.
See ANP-32 “Practical Layout Guidelines for
PowerXR Designs.”
For operation with a VCC of 4.75V to 5.5V, the
LDO5 output needs to be connected directly to
VCC on the board.
LDO
S
The XRP7725 has two internal Low Drop Out
(LDO) linear regulators that generate 5.0V
© 2014 Exar Corporation
17/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
C
LOCKS AND
T
IMING
Ext Clock Output
GPIO1
÷4/÷8
Reg
Clock
Divider
Freg Mult Reg
DPWM
SEL
PLL
System Clock
Ext Clock Input
GPIO0
Base Frequency
2x
CH1 Timing
x4/x8
Reg
Frequency
Set Reg
4x
Sequencer
To Channels 2→4
Figure 18: XRP7725 Timing Block Diagram
channel then has its own frequency multiplier
register that is used to select its final output
switching frequency.
Figure 18 shows a simplified block diagram of
the XRP7725 timing. Again, please note that
the function blocks and signal names used are
chosen for ease of understanding and do not
necessarily reflect the actual design.
Table 1 shows the available channel switching
frequencies for the XRP7725 device. In
practice the PowerArchitect™ 5.1 (PA 5.1)
design tool handles all the details and the
user only has to enter the fundamental
switching frequency and the 1x, 2x, 4x
frequency multiplier for each channel.
The system timing is generated by a 103MHz
internal system clock (Sys_Clk). There are
two ways that the 103MHz system clock can
be generated. These include an internal
oscillator and a Phase Locked Loop (PLL) that
is synchronized to an external clock input.
The basic timing architecture is to divide the
Sys_Clk down to create a fundamental
switching frequency (Fsw_Fund) for all the
output channels that is settable from 105kHz
to 306kHz. The switching frequency for a
channel (Fsw_CHx) can then be selected as 1
time, 2 times or 4 times the fundamental
switching frequency.
If an external clock is used, the frequencies in
this table will shift accordingly.
To set the base frequency for the output
channels, an “Fsw_Set” value representing
the base frequency shown in Table 1, is
entered
into
the
switching
frequency
configuration register. Note that Fsw_Set
value is basically equal to the Sys_Clk divided
by the base frequency. The system timing is
then created by dividing down Sys_Clk to
produce a base frequency clock, 2X and 4X
times the base frequency clocks, and
sequencing timing to position the output
channels relative to each other. Each output
© 2014 Exar Corporation
18/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Base
Frequency
Available 2x
Frequencies
kHz
Available 4x
Frequencies
kHz
kHz
422.1
429.2
436.4
444.0
451.8
459.8
468.2
476.9
485.8
495.2
504.9
515.0
525.5
536.5
547.9
559.8
572.2
585.2
598.8
613.1
628.0
643.8
660.3
677.6
695.9
715.3
735.7
757.4
780.3
804.7
830.6
858.3
887.9
919.6
953.7
990.4
1030.0
1072.9
1119.6
1170.5
1226.2
211.1
214.6
218.2
222.0
225.9
229.9
234.1
238.4
242.9
247.6
252.5
257.5
262.8
268.2
273.9
279.9
286.1
292.6
299.4
306.5
314.0
321.9
330.1
338.8
348.0
357.6
367.9
378.7
390.2
402.3
415.3
429.2
444.0
459.8
476.9
495.2
515.0
536.5
559.8
585.2
613.1
105.5
107.3
109.1
111.0
112.9
115.0
117.0
119.2
121.5
123.8
126.2
128.8
131.4
134.1
137.0
139.9
143.1
146.3
149.7
153.3
157.0
160.9
165.1
169.4
174.0
178.8
183.9
189.3
195.1
201.2
207.7
214.6
222.0
229.9
238.4
247.6
257.5
268.2
279.9
292.6
306.5
Table 1
© 2014 Exar Corporation
19/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
• Power Group Enable
–
controls
S
UPERVISORY AND CONTROL
enabling and disabling of Group 1 and
Group 2
Power system design with XRP7725 is
accomplished using PA 5.1 design tool. All
figures referenced in the following sections
are taken from PA 5.1. Furthermore, the
following sections reference I2C commands.
For more information on these commands,
refer to ANP-38.
• Power Channel Enable – controls
enabling and disabling of a individual
channel including LDO3.3
• I2C Address Bit – controls an I2C
address bit
• Power OK – indicates that selected
channels have reached their target levels
and have not faulted. Multiple channel
selection is available, in which case the
resulting signal is the AND logic function
of all channels selected
D
IGITAL I/O
XRP7725 has two General Purpose Input
Output (GPIO) and three Power System Input
Output (PSIO) user configurable pins.
• ResetOut – is delayed Power OK. Delay
is programmable in 1msec increments
with the range of 0 to 255 msecs
• Low VCC – indicates when VCC has fallen
below the UVLO fault threshold and
when the UVLO condition clears (VCC
voltage rises above the UVLO warning
level)
• GPIOs are 3.3V CMOS logic compatible
and 5V tolerant.
• Interrupt – the controller generated
interrupt selection and clearing is done
through I2C commands
• PSIOs which configured as outputs are
open drain and require external pull-up
resistors. These I/Os are 3.3V and 5V
CMOS logic compatible, and up to 15V
capable.
Interrupt, Low VCC, Power OK and ResetOut
signals can only be forwarded to a single
GPIO/PSIO.
The polarity of the GPIO/PSIO pins is set in
PA 5.1 or with an I2C command.
In addition, the following are functions that
are unique to GPIO0 and GPIO1.
Configuring GPIO/PSIOs
The following functions can be controlled from
or forwarded to any GPIO/PSIO:
•
HW Flags – these are hardware
monitoring functions forwarded to
GPIO0 only. The functions include
• General Output – set with
an I2C
Under-Voltage
Warning,
Over-
command
Temperature Warning, Over-Voltage
Fault, Over-Current Fault and Over -
Current Warning for every channel.
• General Input – triggers an interrupt;
state read with an I2C command
© 2014 Exar Corporation
20/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Multiple selections will be combined
using the OR logic function.
values can be calculated with the following
equation:
ͩ
͈ ∗ ͍̼͆ʚ͐͡ʛ ∗ 10
ʚ
ʛ
͉͉͊́̾ % Ɣ
͕͙͐ͨͦ͛ͨꢀʚ͐ʛ
Where N=1 to 63 for the PGOOD Max
value and N=1 to 62 for the PGOOD Min
• External
Clock-in
–
enables
the
controller to lock to an external clock
including one from another XRP7725
applied to the GPIO0 pin. There are two
ranges of clock frequencies the controller
accepts, selectable by a user.
value.
For example, with the target
voltage of 1.5V and set point resolution of
2.5mV (LSB), the Power Good min and
max values can range from 0.17% to
10.3% and 0.17% to 10.5% respectively.
A user can effectively double the range by
changing to the next higher output
voltage range setting, but at the expense
of reduced set point resolution.
• External Clock-out – clock sent out
through GPIO1 for synchronizing with
another XRP7725 (see the clock out
section for more information).
F
AULT HANDLING
There are seven different types of fault
handling:
• HW Power Good – the Power Good
hardware monitoring function. It can only
be forwarded to GPIO1. This is an output
voltage monitoring function that is a
hardware comparison of channel output
voltage against its user defined Power
Good threshold limits (Power Good
minimum and maximum levels). It has no
hysteresis. Multiple channel selections will
be combined using the AND logic function
of all channels selected.
• Under
Voltage
Lockout
(UVLO)
monitors voltage supplied to the VCC pin
and will cause the controller to shut down
all channels if the supply drops to critical
levels.
• Over Temperature Protection (OTP)
monitors temperature of the chip and will
cause the controller to shut down all
channels if temperature rises to critical
levels.
• Over
Voltage
Protection
(OVP)
monitors regulated voltage of a channel
and will cause the controller to react in a
user specified way if the regulated voltage
surpasses threshold level.
The Power Good minimum and maximum
levels are expressed as percentages of the
target voltage.
• Over
Current
Protection
(OCP)
monitors current of a channel and will
cause the controller to react in a user
specified way if the current level
surpasses threshold level.
• Start-up
Time-out
Fault
monitors
whether a channel gets into regulation in
a user defined time period
• LDO5 Over Current Protection (LDO5
OCP) monitors current drawn from the
“PGood Max” is the upper window and
“PGood Min” is the lower window. The
minimum and maximum for each of these
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
regulator and will cause the controller to
be reset if the current exceeds LDO5 limit
• LDO3.3 Over Current Protection
(LDO3.3 OCP) monitors current drawn
from the regulator and will cause the
controller to shut down the regulator if the
current exceeds LDO3.3 limit
OTP
User defined OTP warning, fault and restart
levels are set at 5°C increments in PA 5.1.
When the warning level is reached the
UVLO
controller
TEMP_WARNING_EVENT
will
generate
interrupt.
the
In
Both UVLO warning and fault levels are user
programmable and set at 200mV increments
in PA 5.1.
addition, the host can be informed about the
event through HW Flags on GPIO0 (see the
Digital I/O section).
When an OTP fault condition occurs, the
XRP7725 outputs are shut down and the
TEMP_OVER_EVENT interrupt is generated.
When the warning level is reached the
controller
UVLO_WARNING_EVENT
will
generate
interrupt.
the
In
Once temperature reaches a user defined OTP
addition, the host can be informed about the
event through HW Flags on GPIO0 (see the
Digital I/O section).
Restart
TEMP_UNDER_EVENT
Threshold
level,
interrupt
the
be
will
generated and the controller will reset.
When an under voltage fault condition occurs,
the XRP7725 outputs are shut down and the
OVP
UVLO_FAULT_ACTIVE_EVENT
interrupt
is
A user defined OVP fault level is set in PA 5.1
and is expressed in percentages of a
regulated target voltage.
generated. In addition, the host can be
informed by forwarding the Low VCC signal to
any GPIO/PSIO (see the Digital I/O section).
This signal transitions when the UVLO fault
occurs. When coming out of the fault, rising
VCC crossing the UVLO fault level will trigger
the UVLO_FAULT_INACTIVE_EVENT interrupt.
Resolution is the same as for the target
voltage (expressed in percentages). The OVP
minimum and maximum values are calculated
by the following equation where the range for
N is 1 to 63:
Once the UVLO condition clears (VCC voltage
rises above or to the user-defined UVLO
warning level), the Low VCC signal will
transition and the controller will be reset.
ͩ
͈ ∗ ͍̼͆ʚ͐͡ʛ ∗ 10
ʚ
ʛ
͉͐͊ % Ɣ
Special attention needs to be paid in the case
when VCC = LDO5 = 4.75V to 5.5V. Since the
input voltage ADC resolution is 200mV, the
UVLO warning and fault set points are coarse
for a 5V input. Therefore, setting the warning
level at 4.8V and the fault level at 4.6V may
result in the outputs not being re-enabled
until a full 5.0V is reached on VCC. Setting the
warning level to 4.6V and the fault level at
4.4V would likely make UVLO handling as
desired; however, at a fault level below 4.6V
the device has hardware UVLO on LDO5 to
ensure proper shutdown of the internal
circuitry of the controller. This means the
4.4V UVLO fault level may never occur.
͕͙͐ͨͦ͛ͨꢀʚ͐ʛ
When the OVP level is reached and the fault is
generated, the host will be notified by the
SUPPLY_FAULT_EVENT interrupt generated by
the controller. The host then can use an I2C
command to check which channel is at fault.
In addition, OVP fault can be monitored
through GPIO0.
A user can choose one of three options in
response to an OVP event: shut down the
faulting channel, shut down faulting channel
and perform auto-restart of the channel, or
restart the chip.
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
WARNING: Choosing the “Restart Chip”
option during development is NOT
recommended as it makes debug efforts
difficult.
OCP
A user defined OCP fault level is set with 10
mA increments in PA 5.1. PA 5.1 uses
calculations to give the user the approximate
DC output current entered in the current limit
field. However the actual current limit trip
value programmed into the part is limited to
280mV
as
defined
in
the
electrical
characteristics. The maximum value the user
can program is limited by RDSON of the
synchronous
Power
FET
and
current
monitoring ADC range. For example, using a
synchronous FET with RDSON of 30mꢀ, and the
wider ADC range, the maximum current limit
programmed would be:
280͐͡
ʚ ʛ
͉̽͊ꢀ͇͕ͬ ̻ Ɣ
Ɣ 9.33̻
30͡Ω
In the case of shutting down the faulting
channel and auto-restarting, the user has an
option to specify startup timeout (the time in
which the fault is validated) and hiccup
timeout (the period after which the controller
will try to restart the channel) periods in 1
msec increments with a maximum value of
255 msec.
The current is sampled approximately 30ns
before the low side MOSFET turns off, so the
actual measured DC output current in this
example would be 9.33A plus approximately
half the inductor ripple.
An OCP Fault is considered to have occurred
only if the fault threshold has been tripped in
four consecutive switching cycles. When the
switching frequency is set to the 4x multiplier,
the current is sampled only every other cycle.
As a result it can take as many as eight
switching cycles for an over current event to
be detected. When operating in 4x mode an
inductor with a soft saturation characteristic is
recommended.
When the OCP level is reached and the fault is
generated, the host will be notified by the
SUPPLY_FAULT_EVENT interrupt generated by
the controller. The host then can use an I2C
command to check which channel is at fault.
In addition, OCP faults can be monitored
through HW Flags on GPIO0. The host can
also monitor the OCP warning flag through
HW Flags on GPIO0. The OCP warning level is
calculated by PA 5.1 as 85% of the OCP fault
level.
Note: The Channel Fault Action response is
the same for an OVP or OCP event.
A user can choose one of three options in
response to an OCP event: shut down the
faulting channel, shut down faulting channel
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
and perform auto-restart of the channel, or
LDO5 OCP
restart the chip.
When current is drawn from the LDO5 that
exceeds the LDO5 current limit the controller
will be reset.
WARNING: Choosing the “Restart Chip”
option
during
development
is
NOT
recommended as it makes debug efforts
difficult.
LDO3.3 OCP
When current drawn from LDO3.3 exceeds
LDO3.3 current limit the regulator gets shut
down, a fault is generated, and the host will
be notified by the SUPPLY_FAULT_EVENT
interrupt generated by the controller. The
host then can through an I2C command check
which channel/regulator is at fault. Once the
fault condition is removed, the host needs to
turn the regulator on again.
The output current reported by the XRP7725
is processed through a seven sample median
filter in order to reduce noise. The OCP limit
is compared against unfiltered ADC output.
V5EXT SWITCHOVER
The V5EXT gives a user an opportunity to
supply an external 5 Volt rail to the controller
in order to reduce the controller’s power
dissipation. The 5 Volt rail can be an
independent power rail present in a system or
any of 7725 channels regulated to 5 Volts (in
the PFM mode in particular) and routed back
to the V5EXT pin. It is important to mention
that voltage to VCC must be applied all the
time even after the switchover in which case
the current drawn from VCC supply will be
minimal.
For the case of Shutdown and Auto-restart
Channel, the user has an option to specify
startup timeout (the time in which the fault is
validated) and hiccup timeout (the period
after which the controller will try to restart
the channel) periods in 1 msec increments
with a maximum value of 255 msec.
If the function not used, we recommend the
pin to be either grounded or left floating in
conjunction with making sure the function
gets disabled through register settings.
Note: The Channel Fault Action response is
the same for an OVP or OCP event.
V5EXT switchover control
Start-up Time-out Fault
The function is enabled in PA 5.1. The
switchover thresholds are programmable in
50mV steps with a total range of 200mV.
Hysteresis to switch the external 5 Volt
supply in-out is 150mV. LDO5 automatically
turns off when the external voltage is
switched in and turns on when the external
voltage drops below the lower threshold.
A channel will be at Startup Timeout Fault if it
does not come-up in the time period specified
in the “Startup Timeout” box. In addition, a
channel is at Startup Timeout Fault if its pre-
bias configuration voltage is within a defined
value too close to the target.
When the fault is generated, the host will be
notified
by
the
SUPPLY_FAULT_EVENT
interrupt generated by the controller. The
host then can use an I2C command to check
which channel is at fault.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
C
LOCK OUT
XRP7725 can supply clock out to be used by
another XRP7725 controller. The clock is
routed out through GPIO1 and can be set to
system clock divided by 8 (Sys_Clock/8) or
system clock divided by 4 (Sys_Clock/4)
frequencies.
When the controller switches over to the
V5EXT rail, the V5EXT_RISE interrupt is
generated to inform the host. Similarly, when
the controller switches out, the V5EXT_FALL
interrupt gets generated.
The functionality is enabled in PA 5.1 by
selecting External Clock-Out function under
GPIO1.
E
XTERNAL CLOCK SYNCHRONIZATION
C
HANNEL CONTROL
XRP7725 can be run off an external clock
available in the system or another XRP7725.
The external clock must be in the ranges of
10.9MHz to 14.7MHz or 21.8MHz to 29.6MHz.
Locking to the external clock is done through
an internal Phase Lock Loop (PLL) which
requires an external loop capacitor of 2.2nF to
be connected between the CPLL pin and
AGND.
Channels including LDO3.3 can be controlled
independently by any GPIO/PSIO or I2C
command. Channels will start-up or shut-
down following transitions of signals applied
to GPIO/PSIOs set to control the channels.
The control can always be overridden with an
I2C command.
In applications where this functionality is not
desired, the CPLL capacitor is not necessary
and can be omitted, and the pin shall be left
floating. In addition, the user needs to make
sure the function gets disabled through
register settings.
The external clock must be routed to GPIO0.
The GPIO0 setting must reflect the range of
the external clock applied to it: Sys_Clock/8
corresponds to the range of 10.9MHz to
Regardless of whether the channels are
controlled independently or are in a group,
the ramp rates will be followed as specified
(see the Power Sequencing section).
14.7MHz
while
Sys_Clock/4
setting
corresponds to the range of 21.8Mhz to
29.6MHz.
Regulated voltages and voltage drops across
the synchronous FET on each switching
channel can be read back using I2C
commands. The regulated voltage read back
resolution is 15mV, 30mV and 60mV per LSB
depending on the target voltage range. The
voltage drop across synchronous FET read
back resolution is 1.25mV and 2.5mV per LSB
depending on the range.
The functionality is enabled in PA 5.1 by
selecting External Clock-in function under
GPIO0.
For more details on how to monitor PLL lock
in-out, please contact Exar or your local Exar
representative.
Through an I2C command the host can check
the status of the channels; whether they are
in regulation or at fault.
Regulated voltages can be dynamically
changed on switching channels using I2C
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
commands with resolution of 2.5mV, 5mV
Group Selection
and 10mV depending on the target voltage
range (in PWM mode only).
For more information on I2C commands
please refer to ANP-38 or contact Exar or
your local Exar representative.
There are three groups:
• Group 0 – is controlled by the chip
ENABLE or an I2C command. Channels
assigned to this group will come up with
the ENABLE signal being high (plus
additional
delay
needed
to
load
configuration from Flash to run-time
registers), and will go down with the
ENABLE signal being low. The control can
always be overridden with an I2C
command
Since it is recommended to leave the
ENABLE pin floating in the applications
when VCC = LDO5 = 4.75V to 5.5V, please
contact Exar for how to configure the
channels to come up at the power up in
this scenario
• Group 1 – can be controlled by any
GPIO/PSIO or I2C command. Channels
assigned to this group will start-up or
shut-down following transitions of a signal
applied to the GPIO/PSIO set to control
the group. The control can always be
overridden with an I2C command
• Group 2 – can be controlled by any
GPIO/PSIO or I2C command. Channels
assigned to this group will start-up or
shut-down following transitions of a signal
applied to the GPIO/PSIO set to control
the group. The control can always be
overridden with an I2C command
P
OWER SEQUENCING
All four channels and LDO3.3 can be grouped
together and will start-up and shut-down in a
user defined sequence.
Start-up
Selecting none means channel(s) will not be
assigned to any group and therefore will be
controlled independently.
For each channel within a group, a user can
specify the following start-up characteristics:
• Ramp Rate – expressed in milliseconds
per volt. It does not apply to LDO3.3
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
• Order – position of a channel to come-up
within the group
I
NSTANTANEOUS CURRENT MONITORING
XRP7725 will capture VIL readings every
1msec on all channels until a user defined
sample threshold is reached. Then, the sum is
latched into a separate register to be read
from an I2C command.
• Wait PGOOD? – selecting this option for
a channel means the next channel in the
order will not start ramping-up until this
channel reaches the target level and its
Power Good flag is asserted
• Delay – an additional time delay a user
can specify to postpone a channel start-up
with respect to the previous channel in the
order. The delay is expressed in
milliseconds with a range of 0msec to
255msec
Shut-down
The sample size is selected in Power Architect
5.1 (PA 5.1). The recommended maximum
sample size is 512. Going over this limit could
potentially cause overflow. In certain designs
it would be possible to increase sample size
above this limit without problems, but this will
depend on the design parameters. If there is
For each channel within a group a user can
specify
the
following
shut-down
characteristics:
• Ramp Rate – expressed in milliseconds
per volt. It does not apply to LDO3.3
• Order – position of a channel to come-
down within the group
• Wait Stop Thresh? – selecting this
option for a channel means the next
channel in the order will not start
ramping-down until this channel reaches
the Stop Threshold level. The stop
threshold level is fixed at 600mV
such
a
need
please
contact
Exar
representatives who will determine if your
design is suitable.
• Delay – additional time delay a user can
specify to postpone a channel shut-down
with respect to the previous channel in the
order. The delay is expressed in
milliseconds with a range of 0msec to
255msec
MONITORING VCC AND TEMPERATURE
Through I2C commands, the host can read
back the voltage applied to the VCC pin and
the die temperature respectively. The VCC
read back resolution is 200mV per LSB; the
die temperature read back resolution is 5C°
per LSB. For more on I2C commands please
refer to ANP-38.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
The internal counter can be reinitialized by
reading from the following I2C command:
0x70 (VIL_ACC_INIT) – Accumulator Initialization
These I2C commands follow the same
command structure as the commands
described in ANP-38.
Once the host reads the accumulated sum, it
will need to do some post data processing in
order to get an average load current.
First, the host has to divide the read sum by a
number of samples to obtain an average VIL
register value.
Secondly, the average VIL register value
needs to be translated into a load current.
Translating average VIL register value
into a load current
To adjust for the gain and offset of the sense
circuit the average VIL register value needs to
be converted to VIL. That can be done with
the following equation:
The host should time its reading frequency to
match the sample window size. A GPIO/PSIO
can be configured in PA 5.1 to indicate to the
host each time a new accumulated sum has
been latched.
DEC
(
R _Value
)
IFE _ Gain
*0.01
VGL _ RTN −VLX =VIL =
− 0.04
Equation 1
where IFE_Gain is a gain setting of the sense
circuit. The IFE_Gain equals to 8 if Gain 8 of
the sense circuit is enabled, else IFE_Gain is
4.
PA 5.1 sets the gain based on RDSON, IOUTMAX
values entered, and current sense ADC range.
The IFE_Gain value can be obtained by
reading register 0xD016 via the PA 5.1 Peek
Poke function. This is a four bit register with
following bit description:
The IO will be asserted after all samples have
been taken and held while the accumulated
values are being latched.
Bit 0 – IFE_Gain 8 setting for channel 1
Bit 1 – IFE_Gain 8 setting for channel 2
Bit 2 – IFE_Gain 8 setting for channel 3
Bit 3 – IFE_Gain 8 setting for channel 4
Reading of the accumulated sum is done
using following I2C commands:
0x71 (VIL_ACC_READ_CH1) – CH1 Accumulator
0x72 (VIL_ACC_READ_CH2) – CH2 Accumulator
0x73 (VIL_ACC_READ_CH3) – CH3 Accumulator
0x74 (VIL_ACC_READ_CH4) – CH4 Accumulator
Value 1 indicates gain 8 setting while value 0
indicates gain 4.
Reading this register from customer software
requires implementation of I2C register read
command structure described in ANP-39.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
The flash equivalent of this register is 0x156
if obtaining the value from flash HEX image is
preferred.
Since VIL is
a
voltage sensed across
synchronous Power FET during its on time,
the current through will be:
VIL
I =
RDSON
Equation 2
where RDSON is channel resistance of the
synchronous Power FET entered as a channel
parameter in PA 5.1.
In addition, XRP7725 samples VIL at valley of
the inductor current which means one half of
the inductor ripple current has to be added to
current in equation 2 in order to get an
average inductor current (load current).
Inductor ripple current is calculated as:
The function displays load currents calculated
as described in the section above. In addition,
it gives a user an opportunity to make
adjustments to RDSON (KR) and ripple current
offset (KO).
(VIN −VOUT )*VOUT
VIN * fSW * L
IPeak −Peak −Ripple
=
(
)
Equation 3
where VIN, VOUT, fSW and L are channel
parameters entered in PA 5.1.
Finally, the load current is a sum of the valley
current (equation 2) and one half of the
inductor ripple current (equation 3).
IPeak−Peak−Ripple
ILoad = ILValley
+
2
Equation 4
the calculated load
Note:
current
is
dependent on parameters entered in PA 5.1.
RDSON and L are the most significant since
they will change noticeably depending on
operating conditions. Because of this,
calibrating RDSON and L can greatly improve
accuracy. For more on RDSON and L calibration
techniques refer to ANP-43.
The default value of KR is 1. PA 5.1 will
calculate KO based on entered design
parameters such as VIN, VOUT, fSW and L. The
calculated KO can be recalled by clicking on
“Choose Suggested KO.”
XRP7725 TELEMETRY IN PA 5.1
PA 5.1 adds a new function under the
dashboard called XRP7725 Telemetry.
Once the design has been calibrated, saving
the project file (.pwrxr) will save KR and KO
for later use as well.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
The scale and sample values will always
reflect what is saved in a project file. PA 5.1
will also read actual register values and report
discrepancies highlighted in red if there exist
during design development.
C
URRENT READING ACCURACY
An important advantage of averaging current
readings across a large sample size is that a
distribution gets much tighter compared to
current reading through I2C bus in XRP7724.
The accuracy specification in the electrical
table
includes
quantization
noise.
Quantization noise is divided down by the
square root of the number of samples taken
by the accumulator.
For example, if 400
samples are taken, the quantization noise is
reduced by a factor of 20. The result below
shows how the current reading is much
improved whether the noise is from the board
or quantization noise.
By clicking on the Flash button, user will start
programming sequence of the design
configuration into the Flash NVM. After the
programming sequence completes, the chip
will reset (if automatically reset After Flashing
box is checked), and boot the design
configuration from the Flash.
PROGRAMMING XRP7725
XRP7725 is a FLASH based device which
means its configuration can be programmed
into FLASH NVM and re-programmed a
number of times.
Programming of FLASH NVM is done through
PA 5.1.
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Short duration Enable pin toggled low
Short duration shutdown pulses to the
ENABLE pin of the XRP7725, which do not
provide sufficient time for the LDO5 voltage
to fall below 3.5V, can result in significant
delay in re-enabling of the device. Some
examples below show LDO5 and ENABLE
pins:
For users that wish to create their own
programming procedure so they can re-
program Flash in-circuit using their system
software, please contact Exar for a list of I2C
Flash Commands needed.
E
NABLING XRP7725
XRP7725 has a weak internal pull-up ensuring
it gets enabled as soon as internal voltage
supplies have ramped up and are in
regulation.
No load on LDO5, blue trace. Recovery time
after ENABLE logic high is approximately
40ms.
Driving the Enable pin low externally will keep
the controller in the shut-down mode. A
simple open drain pull down is the
recommended way to shut XRP7725 down.
If the Enable pin is driven high externally to
control XRP7725 coming out of the shut-down
mode, care must be taken in such a scenario
to ensure the Enable pin is driven high after
VCC gets supplied to the controller.
In the configuration when VCC = LDO5 =
4.75V to 5.5V, disabling the device by
grounding
the
Enable
pin
is
not
recommended. At this time we recommend
leaving the Enable pin floating and placing the
controller in the “Standby Mode” instead in
this scenario. The standby mode is defined as
the state when all switching channels and
LDO3.3 are disabled, all GPIO/PSIOs are
programmed as inputs, and system clock is
disabled. In this state chip consumes 440uA
typical.
Adding a 200 ohm load on LDO5 pulls voltage
below 3.5V and restart is short.
Note that as VCC increases, the restart time
falls as well. 5.5V input is shown as the worst
case.
Since the ENABLE pin has an internal current
source, a simple open drain pull down is the
recommended way to shut down the
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
XRP7725. A diode in series with a resistor
between the LDO5 and ENABLE pins may
offer a way to more quickly pull down the
LDO5 output when the ENABLE pin is pulled
low.
the system, then the power loss will increase
significantly and proper thermal design
APPLICATION INFORMATION
becomes critical.
For lower power levels
T
HERMAL DESIGN
using properly sized MOSFETs, the use of the
internal 5V regulator as a gate drive supply is
considered appropriate.
As a four channel controller with internal
MOSFET drivers and 5V gate drive supply all
in one 7x7mm 44pin TQFN package, there is
the potential for the power dissipation to
exceed the package thermal limitations. The
XRP7725 has an internal LDO which supplies
5V to the internal circuitry and MOSFET
LAYOUT GUIDELINES
Refer to application note ANP-32 “Practical
Layout Guidelines for PowerXR Designs and
ANP-35 “XRP77XX: Extending the MOSFET
Gate Drive Conductors”.
drivers during startup.
It is generally
expected that either one of the switching
regulator outputs is 5V or another 5V rail is
available in the system and connected to the
5 Volt EXT pin. If there is no 5V available in
© 2014 Exar Corporation
32/34
Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
PACKAGE SPECIFICATION
44-PIN 7X7MM TQFN
© 2014 Exar Corporation
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Rev. 1.0.0
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
REVISION HISTORY
Revision
Date
Description
01/27/2014
Initial Release [ECN# 1406-03]
1.0.0
FOR FURTHER ASSISTANCE
Email:
customersupport@exar.com
powertechsupport@exar.com
Exar Technical Documentation:
http://www.exar.com/TechDoc/default.aspx?
E
XAR CORPORATION
H
EADQUARTERS AND
SALES OFFICES
48720 Kato Road
Fremont, CA 94538 – USA
Tel.: +1 (510) 668-7000
Fax: +1 (510) 668-7030
www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,
is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in
writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all
such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
© 2014 Exar Corporation
34/34
Rev. 1.0.0
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