XRS10L120IL-F中文资料_数据手册_规格书

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

JUNE 2009

FEATURES

test and loopback features is achieved in a low cost

and lower power implementation.

G

•

ENERAL FEATURES

The port multiplier function is used when one active

host has to communicate with multiple SATA drives.

The XRS10L120 supports up to 2 SATA drives and

utilizes the full bandwidth of the host connection.

Three independent 3/1.5Gbps SATA ports.

Connects 1 host port to 2 device ports.

•

Supports 3/1.5Gbps rate detection/speed

negotiation.

The XRS10L120 includes enhanced features such as

staggered HDD spin-up, power management control,

hot plug capability and support for legacy software.

The XRS10L120 acts as a retimer, maintaining

independent signaling domains between the drives,

hosts and the external interconnect.

•

Supports power down modes - Active, partial,

slumber and power down.

Advanced features configurable through MDIO

bus.

The high-speed serial input feature: selectable

equalization and the high-speed serial output feature:

programmable pre-emphasis can be used to

compensate for ISI (Inter-Symbol Interference) and

increase maximum cable distances.

P

ORT MULTIPLIER LOGIC FEATURES

•

Low latency architecture.

•

Supports OOB signaling for SATA applications.

Internal OOB detectors for COMRESET/

COMINIT and COMWAKE.

XRS10L120 meets tight jitter budgets in SATA

applications. Exar's serial I/O technology enables

reliable data transmission over 1 meter of FR-4 and 4

meters of unequalized copper cable.

H

IGH SPEED I/O FEATURES

•

High speed outputs with programmable pre-

emphasis to drive long interconnects.

Host and drive port speeds can be mixed and

matched, based upon inherent data rate negotiation

present in the SATA II specifications.

•

Selectable high speed input equalization for

optimum reception.

Compliant with SATA Gen-2i

specification.

&

Gen-2m

The MDIO bus allows simple configuration of the

XRS10L120 when needed. Receive equalization,

transmit amplitude and pre-emphasis and SSC

control are all configurable via the 2-wire MDIO

interface

Enables reliable data transmission over 1 meter

of FR-4 and 4 meters or more of unequalized

copper cable.

To summarize, the port multiplier functionality in the

XRS10L120 allows the system designer to increase

the number of serial ATA connections in an enclosure

that does not have a sufficient number of serial ATA

connections for all of the drives in the enclosure.

•

Supports spread spectrum clocking (SSC) to

reduce EMI.

P

•

HYSICAL FEATURES

CMOS 0.13 Micron Technology

Single 1.2 V Power Supply

STANDARDS COMPLIANCE

-40°C to 85°C Industrial Temperature Range

No heatsink or airflow required

64-Pin QFN Package

The XRS10L120 is compliant with the following

industry specifications:

•

Serial ATA, Revision 1.0a

1.0 INTRODUCTION

Serial ATA II: Extensions to Serial ATA 1.0a,

Revision 1.2

The XRS10L120 provides the advantages of the

Serial ATA II Port Multiplier implementations for Serial

ATA II systems at 3.0 Gbps and 1.5 Gbps. The

XRS10L120 offers a leading solution for propagation

of high data rate Serial ATA products in a wide variety

of applications. The integration of Serial ATA PHY

links, a variety of digital logic capabilities, rate adjust

FIFOs, integrated low-cost clock oscillator support,

•

Serial ATA II PHY Electrical Specifications,

Revision 1.0

•

Serial ATA II: Port Multiplier, Revision 1.2

Serial ATA II: Revision 2.6

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

APPLICATIONS

REV. 1.06

•

Serial ATA Enclosures

Other Serial ATA link replicator applications

Buffers for externally connected links

High density storage boxes

RAID Subsystems

APPLICATION EXAMPLE

The XRS10L120 is ideally suited for use within an external drive enclosure as a means of providing redundant

host access to ensure system availability and reliability, while enabling access to up to four target devices per

XRS10L120. This application is shown in Figure 1. Other applications for the XRS10L120 include use in fixed-

content or network attached storage systems, storage arrays, desktop applications or entry-level servers,

RAID storage or disk-to-disk backup.

FIGURE 1. SYSTEM BLOCK DIAGRAM FOR XRS10L120 IN A DRIVE ENCLOSURE APPLICATION

DRIVE ENCLOSURE

SATA

XRS10L120

PORT MULTIPLIER

SATA

XRS10L120

PORT MULTIPLIER

SATA

2

EXSTOR XRS10L120

REV. 1.06

IGURE 2. PINOUT OF THE XRS10L120

SERIAL ATA II: PORT MULTIPLIER

F

1

2

48 DRACT1

47 VSS

TCK

TMS

TDO

3

46 SOTN0

45 SOTP0

44 VDD

4

TDI

TRST

5

VSS

MDC

VSS

6

43 SORN0

42 SORP0

7

XRS10L120

64-pin QFN

VSS

8

41

40

39

VSSA

VDDA

MDIO

VSS

9

10

11

12

13

14

15

16

38 VSS

VDD

37 SORP1

36 SORN1

35 VDD

VSS

VDD

VSS

VDD

34 SOTP1

33 SOTN1

CLKSTN

3

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

2.0 PIN DESCRIPTIONS

REV. 1.06

TABLE 1: XRS10L120 PIN

D

ESCRIPTIONS

Pin Name

Pin Number

64 QFN

I/O

Type

DESCRIPTION

DATA INTERFACE

SOTP0/SOTN0

SOTP1/SOTN1

45, 46

34, 33

CML

AC

O

I

Coupled Serial ATA Output Transmitters. These ports communicate

from the XRS10L120 to downstream devices

SORP0/SORN0

SORP1/SORN1

42, 43

37, 36

Serial ATA Input Receivers. These ports receive signals from

downstream devices

SITP/SITN

SIRP/SIRN

62, 63

59, 60

Serial ATA Output Transmitters. These ports communicate

from the XRS10L120 to upstream hosts.

O

I

Serial ATA Input Receivers. These ports receive signals from

upstream hosts.

CLOCK

I

NTERFACE

CMU_REFP/

CMU_REFN

25, 26

CML

AC

Reference clock input

Coupled

XOD

XOG

22

23

O

I

Analog

Crystal oscillator output

Crystal oscillator input, 1.26V max

MDIO INTERFACE

SIGNALS

MDC

7

9

I

LVCMOS MDIO clock input, +3.3V LVCMOS

LVCMOS MDIO data port, +3.3V LVCMOS. Open drain

JTAG Interface Signals

MDIO

I/O

TCK

TDI

1

4

3

I

LVCMOS JTAG test clock, +3.3V LVCMOS

JTAG test data in, +3.3V LVCMOS

TDO

O

JTAG test data out, +3.3V LVCMOS. Open drain. If used to

daisy chain JTAG devices, pull up externally using 3.3KOhm

resistor.

TMS

2

5

I

JTAG mode select, +3.3V LVCMOS

TRST

JTAG test reset, +3.3V LVCMOS. Pull low externally using

3.3KOhm resistor for normal operation of the device

G

ENERAL

CONTROL AND

CONFIGURATION

S

IGNALS (CMOS)

RBIAS

RESETB

PWRDNB

28

50

31

I

Analog

Connection point for calibration termination resistor.

LVCMOS Active low reset pin, +3.3V LVCMOS.

LVCMOS Active low power down signal for chip, +3.3V LVCMOS.

4

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 1: XRS10L120 PIN

DESCRIPTIONS

Pin Name

Pin Number

64 QFN

I/O Type

DESCRIPTION

DRACT[1:0]

48, 49

O

LVCMOS Drive activity port for external LED. Active Low, 3.3V LVC-

MOS, open drain

TEST PINS

ANTEST

30

O

Analog

Analog test pin

CLKSTN/

CLKSTP

16, 17

CML

AC

Output clock test pin

Coupled

R

ESERVED PINS

NC

51

20

No Connect

LVCMOS For factory use only. connect to ground.

SCANMODE

I

P

OWER AND GROUND SIGNALS

VDD

11, 13, 15,

19, 35, 44,

54, 61

1.2V supply.

VDDA

VSS

24, 29, 39, 56

I

1.2V Analog supply.

Ground.

6, 8, 10, 12,

14, 18, 32,

38, 41, 47,

52, 53, 55,

58, 64

VSSA

21, 27, 40, 57

I

Analog Ground.

5

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

3.0 FUNCTIONAL DESCRIPTION

REV. 1.06

A top-level view of the XRS10L120 is shown in Figure 3 outlining the interfaces to the device and the required

support components. The data path can be seen at the top of the device. This includes the output transmit and

input receive paths at the top left, providing the upstream interface to the host, and the two output transmit and

input receive paths at the top right, providing the downstream interface to the target devices. The clocking,

control, and configuration interfaces are shown below the dotted line.

FIGURE 3. XRS10L120 INTERFACES

SIT_P/N

SIR_P/N

Serial ATA Upstream

Interface to HBAs

Serial ATA Downstream

Interface to Devices

SOT_P/N[1:0]

SOR_P/N[1:0]

DRACT[1:0]

CMU_REF_P/N

Reference Clock

Control and

Status

Interface

PS_SIDEBAND_B

PORTSEL

XOD

XOG

Crystal Oscillator I/O

RESETB

PWRDNB

TCK

TDI

MDC

JTAG

Interface

Configuration

Interface

TDO

TMS

TRST

MDIO

RBIAS

VDDA

Calibration Resistor

49.9Ω ±

0.5%

The XRS10L120 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This

common building block provides a uniform implementation with common characteristics and a common

register map, but provides a functional implementation of independent PHY blocks. Digital logic

implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data

path within the XRS10L120. In addition, management and control interfaces including an MDIO interface for

6

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the

device. A block diagram of the XRS10L120 is shown in Figure 4.

FIGURE 4. XRS10L120 BLOCK DIAGRAM

SATAII

LINK

LAYER

SOT0

SOR0

SATAII

3GPHY

SATAII

LINK

LAYER

RATE

ADJUST

FIFO

SIR

SIT

SATAII

3GPHY

SATAII

LINK

LAYER

SOT1

SOR1

SATAII

3GPHY

PORT

MULTIPLIER

7

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

3.1

Out Of Band Feature

Each Serial ATA link provides full support for the three Out Of Band (OOB) signals supported by Serial ATA:

COMRESET, COMINIT and COMWAKE. These sequences must be separated by idle periods as shown in

Figure 5. The sequences are comprised of 106.7ns bursts of activity that are interleaved with varying length

stretches of electrical idle. This alternating sequence must be repeated four times to be recognized.

FIGURE 5. COMWAKE AND COMRESET/COMINIT SEQUENCES

106.7ns

COMWAKE

106.7ns

COMRESET

COMINIT

320ns

An example OOB sequence and the resulting burst and idle widths are shown in Figure 6. If the sequence of

burstWidth and idleWidth counts falls within the range specified in the MDIO registers for four consecutive

burst/idle sequences, then the link will assert COMINIT or COMWAKE. This OOB signal will remain asserted

for as long as the corresponding sequence on the input pins continues.

FIGURE 6. EXAMPLE OOB SEQUENCE

rxdP, rxdN

squelchClock

15

burstWidth

idleWidth

17

COMINT = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxInitWidth≥idleWidth≥MinInitWidth)

COMWAKE = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxWakeWidth≥idleWidth³MinWakeWidth)

8

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

3.2

Power Down Modes

The XRS10L120 features independent support for the 3 transceiver power modes, as follows:

•

Active: All parts of the transceiver are active. All power-down signals are de-asserted.

Partial: In partial mode, the input and output pipelines are shut down, but the PLL and the OOB generation

circuits are active.

•

Slumber: In slumber mode, the PLL is also shut down, saving additional power but adding latency on exit.

The XRS10L120 transceiver components (transmitter, receive CDR, PLL, etc.) can be powered down through

MDIO register settings. Please refer to Table 12, “Powerdown Registers (MDIO Devices 1 & 2),” on

page 27

The XRS10L120 does not support Link Power Management as defined in the SATA standard revision 2.6.

3.3

Speed Negotiation

The XRS10L120 will automatically perform speed negotiation with the host and devices in order to verify

whether the second generation Serial ATA 3.0 Gbps data rate is available or whether the system will need to

fall back upon the first generation Serial ATA 1.5 Gbps data rate. Speed negotiation is performed on an

independent basis by each of the dual-channel macros. Speed negotiation is done independently on all host

and device ports by default. MDIO configuration can request a common negotiated speed on the host and

device ports if such a speed exists. To perform speed negotiation with a downstream device, the XRS10L120

will first perform a COMRESET/COMINIT handshake with the device and then performs a calibrate/

COMWAKE handshake. Following receipt of the device COMWAKE signal, the XRS10L120 will continually

send out a D10.2 signal while awaiting receipt of the device ALIGN primitive. Depending on the speed of the

ALIGN primitive, the XRS10L120 will be able to determine the PHY generation of the device, and provide the

appropriate 1.5 Gbps or 3.0 Gbps ALIGN primitive in return to the device, thus completing speed negotiation.

This process is outlined in Figure 7.

FIGURE 7. SERIAL ATA SPEED NEGOTIATION

For speed negotiation with an upstream host, after the COMRESET/COMINIT and COMWAKE handshake is

complete, the XRS10L120 will initially send out an ALIGN primitive at the 2nd generation 3.0 Gbps data rate. If

no confirming 3.0 Gbps ALIGN primitive is received from the host, the XRS10L120 will then step down and

attempt negotiation at the lower 1.5 Gbps data rate.

3.4

Port Multiplier Implementation

9

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

The XRS10L120 provides full support for the functionality outlined in the Serial ATA II Port Multiplier

specification. A Serial ATA II Port Multiplier is a mechanism for one active host connection to communicate

with multiple devices. A Port Multiplier is conceptually a simple multiplexer in which one active host connection

is multiplexed to multiple device connections.

The XRS10L120 uses four bits, known as the PM Port field in all Serial ATA frame types, to route frames

between the selected host and the appropriate device. PM ports 0 through 1 are valid device ports within the 2-

output XRS10L120, while PM port 15 is designated for communication between the host and the XRS10L120

itself. For host-to-device transactions, the PM Port field is designated by the host in order to specify which

device the frame is intended for. For device-to-host transactions, the XRS10L120 fills in the PM Port field with

the port address of the device that is transmitting the frame.

The PM Port field is defined in the Serial ATA port multiplier specification to be the first 32-bit Dword in the

Frame Information Structure (FIS) for all FIS types, as shown in Figure 8.

FIGURE 8. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS

As defined in Serial ATA1.0

PM Port

FIS Type

3.4.1

Transmission from a host to a device

A host indicates the target device for receipt of a transmitted frame by setting the PM Port field in the frame to

the device's port address. When an XRS10L120 receives a frame from the host, it checks the PM Port field in

the frame to determine which port address should be used. If the frame is set for transmission to the control

port (15), the XRS10L120 receives the frame and performs the command or operation requested. If the frame

is designated for a device port, the XRS10L120 obeys the following procedure:

1. The XRS10L120 first determines if the device port is valid. If the device port is not valid, the XRS10L120

will issue a SYNC primitive to the host and terminate reception of the frame.

2. The XRS10L120 determines if the X bit is set in the device port's PSCR[1] (SError) register. If the X bit is

set, the XRS10L120 issues a SYNC primitive to the host and terminates reception of the frame.

3. The XRS10L120 determines if a collision has occurred. A collision occurs when a reception is already in

progress from the device that the host wants to transmit to. If a collision has occurred, the XRS10L120 will

finish receiving the frame from the host and will then issue an R_ERR primitive to the host as the ending

status. The XRS10L120 will then discard the frame, but will not return an R_RDY primitive to the host until

the frame from the affected device port has been transmitted to the host, thus indicating to the host when it

can retry to send the frame. The transmission from the device will proceed as requested, as the device will

always take collision precedence over the host.

4. The XRS10L120 initiates a transfer with the device by issuing an X_RDY primitive to the device. A collision

may occur as the XRS10L120 is issuing the X_RDY to the device if the device has started transmitting an

X_RDY primitive to the XRS10L120, indicating a decision to start a transmission to the host. In this case,

the XRS10L120 will finish receiving the frame from the host and then issue an R_ERR primitive to the host

to indicate an unsuccessful transmission. The transmission from the device will proceed as requested, as

the device will always take collision precedence over the host.

5. After the device issues an R_RDY primitive to the XRS10L120, the XRS10L120 will transmit the frame

from the host to the device. The XRS10L120 will not send an R_OK status primitive to the host until the

device has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status

handshake is interlocked from the device to the host.

If an error is detected during any part of the frame transfer, the XRS10L120 will ensure that the error condition

is propagated to the host and the device. If no error occurs during frame transfer, the XRS10L120 will not alter

the contents of the frame, or modify the CRC in any way.

10

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

3.4.2

Transmission from a device to a host

A device indicates a transmit to a host in the same way as would be done if the host and device were attached

directly. This transaction obeys the following procedure:

1. After receiving an X_RDY primitive from the device, the XRS10L120 will determine if the X bit is set in the

device port's PSCR[1] (SError) register. The XRS10L120 will not issue an R_RDY primitive to the device

until this bit is cleared to zero.

2. The XRS10L120 will then receive the frame from the device. The XRS10L120 will fill in the PM Port field

with the port address of the transmitting device. The XRS10L120 will then check the CRC received from

the device, and if valid, it will recalculate the CRC based upon the new PM Port field. If the CRC calculated

from the device is incorrect, the XRS10L120 will corrupt the CRC sent to the host to ensure propagation of

the error condition

3. The XRS10L120 will issue an X_RDY primitive to the host to start the transmission of the frame to the host.

After the host issues an R_RDY primitive to the XRS10L120, the frame from the device, with the updated

CRC, will then be transmitted to the host. The XRS10L120 will not send an R_OK status primitive to the

device until the host has issued an R_OK primitive to indicate successful frame reception. In this way, the

R_OK status handshake will be interlocked from the device to the host.

If an error is detected during any part of the frame transfer, the XRS10L120 will ensure that the error condition

is propagated to the host and the device.

11

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

3.5

Clocking

The XRS10L120 allows the use of either an external reference clock or of a low cost crystal oscillator to act as

a reference clock. Separate device inputs are available for each approach, with full rate reference clock inputs

provided on pins CMU_REFP and CMU_REFN, and crystal oscillator inputs provided on pins XOD and XOG.

Supported data rates and their appropriate PLL divide factors are outlined in Table 2.

TABLE 2: PLL DIVIDE FACTORS

DINCLK

S

ERIAL

D

ATA

ATE

M

ODE

S

YSCLK

/REF

/FB

RXCLK

300MHz

CLOCK

R

SATA Gen. 2

25MHz

75MHz

1

2

1

60

20

30

10

1.5GHz

3.0Gbps

*

100MHz

150MHz

NOTE: * All link start with 3.0Gbps, then negotiate down to 1.5Gbps for SATA Generation 1 devices.

3.5.1

Spread Spectrum Clocking

The XRS10L120 provides full support for receipt and generation of signals that have been configured for

Spread Spectrum Clocking (SSC) support. The spread technique is implemented by down-spreading the data

rate by 0.5% as a means of reducing EMI. Generation of the down-spread clock is performed within the

XRS10L120. An example of the resultant spectral fundamental frequency before and after SSC can be seen in

Figure 9.

FIGURE 9. SPREAD SPECTRUM CLOCKING

12

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

4.0 ELECTRICAL SPECIFICATIONS

This section contains the electrical specifications for the XRS10L120.

4.1

Serial ATA Specifications

The XRS10L120 electrical transmit and receive specifications are outlined in this section. The XRS10L120 is

fully compliant to the Serial ATA II specification for Gen2i, Gen2x, Gen2m, Gen1i, Gen1x and Gen1m

variations at 3.0 and 1.5 Gbps.

4.1.1

Serial ATA Transmitter

A simplified version of the output circuit and test fixture for each of the 3 Serial ATA transmit output pairs on the

XRS10L120 is shown in Figure 10. The output differential pair is terminated to the supply VDD. The circuit is

designed to be AC coupled.

FIGURE 10. SERIAL ATA EQUIVALENT OUTPUT CIRCUIT

The XRS10L120 Serial ATA outputs include a simple one-tap equalizer, that is useful in driving longer printed

circuit traces and is a required component in second generation Serial ATA PHYs. This equalizer pre-

emphasizes the output signal whenever there is a data transition. The amount of pre-emphasis can vary

between 0 and 45.5%, and is configured via MDIO register settings. Note that pre-emphasis doesn't increase

the overall swing, but instead reduces the output amplitude when there is no transition.

13

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

FIGURE 11. EFFECTS OF TRANSMIT PRE-EMPHASIS

The overall swing level can also be modified via MDIO register settings. The XRS10L120 transmit mask is

shown in Figure 12.

FIGURE 12. TRANSMIT

EYE

M

ASK FOR

S

ERIAL ATA OUTPUT

14

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

4.1.2

Serial ATA Receiver

An equivalent circuit for the XRS10L120 Serial ATA inputs is shown in Figure 13. The device receiver mask is

shown in Figure 14. This circuit is designed to be AC coupled. The termination resistors are not connected

during power-up

FIGURE 13. SERIAL ATA EQUIVALENT INPUT CIRCUIT

FIGURE 14. RECEIVE EYE MASK FOR SERIAL ATA INPUT

15

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 3: SERIAL ATA LINK

SPECIFICATIONS

NAME

DESCRIPTION

M

IN

.

NOM

MAX

UNITS

t

Bit Time

670

0.32

0.18

-

333

-

ps

BIT,XS

J

Input Jitter Tolerance Mask at signal crossover

Deterministic jitter tolerance at signal crossover

Output jitter mask at signal crossover

-

UI

XR1

J

-

XR1,DJ

J

-

0.15

0.07

0.46

0.41

350

XT1

J

Deterministic output jitter at signal crossover

Input signal rise/fall times (20% - 80%)

Output signal rise/fall times (20% - 80%)

RX to sysclock frequency offset tolerance

-

XT1,DJ

t /t

0.2

-5350

-

R F

t

/t

-

QR QF

1

0

ppm

t

TOL,RX

V

Input swing, differential peak-peak

Output swing, differential peak-peak

175

800

-

1600

1200

mV

IN

2

V

SW

V

No swing detection threshold

Differential mode input resistance

Common mode input resistance

65

85

40

120

100

50

155

115

60

mV

Ω

IN,IDLE

R

IN,DIFF

3

Ω

R

IN,CM

Common mode input resistance, no power

Output termination resistance

200

40

12

6

-

50

-

60

-

kΩ

IN,OFF

R

Ω

IN,XS

11,IN,DIFF

S

Differential input return loss, 50MHz - 1.5GHz

Common mode input return loss 50MHz-1.5GHz

Differential output return loss 50MHz-1.5GHz

Common mode output return loss 50MHz-1.5GHz

Setup time for register port

dB

ns

S

-

11,IN,CM

S

12

6

-

22,OUT,DIFF

S

-

22,OUT,CM

t

1.5

0

-

S,REG

H,REG

Q,REG

t

Hold time for register port

-

t

Clock to Q time for register port

-

2

-

t

Register port clock cycle time

10

4

-

CYC,REG

t

R register port clock high time

-

HI,REG

t

Register port clock low time

4

-

LO,REG

t

Register port input rise/fall time

-

0.5

RF,REG

NOTES

:

1. This value includes 0.5% downspread Spread Spectrum clocking, plus 350ppm tolerance around the center

frequency.

2. This is measured at the package ball and does not include any board or connector loss.

3. This value can be as low as 5Ω during power on.

16

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

4.2

CMOS Interface

AC and DC specifications for the CMOS inputs and outputs are listed in Table 4. Since all these signals are

asynchronous, there are no setup or hold times defined. The CMOS pins are defined in the General Control

and Configuration portion of Table 1 in Section 3, "Pin Descriptions".

TABLE 4: CMOS I/O SPECIFICATIONS

NAME

DESCRIPTION

M

IN

NOM

MAX

UNITS

t

/t

CMOS input signal rise/fall times (20% - 80%)

0.2

-0.3

1.7

-0.3

2.3

10

-

5

ns

DR DF,CMOS

t

_QR/t_QF,CMOS1 CMOS output signal rise/fall times (20% - 80%)

-

5

0.8

3.6

0.4

3.6

20

10

8

ns

V

CMOS input low voltage

CMOS input high voltage

CMOS output low voltage

Open Drain Pull-up Voltage

Output current for VOL = 0.4V

Output current rate of change

CMOS I/O inductance

0

IL,CMOS

IH,CMOS

OL,CMOS

V

3.3

-

V

PULLUP

I

-

mA

mA/ns

nH

OL,CMOS

dI /dt,

-10

-

OL

CMOS

L

I,CMOS

C

CMOS I/O capacitance

-

5

pF

I,CMOS

I

_LEAKAGE2

CMOS I/O Leakage Current

150

uA

N

OTE: .1. This value is measured driving a load of 20pF.

OTE: .2. This values is measured at 2.5 VDC.

N

4.3

MDIO Interface

The Management Data Input/Output (MDIO) port complies with Clause 45 of the IEEE 802.3ae specification. A

representative MDIO driver/receiver is shown in Figure 15. MDIO uses an open drain driver with a pullup

resistor.

17

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

FIGURE 15. REPRESENTATIVE MDIO CIRCUIT

2.5V/3.3V

To other MDIO Devices

Open Drain

Driver

Representative MDIO Read and Write waveforms are shown in Figure 16. The XRS10L120 samples MDIO on

the rising edge of MDC for input and drives MDIO after the rising edge of MDC for output. Note that setup,

hold, and output timings are defined from the maximum vIL and minimum VIH levels.

FIGURE 16. MDIO INPUT AND OUTPUT WAVEFORMS

Values for MDIO parameters are shown in Table 5

18

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 5: MDIO DC AND AC CHARACTERISTICS

NAME

DESCRIPTION

M

IN

NOM

M

AX

UNITS

t

MDC cycle time

MDC low time

MDC high time

400

160

10

-

ns

CYCLE,MDIO

t

-

ns

LOW,MDC

t

HIGH,MDC

1

MDIO input to MDC setup time

MDC to MDIO input hold time

MDC to MDIO output time

t

S,MDIO

H,MDIO

Q,MDIO

2

3

10

0

-

ns

t

150

t

/t

MDIO input signal rise/fall times (20% - 80%)

MDIO output signal rise/fall times (20% - 80%)

0.2

-

100

80

ns

DR DF,MDIO

4

t

/t

QR QF,MDIO

V

MDIO input low voltage

MDIO input high voltage

MDIO output low voltage

-0.3

1.7

0

0.8

3.6

0.4

V

IL,MDIO

IH,MDIO

V

3.3

0

4

-0.3

V

OL,MDIO

V

Open Drain Pull-up Voltage

MDIO Output current for VOL = 0.4V

MDIO Output current rate of change

MDIO input inductance

2.3

10

-10

-

3.6

20

10

8

V

PULLUP

OL,MDIO

I

-

mA

mA/ns

nH

dI /dt

OL ,MDIO

L

I,MDIO

C

MDIO input capacitance

-

5

pF

I,MDIO

NOTES:

1. Measured from minimum MDIO VIH to maximum MDC VIL for MDIO rising edge.

Measured from maximum MDIO VIL to maximum MDC VIL for MDIO falling edge.

2. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge.

Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge.

3. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge and MDC rising edge.

Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge and MDC rising edge.

Measured from maximum MDC VIL to maximum MDIO VIL for MDIO rising edge and MDC falling edge.

Measured from maximum MDC VIL to minimum MDIO VIH for MDIO falling edge and MDC falling edge.

4. Measured driving a load of 470pF.

TABLE 6: OPERATING CONDITIONS

Name

Description

Ambient temperature under bias

Core power supply voltage

Min

Nom

25

Max

85

Units

°C

T

-40

A

V

1.14

1.2

1.26

V

DD

I

Core power supply current

-

300

400

mA

19

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 6: OPERATING

CONDITIONS

Name

Description

Min

Nom

Max

Units

V

Electrostatic discharge tolerance, Human Body Model -

Any pin with respect to any other pin except VDDA pins

-1400

1400

V

ESD1

V

Electrostatic discharge tolerance, Human Body Model -

Any pin with respect to VDDA pins

-300

300

V

ESD2

0

θ

JA

Junction-to-ambient thermal resistance (64 QFN)

26.00

C/W

20

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

5.0 REGISTERS DESCRIPTION

The XRS10L120 provides a variety of registers for the purpose of device configuration, testing and monitoring.

These registers are accessed through the MDIO interface, outlined in “Section 4.3, MDIO Interface” on

page 17. Operational registers available to the customer are given below. Note that all other addres space

should be left unmodified in order to ensure proper behaviour of the device.

5.1

Register Overview

The XRS10L120 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L120

contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within

each of these macros, and are outlined in “Section 5.2, Macro Registers” on page 22. MDIO device

designations 1-3 are used for each of these three macros as shown in Table 7. Registers relating to the

XRS10L120 as a whole are outlined in “Section 5.3, XRS10L120 Device Generic Registers” on page 27

and make use of MDIO device 0.

TABLE 7: MDIO DEVICE DESIGNATIONS

MDIO DEVICE

D

ESIGNATION

MACRO

RELEVANT

PINS

0

XRS10L120 Device Generic Registers

N/A

1

2

Serial ATA Host Interface Macro (Lane 0)

Serial ATA Devoce Interface Macro 0

SI

SO0, SO1

The XRS10L120 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit

MDIO address and data fields by setting the most significant byte of each to be 0. An example mapping from a

macro address/data combination to an MDIO address & data combination is shown in Table 8.

TABLE 8: MDIO ADDRESSING

MACRO

ADDRESS

M

ACRO

DATA

MDIO ADDRESS

MDIO DATA

0x40

abcde

0x0040

00000000000abcde

NOTE: The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads.

In the description of each register field, there is an entry describing its read/write status. This may fall into one

of the following categories:

•

R/W- register field is read/write

RO - register field is read only

LL - Latching Low - Used with bits that monitor some state internal to the XRS10L120. When the condition

for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts

to the cur-rent state of the condition it monitors.

•

LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time

it is read. Once it is read, its value reverts to the current state of the condition it monitors.

SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared.

21

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

5.2

Macro Registers

The registers outlined in this section are common to each of the two Serial ATA dual PHY macros as described

in the previous section. As such, each listed register is present in each of the 1 and 2 MDIO register spaces,

and will perform the stated function on the specified Serial ATA lane.

The registers within each dual PHY macro are split into the following sections:

Transmit/Receive lane 0 registers:

Transmit/Receive lane 1 registers:

PLL registers:

Address range 000*****

Address range 001*****

Address range 010*****

Address range 011*****

Bias generator registers:

TABLE 9: TRANSMIT/RECEIVE

L

ANE

R

EGISTERS (MDIO DEVICE 1, 2)

A

DDRESS

BIT

(

S

)

N

AME

R/W

DEFAULT

DESCRPTION

HEX

N.0000

N.0020

7

Reserved

R/W

0

DO NOT MODIFY

6

SATAPCIEXB_G1

Tx output swing booster bit (Gen 1)

0 = boost swing by 15%

1 = nominal swing

5:1

0

Reserved

R/W

00001 DO NOT MODIFY

Tx output swing booster bit (Gen 2)

SATAPCIEXB_G2

0

0 = boost swing by 15%

1 = nominal swing

N.0001

N.0021

7:3

2:0

Reserved

R/W

00000 DO NOT MODIFY

011 Transmit pre-emphasis control

Transmit_Eq0[2:0]

Transmit_Eq1[2:0]

000 = 0% transmit preemphasis

001 = 6.5% transmit preemphasis

010 = 13% transmit preemphasis

011 = 19.5% transmit preemphasis

100 = 26% transmit preemphasis

101 = 32.5% transmit preemphasis

110 = 39% transmit preemphasis

111 = 45.5% transmit preemphasis

22

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 9: TRANSMIT/RECEIVE

LANE REGISTERS (MDIO DEVICE 1, 2)

A

DDRESS

BIT

(

S

)

N

AME

R/W

DEFAULT

DESCRPTION

HEX

N.0002

N.0022

7:6

mscProg0[1:0]

mscProg1[1:0]

RW

01

Receive equalization control – boost at 1.5GHz

00 = Lowest boost level

01 = 2nd boost level

10 = 3rd boost level

11 = Highest boost level

5:3

Beacon_Swing0[2:0]

Beacon_Swing1[2:0]

R/W

100

0

Transmit swing size for OOB Signals

000 = 800mV

001 = 700mV

010 = 600mV

011 = 500mV

100 = 400mV

101 = 300mV

110 = 200mV

111 = 0mV

2:0

Output_Swing0[2:0]

Output_Swing1[2:0]

R/W

Transmit swing size in normal operation

000 = 800mV

001 = 700mV

010 = 600mV

011 = 500mV

100 = 400mV

101 = 300mV

110 =200mV

111 = 0mV

N.0003

N.0023

7

enEqB

R/W

Enable receive equalization

0 = enable equalization

1 = disable equalization

6:0

7

Reserved

RW

RO

RW

0010000 DO NOT MODIFY

N.0015

N.0035

-

Reserved

6:4

sysclk25divsel0[2:0]

sysclk25divsel1[2:0]

000

Divider selection for sysclk-> sysclk25

000 = divide by 1 (sysclk is 25MHz)

001 = divide by 2 (sysclk is 50MHz)

010 = divide by 3 (sysclk is 75MHz)

011 = divide by 4 (sysclk is 100MHz)

100 = divide by 5 (sysclk is 125MHz)

101 = divide by 6 (sysclk is 150MHz)

110 = divide by 10 (sysclk is 250MHz)

111 = divide by 12 (sysclk is 300MHz)

3:0

Reserved

RW

0x5

DO NOT MODIFY

23

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 9: TRANSMIT/RECEIVE

L

ANE REGISTERS (MDIO DEVICE 1, 2)

A

DDRESS

BIT

(

S

)

N

AME

R/W

DEFAULT

DESCRPTION

HEX

N.0018

N.0038

7:3

2:0

Reserved

RW

00100 DO NOT MODIFY

txbiasbuffsela0[2:0]

txbiasbuffsela1[2:0]

100

Tx Predriver swing size in normal operation

000 = 800mV

001 = 700mV

010 = 600mV

011 = 500mV

100 = 400mV (sata default)

101 = 300mV

24

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 10: PLL CONFIGURATION (MDIO DEVICE 1, 2)

A

DDRESS

BIT

(

S

)

NAME

TYPE

DEFAULT

DESCRIPTION

HEX

N.0040

7:6

5:0

Reserved

RO

-

Reserved

FBDIV[5:0]

RW

101101

Divide value for feedback clock

110000 = divide by 5

100000 = divide by 10

100001 = divide by 15

100010 = divide by 20

100011 = divide by 25

100101 = divide by 30

100111 = divide by 50

101101 = divide by 60 (default for 25MHz Ref))

Other - reserved

N.0041

7:6

5:0

Reserved

RO

-

Reserved

REFDIV[5:0]

RW

010000 Divide values for system clock

010000 = divide by 1 (default for 25MHz Ref))

000000 = divide by 2

000001 = divide by 3

000010 = divide by 4

000011 = divide by 5

000101 = divide by 6

000110 = divide by 8

000111 = divide by 10

001101 = divide by 12

001110 = divide by 16

001111 = divide by 20

Others - reserved

N.0044

7:6

5:0

Reserved

SSCMax

RO

-

Reserved

RW

000000 Maximum value for spread (set to 45 [0x2D] when

SSCBypass is set to "0")

25

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 10: PLL CONFIGURATION (MDIO DEVICE 1, 2)

A

DDRESS

BIT

(

S

)

NAME

TYPE

DEFAULT

DESCRIPTION

HEX

N.0045

7:5

4

Reserved

SSCmode

RO

0

Reserved

NOTE 1

R/W

Selects position of spreading interpolator

0 = Interpolator in feedback path

1 = Interpolator in feedforward path

Set to ’1’ when SSCBypass = ’0’

3

2

Reserved

SSCInvert

R/W

0

DO NOT MODIFY

Inverting SSC profile - Setting for downspread per

SATA spec

Set to ’0’ when SSCmode = ’0’

Set to ’1’ when SSCmode = ’1’

1

0

Reserved

R/W

0

1

DO NOT MODIFY

SSCBypass

Bypass the saw generator and pulse density modu-

lator and get increment from SSCMax (set SSCMax

to 45 [0x2D] when SSCBypass is set to 0)

NOTE: 1) In order to enable SSC generation, set register N.0044 to 0x2D, N.0045 to 0x14 and then reset the PLL by

writing register 0.0004 to 0x0 then 0xF.

TABLE 11: BIAS GENERATOR CONFIGURATION REGISTERS (MDIO DEVICES 1 & 2)

A

DDRESS

BIT

(

S

)

NAME

TYPE

RESET

VALUE

DESCRIPTION

HEX

N.0064

7:4

pr100Tx[3:0]

RW

0x0

Transmit pre-driver current bias

1010=50uA

0010=75uA

0000=100uA

0001=125uA

1100=150uA

0111=175uA

1111=200uA

3:0

7:4

3:0

Reserved

RW

0x0

DO NOT MODIFY

N.0065

prcal100Tx[3:0]

Transmit driver current bias

1010=50uA

0010=75uA

0000=100uA

0001=125uA

1100=150uA

0111=175uA

1111=200uA

26

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 12: POWERDOWN REGISTERS (MDIO DEVICES 1 & 2)

A

DDRESS

BIT

(

S

)

NAME

TYPE

RESET

VALUE

DESCRIPTION

HEX

1.0080

2.0080

7:6

SIpwrdnDetB[1:0]

RW

11

Powers down the signal detector and COM*

circuits

SO01pwrdnDetB[1:0]

1 = normal operation

0 = power down

5:4

3:2

1:0

SIpwrdnRxB[1:0]

RW

11

Powers down the receivers and CDR

1 = normal operation

SO01pwrdnRxB[1:0]

0 = power down

SIpwrdnTxDrvB[1:0]

Powers down the transmitter

1 = normal operation

0 = power down

SO01pwrdnTxDrvB[1:0]

SIpwrdnTxB[1:0]

Powers down the transmit pipes and clock

1 = normal operation

SO01pwrdnTxB[1:0]

0 = power down

1.0081

2.0081

7:2

1

Reserved

RO

RW

-

Reserved

SIpwrdnBiasGen

0

Powers down the bandgap.

1 = power down

SO01pwrdnBiasGen

0 = normal operation

0

SIpwrdnPLLB

RW

1

Powers down the PLL

1 = normal operation

0 = power down

SO01pwrdnPLLB

5.3

XRS10L120 Device Generic Registers

This section outlines generic registers relating to the XRS10L120 as a whole. These registers are accessed

through MDIO device 0.

TABLE 13: RESET

C

ONTROL SIGNALS

A

DDRESS

BIT

(

S

)

NAME

TYPE

RESET

VALUE

DESCRIPTION

HEX

0.0004

3:0

resetPLLB_reg[3:0]

RW

0x0F

Resets the PLL portion of the macros

0x00 = PLL reset

0x0F = clears PLL reset

0.0030

0.0031

0.0032

7:0

revision_id[7:0]

device_id [15:8]

device_id [7:0

R/O

0x01

0x83

0x04

Deivice Revision ID

Device ID MSB

Device ID LSB

27

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 14: PORT MULTIPLIER SATA STANDARD REGISTERS

D

V

EFAULT

REGISTER

BIT

(

S

)

NAME

TYPE

DESCRIPTION

ALUE

GSCR(0)

31 - 16

15 - 0

Device ID

Vendor ID

R/O

0x8304 Device ID allocated by the vendor.

Product

Identifier

0x13A8 Vendor ID allocated by the PCI-SIG of the vendor

that produced the Port Multiplier.

GSCR(1)

31 - 16

15 - 8

7:4

3

Reserved

REV_LEV

Reserved

PM_1,2

R/O

0x0000 31-16 Reserved

Revision

Information

0x01

0x0

1

15-8 Revision level of the Port Multiplier.

7-4 Reserved

1=Supports Port Multiplier specification 1.2.

1=Supports Port Multiplier specification 1.1.

1=Supports Port Multiplier specification 1.0.

Reserved

2

PM_1.1

1

PM_1.0

1

0

Reserved

0

GSCR(2)

Port

7:4

3 - 0

0x0

0x2

Reserved

DEV_FAN_OUT_

PORTS

Number of exposed device fan-out ports.

Information

GSCR(32)

Error

31 - 15

Reserved

OR_PORT-14

OR_PORT-13

OR_PORT-12

OR_PORT-11

OR_PORT-10

OR_PORT-9

OR_PORT-8

OR_PORT-7

OR_PORT-6

OR_PORT-5

OR_PORT-4

OR_PORT-3

OR_PORT-2

OR_PORT-1

OR_PORT-0

ERR_INFO_EN

R/O

0x0

Reserved

14

13

12

11

10

9

Reserved

Information

Reserved

8

Reserved

7

Reserved

6

Reserved

5

Reserved

4

Reserved

3

OR of selectable bits in Port 3 PSCR[1] (SError)

OR of selectable bits in Port 2 PSCR[1] (SError)

OR of selectable bits in Port 1 PSCR[1] (SError)

OR of selectable bits in Port 0 PSCR[1] (SError)

If set, bit is enabled for use in GSCR[32]

2

1

0

GSCR(33)

31 - 0

0x0

Error Infor-

mation Bit

Enable

28

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

TABLE 14: PORT MULTIPLIER SATA STANDARD REGISTERS

D

V

EFAULT

REGISTER

BIT

(

S

)

NAME

TYPE

DESCRIPTION

ALUE

GSCR(64)

31 - 5

Reserved

R/O

0x0

0

Reserved

Port Multi-

plier Revi-

sion 1.X

Features

Support

4

3

2

1

PHY_EVENT

ASYNC

1 = Supports Phy event counters

1

1 = Supports asynchronous notification

1 = Supports dynamic SSC transmit enable

SSC

0

PMREQ

BIST

1

1 = Supports issuing PMREQ to host

P

0

R/O

R/W

0

0x0

0

1 = Supports BIST

GSCR(96)

31 - 4

Reserved

ASYNC_EN

SSC_EN

Resaerved

Port Multi-

plier Revi-

sion 1.X

Features

Enable

3

2

1

1 = Asynchronous notification enabled

1 = Dynamic SSC transmit is enabled

0

PMREQ _EN

0

1 = Issuing PMREQ to host is enabled

P

0

BIST_EN

R/W

0

1 = BIST support is enabled

29

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

REV. 1.06

TABLE 15: SATA STANDARD REGISTERS - DEVICE PORT (0 TO 1) - STATUS AND CONTROL

NOTE: Registers designated as WC are write clear. In order to clear a particular bit or bit field within a WC designated

register, write a ‘1’ to that bit or bit field.

D

V

EFAULT

REGISTER

BIT

(

S

)

NAME

TYPE

DESCRIPTION

ALUE

PSCR(0)

(SStatus)

31 - 12

11 - 8

Reserved

IPM

R/O

Reserved

The IPM value indicates the current interface power man-

agement state

0000b = Device not present or communication not estab-

lished

0001b = Interface in active state

0010b= Interface in Partial power management state

0110b = Interface in Slumber power management state

All other values reserved

7 -4

SPD

R/O

The SPD value indicates the negotiated interface communi-

cation speed established

0000b = No negotiated speed (device not present or com-

munication not established)

0001b = Generation 1 communication rate negotiated

0010b = Generation 2 communication rate negotiated

All other values reserved

3 - 0

DET

R/O

The DET value indicates the interface device detection and

Phy state.

0000b = No device detected and Phy communication not

established

0001b = Device presence detected but Phy communication

not established

0011b = Device presence detected and Phy communication

established

0100b = Phy in offline mode as a result of the interface being

disabled or running in a BIST loopback mode

All other values reserved

PSCR(1)

(SError)

31 - 16

15 - 0

31 - 19

20 - 16

15 - 12

11 - 8

7 - 4

DIAG

ERR

R/WC

R/O

See description below

PSCR(2)

Reserved

PMP

Reserved All reserved fields shall be cleared to zero.

See description below

(SControl)

R/W

SPM

See description below

IPM

See description below

SPD

See description below

3 - 0

DET

See description below

30

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

SError register SCR(1) -

The Serial ATA interface Error register - SError - is a 32-bit register that conveys supplemental Interface error

information to complement the error information available in the Shadow Register Block Error register. The

register represents all the detected errors accumulated since the last time the SError register was cleared

(whether recovered by the interface of not). Set bits in the error register are explicitly cleared by a write

operation to the SError register, or a reset operation. The value written to clear set error bits shall have 1’s

encoded in the bit positions corresponding to the bits that are to be cleared. Host software should clear the

Interface SError register at appropriate checkpoints in order to best isolate error conditions and the commands

they impact.

Bits [31:16] DIAG

The DIAG field contains diagnostic error information for use by diagnostic software in validating correct

operation or isolating failure modes. The field is bit significant as defined in the following figure.

DIAG

R

A

X

F

T

S

H

C

D

B

W

I

N

A

Port Selector presence detected: This bit is set to one when COMWAKE is received while the host is

in state HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared to zero. The bit is cleared to zero when

the host writes a one to this bit location.

B

10b to 8b Decode error: When set to a one, this bit indicates that one or more 10b to 8b decoding

errors occurred since the bit was last cleared to zero.

C

CRC Error: When set to one, this bit indicates that one or more CRC errors occurred with the Link

layer since the bit was last cleared to zero.

D

Disparity Error: When set to one, this bit indicates that incorrect disparity was detected one or more

times since the last time the bit was cleared to zero.

F

Unrecognized FIS type: When set to one, this bit indicates that since the bit was last cleared one or

more FISes were received by the Transport layer with good CRC, but had atype field that was not recognized.

I

Phy Internal Error: When set to one, this bit indicates that the Phy detected some internal error since

the last time this bit was cleared to zero.

N

PHYRDY change: When set to one, this bit indicates that the PHYRDY signal changed state since the

last time this bit was cleared to zero.

H

Handshake error: When set to one, this bit indicates that one or more R_ERRPhandshake response

was received in response to frame transmission. Such errors may be the result of a CRC error detected by the

recipient, a disparity or 10b/8b decoding error, or other error condition leading to a negative handshake on a

transmitted frame.

R

Reserved bit for future use: Shall be cleared to zero.

S

Link Sequence Error: When set to one, this bit indicates that one or more Link state machine error

conditions was encountered since the last time this bit was cleared to zero. The Link layer state machine

defines the conditions under which the link layer detects an erroneous transition.

T

Transport state transition error: When set to one, this bit indicates that an error has occurred in the

transition from one state to another within the Transport layer since the last time this bit was cleared to zero.

W

COMWAKE Detected: When set to one this bit indicates that a COMWAKE signal was detected by the

Phy since the last time this bit was cleared to zero.

X

Exchanged: When set to one this bit indicates that device presence has changed since the last time

this bit was cleared to zero. The means by which the implementation determines that the device presence has

changed is vendor specific. This bit may be set to one anytime a Phy reset initialization sequence occurs as

determined by reception of the COMINIT signal whether in response to a new device being inserted, in

response to a COMRESET having been issued, or in response to power-up.

31

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

Bits [15:0] ERR

REV. 1.06

The ERR field contains error information for use by host software in determining the appropriate response to

the error condition. The field is bit significant as defined in the following figure.

ERR

R

E

P

C

T

R

M

I

C

Non-recovered persistent communication or data integrity error: A communication error that was not

recovered occurred that is expected to be persistent. Since the error condition is expected to be persistent the

operation need not be retried by host software. Persistent communications errors may arise from faulty

interconnect with the device, from adevice that has been removed or has failed, or a number of other causes.

E

Internal error: The host bus adapter experienced an internal error that caused the operation to fail and

may have put the host bus adapter into an error state. Host software should reset the interface before re-trying

the operation. If the condition persists, the host bus adapter may suffer from a design issue rendering it

incompatible with the attached device.

I

Recovered data integrity error: A data integrity error occurred that was recovered by the interface

through a retry operation or other recovery action. This may arise from a noise burst in the transmission, a

voltage supply variation, or from other causes. No action is required by host software since the operation

ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge

overall communications integrity and potentially step down the negotiated communication speed.

M

Recovered communications error: Communications between the device and host was temporarily lost

but was re-established. This may arise from a device temporarily being removed, from a temporary loss of Phy

synchronization, or from other causes and may be derived from the PHYRDYn signal between the Phy and

Link layers. No action is required by the host software since the operation ultimately succeeded, however, host

software may elect to track such recovered errors in order to gauge overall communications integrity and

potentially step down the negotiated communication speed.

P

Protocol error: A violation of the Serial ATA protocol was detected. This may arise from invalid or

poorly formed FISes being received, from invalid state transitions, or from other causes. Host software should

reset the interface and retry the corresponding operation. If such an error persists, the attached device may

have a design issue rendering it incompatible with the host bus adapter.

R

Reserved bit for future use: Shall be cleared to zero.

T

Non-recovered transient data integrity error: A data integrity error occurred that was not recovered by

the interface. Since the error condition is not expected to be persistent the operation should be retried by host

software.

SControl register SCR(2)

The Serial ATA interface Control register - SControl - is a 32-bit read-write register that provides the interface

by which software controls Serial ATA interface capabilities. Writes to the SControl register result in an action

being taken by the host adapter or interface. Reads from the register return the last value written to it.

Bits [19:16] PMP

The Port Multiplier Port (PMP) field represents the 4-bit value to be placed in the PM Port field of all transmitted

FISes. This field is ‘0000’ upon power-up. This field is optional and an HBA implementation may choose to

ignore this field if the FIS to be transmitted is constructed via an alternative method.

Bits [15:12] SPM

The Select Power Management (SPM) field is used to select a power management state. Anon-zero value

written to this field shall cause the power management state specified to be initiated. A value written to this

field is treated as a one-shot. This field shall be read as 0000b.

■

0000b = No power management state transition requested

32

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

■

0001b = Transition to the Partial power management state initiated

0010b = Transition to the Slumber power management state initiated

0100b = Transition to the active power management state initiated

All other values reserved

Bits [11:8] IPM

The IPM field represents the enabled interface power management states that may be invoked via the Serial

ATA interface power management capabilities

■

0000b = No interface power management state restrictions

0001b = Transitions to the Partial power management state disabled

0010b = Transitions to the Slumber power management state disabled

0011b = Transitions to both the Partial and Slumber power management states disabled

All other values reserved

Bits [7:4]SPD

The SPD field represents the highest allowed communication speed the interface is allowed to negotiate when

interface communication speed is established

■

0000b = No speed negotiation restrictions

0001b = Limit speed negotiation to a rate not greater than Gen 1 communication rate

0010b = Limit speed negotiation to a rate not greater than Gen 2 communication rate

All other values reserved

Bits [3:0] DET

The DET field controls the host adapter device detection and interface initialization.

■

0000b = No device detection or initialization action requested

0001b = Perform interface communication initialization sequence to establish communication. This is

functionally equivalent to a hard reset and results in the interface being reset and communications

reinitialized. Upon a write to the SControl register that sets the DET field to 0001b, the host interface

shall transition to the HP1: HR_Reset state and shall remain in that state until the DET field is set to a

value other than 0001b, by a subsequent write to the SControl register.

■

0100b = Disable the Serial ATA interface and put Phy in offline mode.

All other values reserved

33

EXSTOR XRS10L120

SERIAL ATA II: PORT MULTIPLIER

6.0 ORDERING INFORMATION

REV. 1.06

PRODUCT ORDERING INFORMATION

P

RODUCT

NUMBER

P

ACKAGE

TYPE

OPERATING TEMPERATURE RANGE

XRS10L120IL-F

XRS10L120IL

64 Pin QFN (Lead Free)

64 Pin QFN

-40°C to +85°C

34

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

64 LEAD QUAD FLAT NO LEAD

(9 mm x 9 mm x 0.9mm, 0.50 pitch QFN, Small Thermal Pad)

Rev. 1.00

Note: the actual center pad is

Metallic.

Note: The control dimension is in millimeter.

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

1.00

A

A1

A3

D

0.031

0.039

0.80

0.00

0.15

8.90

4.75

0.18

0.000

0.006

0.350

0.187

0.007

0.002

0.010

0.358

0.199

0.012

0.05

0.25

9.10

5.05

0.30

D2

b

e

0.0197 BSC

0.50 BSC

L

0.014

0.008

0.018

-

0.35

0.20

0.45

-

k

35

EXSTOR XRS10L120

REV. 1.06

SERIAL ATA II: PORT MULTIPLIER

REVISION HISTORY

REV #

1.00

1.01

1.02

1.03

1.04

1.05

1.06

DATE

DESCRIPTION OF CHANGES

November 2007 Released

January 2008

Corrected JTAG TRST, TDO pin desc., part ordering info.

February 2008 Corrected missing package / pinout diagrams.

March 2008

August 2008

Revised to operational registers.

Updated the ESD ratings and Link Power Management support.

February 2009 Updated transceiver power modes section, figure 4

June 2009

Remove 100 pin LQFP Package

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet June 2009.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

36

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFN	包装说明：	HVQCCN, LCC64,.35SQ,20
针数：	64	Reach Compliance Code：	unknown
风险等级：	5.76	边界扫描：	YES
JESD-30 代码：	S-PQCC-N64	JESD-609代码：	e3
长度：	9 mm	低功率模式：	YES
湿度敏感等级：	3	端子数量：	64
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装等效代码：	LCC64,.35SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	1.2 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Serial IO/Communication Controllers
最大供电电压：	1.26 V	最小供电电压：	1.14 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	9 mm
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, MULTIPLIER	Base Number Matches：	1

型号	制造商	描述	价格	文档
XRS10L120IV	EXAR	SERIAL ATA II: 1:2 PORT MULTIPLIER	获取价格
XRS10L120_09	EXAR	SERIAL ATA II: PORT MULTIPLIER	获取价格
XRS10L140	EXAR	SERIAL ATA II: PORT MULTIPLIER	获取价格
XRS10L140IV	EXAR	SERIAL ATA II: PORT MULTIPLIER	获取价格
XRS10L140IV-F	EXAR	SERIAL ATA II: PORT MULTIPLIER	获取价格
XRS10L210	EXAR	SERIAL ATA II: PORT SELECTOR	获取价格
XRS10L210IL	EXAR	SERIAL ATA II: PORT SELECTOR	获取价格
XRS10L210IL-F	EXAR	SERIAL ATA II: PORT SELECTOR	获取价格
XRS10L210IV	EXAR	SERIAL ATA II: PORT SELECTOR	获取价格
XRS10L210IV-F	EXAR	SERIAL ATA II: PORT SELECTOR	获取价格

XRS10L120IL-F

XRS10L120IL-F 概述

XRS10L120IL-F 规格参数

XRS10L120IL-F 数据手册

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