XRT71D04IV_技术文档

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

APRIL 2001

REV. 1.1.1

• Meets output jitter requirement as specified by

ETSI TBR24

GENERAL DESCRIPTION

The XRT71D04 is a four channel, single chip Jitter At-

tenuator, that meets the Jitter transfer characteristic

requirements specified in the ETSI TBR-24, Bellcore

GR-499 and GR-253 standards.

• Meets the Jitter and Wander specifications

described in T1.105.03b,GR-253 and GR-499 stan-

dards

• Selectable buffer size of 16 and 32 bits

• Jitter attenuator can be disabled

• Available in a 80 pin TQFP package

• Single 3.3V or 5.0V supply.

In addition, the XRT71D04 also meets the Jitter and

Wander specifications described in the ANSI

T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-

dards for Desynchronizing and Pointer adjustments in

the DS3 to STS-SPE mapping applications.

• Operates over - 40⁰C to 85⁰C temperature range.

FEATURES

APPLICATIONS

• Meets the E3/DS3/STS-1 jitter requirements

• No external components required

• E3/DS3 Access Equipment

• STS-SPE to DS3 Mapper

• DSLAMs

• Compliant with jitter transfer template outlined in

ITU G.751, G.752, G.755, GR-499-CORE,1995

GR-253-CORE standards

FIGURE 1. BLOCK DIAGRAM (ONE CHANNEL)

MCLK_n

Timing Control Block /

Phase locked Loop

STS1_n

ICT

DS3/E3_n

DJA_n

RRCLK_n

RRPOS_n

RClk_n

Write Clock

Read Clock

RClkES

RPOS_n

RNEG_n

16/32 Bit FIFO

RRNEG_n

FL_n

FSS

Channel 0

Channel 1

Channel 2

Channel 3

MODE_CTRL

HOST

Reset

Microprocessor Serial

Interface

XRT71D04

n = 0, 1, 2, 3

CS SDI SDO SClk

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

FIGURE 2. PIN OUT OF THE XRT71D04

AGND

FL_1

STS1_1

DS3/E3_3

DJA_3

MCLK_1

GND

RCLK_1

RPOS_1

RNEG_1

VDD

RNEG_0

RPOS_0

RCLK_0

GND

MCLK_0

DJA_1/SDI

STS1_3

FL_3

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

AGND

FL_2

STS1_2

DJA_2/CS

MCLK_2

GND

RCLK_2

RPOS_3

RNEG_3

VDD

RNEG_2

RPOS_2

RCLK_3

GND

MCLK_3

DJA_0/SCLK

DS3/E3_0

STS1_0

FL_0

XRT71D04

AGND

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

-40^oC to +85^oC

XRT71D04IV

80 Pin TQFP

Theta - J_A= ° C/W

Theta J_C= ° C/W

THERMAL INFORMATION

2

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................. 1

FEATURES ................................................................................................................................................... 1

APPLICATIONS ............................................................................................................................................. 1

Figure 1. Block Diagram (one channel) ................................................................................................. 1

Figure 2. Pin Out of the XRT71D04 ........................................................................................................ 2

ORDERING INFORMATION ..................................................................................................................... 2

TABLE OF CONTENTS...................................................................................................................................... I

PIN DESCRIPTIONS ........................................................................................................... 3

ELECTRICAL CHARACTERISTICS ................................................................................... 9

Figure 3. Input/Output Timing ................................................................................................................ 9

Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10

SYSTEM DESCRIPTION ................................................................................................... 12

Figure 5. A typical Channel_n of the XRT71D04 configured to operate in the Hardware Mode . 12

Figure 6. A typical Channel_n of the XRT71D04 configured to operate in the Host Mode ........... 13

1.0 Jitter Attenuator PLL .............................................................................................................................. 13

1.1 BACKGROUND INFORMATION ......................................................................................................................................13

1.1.1 Definition of Jitter ..........................................................................................................................................13

1.1.2 SONET STS-1 to DS3 Mapping....................................................................................................................13

1.2 JITTER TRANSFER CHARACTERISTICS.........................................................................................................................13

Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14

1.2.1 Jitter Tolerance .............................................................................................................................................14

1.2.2 Jitter Generation............................................................................................................................................14

1.2.3 Jitter Attenuation ...........................................................................................................................................14

1.2.4 SONET STS-1 DS3 Mapping.......................................................................................................................14

Figure 8. XRT71D04 Desynchronizer Block Diagram ........................................................................ 15

1.3 XRT71DO4 JITTER TRANSFER CHARACTERISTICS......................................................................................................16

TABLE 1: XRT71D04 JITTER TRANSFER FUNCTION .................................................................................. 16

TABLE 2: XRT71D04 MAXIMUM JITTER TOLERANCE ................................................................................. 17

2.0 Operating Modes .................................................................................................................................... 17

2.1 HARDWARE MODE.....................................................................................................................................................17

TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION ..................................... 17

2.2 HOST MODE:............................................................................................................................................................17

TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ...................................................... 18

3.0 Microprocessor Serial Interface ............................................................................................................ 18

3.1 SERIAL INTERFACE OPERATION..................................................................................................................................18

3.1.1 Bit 1—R/W (Read/Write) Bit..........................................................................................................................18

3.1.2 Bits 2 through 6—A0, A1, A2 ,A3, and A4 ....................................................................................................18

3.1.3 Bit 7—A5.......................................................................................................................................................18

3.1.4 Bit 8—A6.......................................................................................................................................................18

3.1.5 Read Operation.............................................................................................................................................18

3.1.6 Write Operation.............................................................................................................................................18

Figure 9. Microprocessor Serial Interface Data Structure ................................................................. 19

3.1.7 Simplified Interface Option............................................................................................................................19

Figure 10. Timing Diagram for the Microprocessor Serial Interface ................................................ 19

ORDERING INFORMATION ............................................................................................. 20

PACKAGE DIMENSIONS ................................................................................................. 20

REVISION HISTORY ..................................................................................................................................... 21

I

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTIONS

PIN DESCRIPTION

PIN #

NAME

AVDD

NC

TYPE

DESCRIPTION

Analog Power Supply = 5V±5% or 3.3V±5%

No Connection

1

****

2

3

4

GND

****

O

Digital Ground

RRCLK_0

Received Recovered Output (De-jittered) Clock - channel 0:

Output is the de-jittered or smoothed clock if the jitter attenuator is enabled. The

de-jittered data, RRPOS/RRNEG are clocked to this signal.

If RRCLKES is “low”, RRPOS/RRNEG will be updated at the falling edge of

RRCLK.

If RRCLKES is “high”, RRPOS/RRNEG will be updated at the rising edge of

RRCLK.

5

6

7

RRPOS_0

RRNEG_0

RRCLKES

O

I

Received Recovered Positive Data (De-Jittered) Output - channel 0:

De-jittered positive data output. Updated on the rising or falling edge of RRCLK,

depending upon the state of the RRCLKES input pin (or bit-field setting).

Received Recovered Negative Data (De-Jittered) Output - channel 0:

De-jittered negative data output. Updated on the rising or falling edge of RRCLK,

depending upon the state of the RRCLKES input pin (or bit-field setting).

Received Recovered Clock Edge Select Input:

Hardware Mode:

1. When RRCLKES = “0”, then RRPOS and RRNEG are updated on the falling

edge of RRCLK

2. When RRCLKES = “1”, then RRPOS and RRNEG are updated on the rising

edge of RRCLK

NOTE: This applies to all channels.

Host Mode

Connect this pin to GND when the 71D04 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

8

9

NC

No Connection

Reset

I

Reset Input. (Active-Low):

A high-low transition will re-center the internal FIFO, and will clear the Command

Registers (for Host Mode operation). Resetting this pin may corrupt data within

the device.

For normal operation, pull this pin to VDD.

Internal 50 K Ohm pull-up resistor.

10

DS3/E3_1

DS3/E3 Select Input - channel 1:

This pin along with the STS-1 mode select pin selects the operating mode. The

following table provides the configuration:

STS-1

DS3/E3

XRT71D04 Operating Mode

DS3 (44.736 MHz)

E3 (34.368 MHz)

STS-1 (51.84 MHz)

E3 (34.368 MHz)

0

1

0

1

0

1

Internal 50 K Ohm pull-down resistor.

11

VDD

****

Digital Power Supply = 5V±5% or 3.3V±5%

3

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

12

MODE_CTRL

I

Mode Control:

When “High” in Multimode, all channels are independent. When “Low”, the Mas-

ter Channel (channel_0) controls DS3/E3_n, STS1_n, RCLKES, FSS and

MCLK_n. DJA is NOT affected.

Internal 50 K Ohm pull-up resistor.

13

14

ICT

I

In Circuit Testing Input. (Active low):

With this pin tied to ground, all output pins will be in high impedance mode for in-

circuit-testing.

For normal operation this input pin should be tied to VDD.

Internal 50 K Ohm pull-up resistor.

HOST

Host/Hardware Mode Select:

An active-high input enables the Host mode. Data is written to the command reg-

isters to configure the XRT71D04.

In the Host mode, the states of discrete input pins are inactive.

An active-low input enables the Hardware Mode.In this mode, the discrete inputs

are active.

Internal 50 K Ohm pull-down resistor.

15

FLRST

I

FIFO Limit Reset

Hardware Mode

Whenever the FIFO is within 2 bits of either underflow or overflow, the FL_n will

be set high.

This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin.

This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND).

NOTE: The FL_n could be set “High” again if the FIFO is within 2 bits of either

underflow or overflow.

Host Mode

Reading the FL_n bits in the status registers clears this FL_n pin. Master Reset

also clears the FL_n output.

This pin is tied to GND. FLRST has no effect in this mode.

Internal 50 K Ohm pull-down resistor.

16

17

18

RRNEG_3

RRPOS_3

RRCLK_3

O

Received Recovered Negative Data (De-Jittered) Output - channel 3:

See description of pin 6

Received Positive Data (De-Jittered) Output - channel 3:

See description of pin 5

Received Recovered Output (De-jittered) Clock - channel 3:

See description of pin 4

19

20

21

22

GND

AVDD

AGND

FL_0

O

****

O

Digital Ground

Analog Power Supply = 5V±5% or 3.3V±5%

Analog Ground

FIFO Limit - channel 0:

This output pin is driven high whenever the internal FIFO comes within two-bits of

being either underflow or overflow.

4

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

23

STS1_0

I

SONET STS1 Mode Select - channel 0:

This pin along with the DS3/E3_0 select pin configures the XRT71D04 either in

E3, DS3 or STS-1 mode.

A table relating to the setting of the pins is given below:

STS-1

DS3/E3

XRT71D04 Operating Mode

DS3 (44.736 MHz)

0

1

0

1

0

1

E3 (34.368 MHz)

STS-1 (51.84 MHz)

E3 (34.368 MHz)

This input pin is active only in the Hardware Mode.

24

25

DS3/E3_0

I

DS3/E3 Select Input - channel 0:

See description pin 10.

Internal 50 K Ohm pull-down resistor.

DJA_0/SCLK

Harware Mode

Disable Jitter Attenuator Input - Channel 0:

An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will be

passed through without jitter attenuation.

Host Mode

Microprocessor Serial Interface Clock Signal:

This signal will be used to (1) sample the data, on the SDI pin, on the rising edge

of this signal. Additionally, during “Read” operations, the Microprocessor Serial

Interface will update the SDO output on the falling edge of this signal.

Internal 50 K Ohm pull-down resistor.

26

MCLK_3

I

Master Clock Input - channel 3:

Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-20ppm.

This clock must be continuous and jitter free with duty cycle between 30 to 70%.

It is permissible to use the EXCLK signal orSTS1 clock.

Internal 50 K Ohm pull-up resistor.

27

28

GND

****

I

Digital Ground

RCLK_3

Received Clock (Jittery) - channel 3:

Clock input RCLK3 should be connected to the recovered clock.

Internal 50 K Ohm pull-up resistor.

29

RPOS_2

RNEG_2

I

Received Positive Data (Jittery) Input: - channel 2:

Data that is input on this pin is sampled on either the rising or falling edge of

RCLK depending on the setting of the RCLKES pin (pin 10).

If RCLKES is “high”, then RPOS will be sampled on the falling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

Internal 50 K Ohm pull-up resistor.

30

I

Received Negative Data (Jittery) - channel 2:

The input jittery negative data is sampled either on the rising or falling edge of

RCLK depending on the setting of RCLKES.

If RCLKES is “high”, then RNEG will be sampled on the falling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

This pin is typically tied to the “RNEG” output pin of the LIU.

Internal 50 K Ohm pull-up resistor.

31

VDD

****

Digital Power Supply = 5V±5% or 3.3V±5%

5

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

32

RNEG_3

I

Received Negative Data (Jittery) - channel 3:

See description of pin 30.

Internal 50 K Ohm pull-up resistor.

33

34

RPOS_3

RCLK_2

I

Received Positive Data (Jittery) Input: - channel 3:

See description of pin 29.

Internal 50 K Ohm pull-up resistor.

Received Clock (Jittery) - channel 2:

See description of pin 28.

Internal 50 K Ohm pull-up resistor.

35

36

GND

****

I

Digital Ground

MCLK_2

Master Clock Input - channel 2:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

37

DJA_2/CS

I

Harware Mode

Disable Jitter Attenuator Input - Channel 2:

See description of pin 25

Host Mode

Chip Select Input:

An active-low input enables the serial interface.

Internal 50 K Ohm pull-down resistor.

38

39

STS1_2

FL_2

I

SONET STS1 Mode Select - channel 2:

See description of pin 23

O

FIFO Limit - channel 2:

See description of pin 22

40

41

42

43

44

AGND

AVDD

NC

****

Analog Ground

Analog Power Supply = 5V±5% or 3.3V±5%

No Connection

GND

****

O

Digital Ground

RRCLK_2

Received Recovered Output (De-jittered) Clock - channel 2:

See description of pin 4

45

46

RRPOS_2

RRNEG_2

O

Received Recovered Positive Data (De-Jittered) Output - channel 2:

See description of pin 5

Received Recovered Negative Data (De-Jittered) Output - channel 2:

See description of pin 6

47

48

NC

No Connection

FSS

I

FIFO Size Select Input:

When “High”: Selects 32 bits FIFO.

When “Low”: Selects 16 bits FIFO.

Internal 50 K Ohm pull-down resistor.

6

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

49

SDO

O

Serial Data Output:

This pin will serially output the contents of the specified Command Register, dur-

ing “Read” Operations. The data, on this pin, will be updated on the falling edge of

the SCLK input signal. This pin will be tri-stated upon completion of data transfer.

50

DS3/E3_2

I

DS3/E3 Select Input - channel 2:

See description pin 10.

Internal 50 K Ohm pull-down resistor.

51

52

53

VDD

NC

****

Digital Power Supply = 5V±5% or 3.3V±5%

I

No Connection

RCLKES

Received Clock Edge Select Input:

Hardware Mode

1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling edge

of RCLK

2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising edge

of RCLK

NOTE: This applies to all channels.

Host Mode

Connect this pin to GND when the 71D04 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

54

55

NC

No Connection

RRNEG_1

O

Received Recovered Negative Data (De-Jittered) Output - channel 1:

See description of pin 6

56

57

RRPOS_1

RRCLK_1

Received Recovered Positive Data (De-Jittered) Output - channel 1:

See description of pin 5

O

Received Recovered Output (De-jittered) Clock - channel 1:

See description of pin 4

58

59

60

61

62

GND

NC

****

Digital Ground

No Connection

AVDD

AGND

FL_1

****

O

Analog Power Supply = 5V±5% or 3.3V±5%

Analog Ground

FIFO Limit - channel 1:

See description of pin 22

63

64

STS1_1

I

SONET STS1 Mode Select - channel 1:

See description of pin 23

DS3/E3_3

DS3/E3 Select Input - channel 3:

See description pin 10.

Internal 50 K Ohm pull-down resistor.

65

DJA_3

I

Disable Jitter Attenuator Input - Channel 3:

See description of pin 25

Internal 50 K Ohm pull-down resistor.

7

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

66

MCLK_1

I

Master Clock Input - channel 1:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

67

68

GND

****

I

Digital Ground

RCLK_1

Received Clock (Jittery) - channel 1:

See description of pin 28.

Internal 50 K Ohm pull-up resistor.

69

70

RPOS_1

RNEG_1

I

Received Positive Data (Jittery) Input: - channel 1:

See description of pin 29.

Internal 50 K Ohm pull-up resistor.

Received Negative Data (Jittery) - channel 1:

See description of pin 30.

Internal 50 K Ohm pull-up resistor.

71

72

VDD

****

I

Digital Power Supply = 5V±5% or 3.3V±5%

RNEG_0

Received Negative Data (Jittery) - channel 0:

See description of pin 30.

Internal 50 K Ohm pull-up resistor.

73

74

RPOS_0

RCLK_0

I

Received Positive Data (Jittery) Input: - channel 0:

See description of pin 29.

Internal 50 K Ohm pull-up resistor.

Received Clock (Jittery) - channel 0:

See description of pin 28.

Internal 50 K Ohm pull-up resistor.

75

76

GND

****

I

Digital Ground

MCLK_0

Master Clock Input - channel 0:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

77

DJA_1/SDI

I

Harware Mode

Disable Jitter Attenuator Input - Channel 1:

See description of pin 25

Host Mode

Serial Data Input

The address value (of the command registers) or the data value is either Read or

Written through this pin.

The input data will be sampled on the rising edge of the SCLK pin.

Internal 50 K Ohm pull-down resistor.

78

79

80

STS1_3

FL_3

I

SONET STS1 Mode Select - channel 3:

See description of pin 23

O

FIFO Limit - channel 3:

See description of pin 22

AGND

****

Analog Ground

8

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

ELECTRICAL CHARACTERISTICS

AC Electrical Characteristics

Electrical Characteristics (TA = 25°C, VDD = 3.3 V t0 5.0 V± 5 % unless otherwise specified)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS.

MClk

RClk

tsu

Duty Cycle

30

50

70

%

MHz

%

Frequency E3 + 20 ppm

34.368

44.736

51.84

50

Frequency DS3 + 20 ppm

Frequency STS-1 + 20 ppm

Duty Cycle

30

70

5

Rise Time

ns

Fall Time

5

ns

RPOS/RNEG to RClk rise time setup

RPOS/RNEG to RClk rising hold time

RRPOS/RRNEG delay from RRClk rising

RRPOS/RRNEG delay from RRClk falling

5

ns

th

ns

td

5

ns

te

ns

FIGURE 3. INPUT/OUTPUT TIMING

t_su

RCLK

t_h

t_d

RPOS/RNEG

RClkES = 0

t_su

RCLK

t_h

t_e

RPOS/RNEG

RClkES = 1

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

Microprocessor Serial Interface Timing ( see Figure 4 )

Electrical Characteristics (TA = 25°C, VDD = 3.3 V to 5.0 V ± 5 % unless otherwise specified)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS.

t21

t22

t23

t24

t25

t26

t27

t28

t29

t30

t31

t32

CS Low to Rising Edge of SClk Setup Time

SClk to CS Hold Time

50

20

ns

SDI to Rising Edge of SClk Setup Time

SDI to Rising Edge of SClk Hold Time

SClk “Low” Time

50

240

500

50

SClk “High” Time

SClk Period

SClk to CS Hold Time

CSB “Inactive” Time

250

Falling Edge of SClk to SDO Valid Time

Falling Edge of SClk to SDO Invalid Time

Falling Edge of SClk, or rising edge of CS to High Z

200

100

FIGURE 4. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE

t29

t21

CS

SClk

SDI

t27

t28

t22

t25

t26

A1

t24

R/W

t23

A0

CS

SClk

t31

t30

Hi-Z

t33

t32

D0

D2

D7

SDO

SDI

D1

Hi-Z

10

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

DC Electrical Characteristics (TA = 25°C, VDD = 3.3 V ± 5 % unless otherwise specified)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Power Supply Voltage

Input High Voltage

Input Low Voltage

VDD

VIH

V_IL

3.135

2.0

3.3

3.465

5.25

0.8

V

-0.5

Output High Voltage @ IOH=-5mA

Output Low Voltage @ IOL=5mA

Supply Current ( E3)

VOH

VOL

Icc

IL

2.4

V

0.4

95

mA

Supply Current ( DS3 )

110

125

Supply Current ( STS-1)

Input Leakage Current(except Input pins with Pull-up resistor.

Input Capacitance

± 10

µA

pF

CI

5.0

Output Load Capacitance

C_L

25

DC Electrical Characteristics (TA = 25°C, VDD = 5.0 V ± 5 % unless otherwise specified)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Power Supply Voltage

Input High Voltage

Input Low Voltage

VDD

VIH

V_IL

4.75

2.0

5.0

5.25

0.8

V

-0.5

Output High Voltage @ IOH=-5mA

Output Low Voltage @ IOL=5mA

Supply Current ( E3)

VOH

VOL

Icc

IL

2.4

V

0.4

140

170

190

mA

Supply Current ( DS3 )

Supply Current ( STS-1)

Input Leakage Current(except Input pins with Pull-up resistor.

Input Capacitance

± 10

µA

pF

CI

5.0

Output Load Capacitance

C_L

25

ABSOLUTE MAXIMUM RATINGS:

Supply Range

ESD Rating

-0.5 V to + 6.0 V

> 2000 V on all pins

-40⁰C to +85⁰C

Operating Temperature

Storage Temperature

-65°C to + 150°C

11

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

The XRT71D04 also meets the DS3 wander specifi-

SYSTEM DESCRIPTION

cation that apply to SONET and asynchronous inter-

faces as specified in the ANSI T1.105.03b 1997 stan-

dard.

The XRT71D04 is an integrated 4-channel E3/DS3/

STS-1 jitter attenuator that attenuates the jitter from

the input clock and data. The jitter attenuation perfor-

mance meets the latest specifications such as Bellcore

GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T

G.751,ITU-T G.752 and ITU-T G.755 standards.

For support of loop-timing applications, the

XRT71D04 can also be used to reduce and limit the

amount of jitter in the recovered line clock signal.

The XRT71D04 also meets both the mapping and

pointer adjustment jitter generation criteria for both

Category I and Category II interfaces as specified in

Bellcore GR-253.

Figure 5 presents a simple block diagram of the

XRT71D04, when it is configured to operate in the

Hardware Mode and Figure 6 presents a simple block

diagram of the XRT71D04, when it is configured to

operate in the Host Mode.

FIGURE 5. A TYPICAL CHANNEL_N OF THE XRT71D04 CONFIGURED TO OPERATE IN THE HARDWARE MODE

MCLK_n

Timing Control Block /

Phase locked Loop

Jittery

Clock

Smoothed

Clock

ICT

DJA_n

RClk_n

RRCLK_n

Write Clock

Read Clock

RRPOS_n

RRNEG_n

RCLKES

RPOS_n

RNEG_n

16/32 Bit FIFO

RRCLKES

FL_n

FSS

HOST

Reset

DS3/E3_n

12

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

FIGURE 6. A TYPICAL CHANNEL_N OF THE XRT71D04 CONFIGURED TO OPERATE IN THE HOST MODE

MClkn

Timing Control Block /

Phase locked Loop

Smoothed

Clock

Jittery

Clock

ICT

RRCLK_n

Write Clock

Read Clock

RCLK_n

RRPOS_n

RRNEG_n

RRCLKES

FL_n

16/32 Bit FIFO

RPOS_n

RNEG_n

HOST

Reset

Microprocessor Serial

Interface

CS

SDI

SDO SClk

The XRT71D04 DS3/E3 Jitter Attenuator IC consists

of the following functional blocks:

2) Cross-talk noise

3) Inter-symbol interference/Signal Distortion

• The Jitter-Attenuator PLL

• Timing Control Block

1.1.2 SONET STS-1 to DS3 Mapping

SONET equipment jitter criteria are specified as:

• The 2-Channel 16/32 Bit FIFO

• Serial Microprocessor Interface

i) Jitter Transfer

ii) Jitter Tolerance

1.0 JITTER ATTENUATOR PLL

1.1 BACKGROUND INFORMATION

1.1.1 Definition of Jitter

iii) Jitter Generation

1.2 JITTER TRANSFER CHARACTERISTICS

The primary purpose of jitter transfer requirements is

to prevent performance degradations by limiting the

accummulation of jitter through the system such that

it does not exceed the network interface jitter require-

ments. Thus, it is more important that a system meet

the jitter transfer criteria for relatively high input jitter

amplitudes. The jitter transferred through the system

must be under the jitter mask for any input jitter ampli-

tude within the range as shown in Figure 7

One of the most important and least understood mea-

sures of clock performance is jitter. The International

Telecommunication Union defines jitter as short term

variations of the significant instants of a digita signal

from their ideal positions in time. Jitter can occur due

to any of the following:

1) Imperfect timing recovery circuit in the system

13

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK

0.1

slope = -20 dB/decade

Acceptable

Range

40

Frequency (Hz)

1.2.1 Jitter Tolerance

In Figure 5and Figure 6, this de-jittered clock is la-

beled Smoothed Clock. This Smoothed Clock is now

used to Read Out the Recovered Data from the 16/32

bit FIFO. This Smoothed Clock will also be output to

the Terminal Equipment via the RRClk output pin.

Likewise, the Smoothed Recovered Data will output

to the Terminal Equipment via the RRPOS and

RRNEG output pins.

The jitter tolerance in the network element is defined

as the maximum amount of jitter in the incoming sig-

nal that it can receive in an error-free manner.

1.2.2 Jitter Generation

Jitter generation is defined in Section 7.3.3 of GR-

499-CORE. Jitter generation criteria exists for both

Category I and II interfaces, which consist of mapping

and pointer adjustment jitter generation.

The XRT71D04 is designed to work as a companion

device with XRT73L04 (STS-1/DS3/E3) Line Inter-

face Unit.

Mapping jitter is the sum of the intrinsic payload map-

ping jitter and the jitter that is generated as a result of

the bit stuffing mechnisms used in all of the asynchro-

nous DSn mapping into STS SPE.

ETSI TBR24 specifies the maximum output jitter in

loop timing must be no more than 0.4UIpp when mea-

sured between 100Hz to 800KHzwith upto 1.5UI input

jitter at 100Hz. This means a jitter attenuator with

bandwidth less than 100Hz is required to be compli-

ant with the standard. ITU G.751 is another applica-

tion where low bandwidth jitter attenuator is needed

to smooth the gapped clock output in the de-multi-

plexer system.

1.2.3 Jitter Attenuation

A digital Jitter Attenuation loop combined with the

FIFO provides Jitter attenuation. The Jitter Attenuator

requires no external components except for the refer-

ence clock.

Data is clocked into the FIFO with the associated

clock signal (TClk or RClk) and clocked out of the

FIFO with the dejittered clock and data. When the

FIFO is within 2 bits of being completely full, the FIFO

Limit (FL) will be set.

1.2.4 SONET STS-1 DS3 Mapping

Bellcore GR-253 section 3.4.2 and the ANSI T1.105-

199 describes the asynchronous mapping for DS3 in-

to STS-1 SPE.

14

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

An asynchronous mapping for DS3 into STS-1 SPE is

defined for clear-channel transport of DS3 signals

that meet the DSX-3 requirements in the GR-499-

CORE.

block diagram of the Desynchronizer is shown in

Figure 8.

The elastic store accepts the STS-1 data stream and

a gapped clock. The gaps in the input clock inhibit the

elastic store from writing all but DS3 payload data.

When the input data has a rate lower than the output

data rate, the positive stuffing will occur. The stuffing

mechanism that generates the C-bits is implement-

ed in a desynchronizer that has the jitter output less

than 0.4 UIpp assuming no jitter or wander at the in-

put of the synchronizer and no pointer adjustments. A

The bit leaking circuit stores incoming STS-1 pointer

adjustments into a queue and leaks them out of the

desynchronizer one bit at a time.

STS-Nc signal is used to transport higher rate sig-

nals. However,the digital signals that SONET carries

do not fit in the SPE perfectly.

FIGURE 8. XRT71D04 DESYNCHRONIZER BLOCK DIAGRAM

STS-1

reference clock

STS-1

gapped clock

XRT71D04

DS3 payload

(dejittered)

STS-N

Clock

STS-1

OH

Processing

Elastic

Store

STS-N

Pointer

Clock

Processing

Recovery

Descramble/

Demux

Section

&

Line Overhead

STS-N

Nth STS-1

Dejittering

Pointer

Adjustment

&

STS-1

gapped clock

Stuff Control

15

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

1.3 XRT71DO4 JITTER TRANSFER CHARACTERISTICS

Table 2 summarizes the results of jitter tolerance test-

ing, performed on the XRT71D04.

Table 1 summarizes the results of jitter transfer char-

acteristics testing, performed on the XRT71D04.

TABLE 1: XRT71D04 JITTER TRANSFER FUNCTION

DS3 E3

APPLICATION

STS-1

INPUT JITTER

1UIPP

10UIPP

1UIPP

10UIPP

1UIPP

10UIPP

FREQ. (HZ)

5

Jitter Gain (dB)

0.02

0.36

-0.30

0.44

0.83

-0.22

10

-0.10

-2.04

-0.15

-3.16

20

-2.24

-3.24

30

-3.63

-4.33

-5.51

-5.93

40

-5.98

-6.16

-7.68

-7.99

50

-7.55

-7.82

-10.36

-12.50

-15.20

-16.22

-17.38

-19.45

-20.36

-22.96

-23.78

-23.51

-9.61

60

-9.57

-9.17

-11.27

-13.59

-15.51

-17.07

-18.75

-21.11

-24.46

-28.84

-35.77

80

-12.54

-14.67

-16.67

-17.32

-18.77

-21.43

-22.22

-25.42

-11.28

-13.36

-14.91

-16.78

-18.96

-21.81

-26.09

-33.44

100

125

150

200

300

500

>1000

16

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

TABLE 2: XRT71D04 MAXIMUM JITTER TOLERANCE

APPLICATION

DS3

E3

STS-1

32

FIFO SIZE

FREQ. (HZ)

10

16

32

16

32

16

UI (PEAK TO PEAK)

34.313

>64

26.689

53.313

37.438

33.938

32.688

32.063

31.689

31.314

31.189

31.064

30.939

20

21.439

18.314

16.939

16.314

16.064

15.689

15.439

15.314

15.189

15.0189

43.188

36.813

34.313

33.188

32.563

31.814

31.439

31.314

31.189

31.064

30.939

18.564

16.689

16.064

15.689

15.564

15.314

15.189

15.064

15.189

30

40

50

60

80

100

125

150

200

300

500

>1000

2.0 OPERATING MODES

2.1 HARDWARE MODE

2.2 HOST MODE:

In Host mode (connect this pin to VDD), the serial

port interface pins are used to control configuration

and status report. In this mode, serial interface pins :

SDI, SDO,SCLK and CS are used.

The HOST pin is used to select the operating mode of

the XRT71D04. In Hardware mode (connect this pin

to ground), the serial processor interface is disabled

and hard-wired pins are used to control configuration

and report status.

A listing of these Command Registers, their Address-

es, and their bit-formats are listed below in Table 4.

TABLE 3: FUNCTIONS OF DUAL MODE PINS IN

HARDWARE MODE CONFIGURATION

FUNCTION, WHILE IN THE

PIN #

PIN NAME

HARDWARE MODE

25

37

77

DJA0/SCLK

DJA2/(CS)

DJA1/(SDI)

DJA0

DJA2

DJA1

17

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS

COMMAND

ADDR

TYPE

D7

D6

D5

D4

D3

D2

D1

D0

REGISTER

0X06

0x07

0x0E

0x0F

0x16

0x17

0x1E

0x1F

CR6

CR7

R/W

RO

***

STS-1_0

***

DS3/E3_0

***

DJA_0 RRClkES_0 RClkES_0 FSS_0

*** *** *** FL_0

CR14

CR15

CR22

CR23

CR30

CR31

R/W

RO

STS-1_1

***

DS3/E3_1

***

DJA_1 RRClkES_1 RClkES_1 FSS_1

*** *** *** FL_1

DJA_2 RRClkES_2 RClkES_2 FSS_2

R/W

RO

STS-1_2

***

DS3/E3_2

***

DJA_3 RRClkES_3 RCLKES_3 FSS_3

*** *** *** FL_3

***

FL_2

R/W

RO

STS-1_3

***

DS3/E3_3

***

3.0 MICROPROCESSOR SERIAL INTERFACE

3.1.3 Bit 7—A5

The serial interface for the XRT71D04 and the

XRT73L00 family of E3/DS3/STS-1 LIU’s are the

same, which makes it easy to configure both the

XRT71D04 and the LIU with a single CS, SDI, SDO

and SClk input and output pins.

A5 must be set to “0”, as shown in Figure 9.

3.1.4 Bit 8—A6

The value of A6 is a don’t care.

Once these first 8 bits have been written into the Seri-

al Interface, the subsequent action depends upon

whether the current operation is a Read or Write op-

eration.

3.1 SERIAL INTERFACE OPERATION.

Serial interface data structure and timings are provid-

ed in Figure 5 and 6 respectively.

3.1.5 Read Operation

The clock signal is provided to the SClk and the CS is

asserted for 50 ns prior to the first rising edge of the

SClk.

Once the last address bit (A4) has been clocked into

the SDI input, the Read operation will proceed

through an idle period, lasting three SClk periods. On

the falling edge of SClk Cycle #8 (see Figure 9) the

serial data output signal (SDO) becomes active. At

this point the user can begin reading the data con-

tents of the addressed Command Register (at Ad-

dress [A4,A3, A2, A1, A0]) via the SDO output pin.

The Serial Interface will output this eight bit data word

(D0 through D7) in ascending order (with the LSB

first), on the falling edges of the SClk . The data (on

the SDO output pin) is stable for reading on the very

next rising edge of the SClk .

3.1.1 Bit 1—R/W (Read/Write) Bit

This bit will be clocked into the SDI input, on the first

rising edge of SClk (after CS has been asserted).

This bit indicates whether the current operation is a

Read or Write operation. A “1” in this bit specifies a

Read operation; whereas, a “0” in this bit specifies a

Write operation.

3.1.2 Bits 2 through 6—A0, A1, A2 ,A3, and A4

The five (5) bit Address Values.

The next five rising edges of the SClk signal will clock

in the 5-bit address value for this particular Read (or

Write) operation. The address selects the Command

Register for reading data from, or writing data to. The

address bits to the SDI input pin is applied in ascend-

ing order with the LSB (least significant bit) first.

3.1.6 Write Operation

Once the last address bit (A4) has been clocked into

the SDI input, the Write operation will proceed

through an idle period, lasting three SClk periods. Pri-

or to the rising edge of SClk Cycle #9 , the eight bit

data word is applied to SDI input. Data on SDI is

latched on the rising edge of SClk.

18

XRT71D04

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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SClk

SDI

R/W

A0

A1

A2

A3

A4

0

A6

D0

D1

D2

D3

D4

D5

D6

D7

High Z

D0

D1

D2

D3

D4

D5

D6

D7

SDO

NOTES:

3.1.7 Simplified Interface Option

1. A5 is always “0”.

The user can simplify the design of the circuitry con-

necting to the Microprocessor Serial Interface by ty-

ing both the SDO and SDI pins together, and reading

data from and/or writing data to this combined signal.

This simplification is possible because only one of

these signals are active at any given time. The inac-

tive signal will be tri-stated.

2. R/W = “1” for Read Operations

3. R/W = “0” for Write Operations

4. Denotes a “don’t care” value (shaded areas)

FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE

t29

t21

CS

SClk

SDI

t27

t28

t22

t25

t26

A1

t24

R/W

t23

A0

CS

SClk

t31

t30

Hi-Z

t33

t32

D0

D2

D7

SDO

SDI

D1

Hi-Z

19

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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

PRELIMINARY

REV. 1.1.1

ORDERING INFORMATION

PART #

PACKAGE

OPERATING TEMPERATURE RANGE

-40^oC to +85^oC

XRT71D04IV

80 Pin TQFP

Theta - J_A= ° C/W

Theta J_C= ° C/W

THERMAL INFORMATION

PACKAGE DIMENSIONS

80 LEAD THIN QUAD FLAT PACK

(14X14X1.4mm, TQFP)

Rev. 1.0

D

D ₁

41

60

40

61

D ₁

D

80

21

1

20

A₂

e

B

C

A

α

A₁

L

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

A₁

A₂

B

0.055

0.002

0.053

0.009

0.004

0.622

0.547

0.063

0.006

0.057

0.015

0.008

0.638

0.555

1.40

0.05

1.60

0.15

1.45

0.38

0.20

16.20

14.10

1.35

0.22

C

0.09

D

15.80

13.90

D₁

e

0.0256BSC

0.65BSC

L

0.018

0^o

0.030

7^o

0.45

0^o

0.75

7^o

α

Note: the control dimension is the millimeter column

20

áç

XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

REVISION HISTORY

Rev. P1.0.1; Revised pull-up/pull-down resistors on various pins.

Rev. P1.0.2; Corrected block diagram and made minor edits.

Rev. P1.0.3 Modified pin list and figures to reflect channel designation by _n (example; MCLK0 to

MCLK_0). Changed from VSS to GND.

Rev. 1.1.0: Remved Preliminary designation. Added electrical characteristics tables.

Rev. 1.1.1: Corrected Table 4 adding RRClkES_n as data D2, STS-1_n as D5, added D7. Corrected the

description of the section 3 Serial Microprocessor Interface. Moved figure 9 into Electrical Characteristics

Section. Moved Jitter Transfer/Tolerance tables into Jitter Attenuator Section 1.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet April 2001.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

21


型号：	XRT71D04IV
厂家：	EXAR CORPORATION
描述：	4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER 4路E3 / DS3 / STS - 1抖动衰减器， STS - 1到DS3的失同步衰减器
文件：	总22页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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