XRT85L61IG [EXAR]
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR; BITS （建筑物综合定时供给）时钟提取
| 型号： | XRT85L61IG |
| 厂家： | 
EXAR CORPORATION |
| 描述： | BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR |
| 文件： | 总16页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
FEBRUARY 2004
REV. 1.0.1
GENERAL DESCRIPTION
• Supports 75Ω and 120Ω (E1), 100Ω (T1) applica-
tions.
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100Ω,
E1 (2.048Mbps) 75Ω or 120Ω applications.
• Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
• Receive loss of signal (RLOS) output
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
• Meets Telcordia GR-1244-CORE Section 3.4.1 R3-
27 specification
• Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
• Single +3.3V Supply Operation
• Logic inputs accept either 3.3 V or 5 V levels
• 28 pin TSSOP package
FEATURES
• Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
APPLICATIONS
• Extracts 2048 kHz, 1544 kHz clock and data com-
• Universal Clock Synchronization for G.703 Telecom
ponents
Formats
• Extracts 64 KHz and 8 kHz, 400 Hz clock informa-
tion
• T1/E1 Line Receiver with Clock and Data Recovery
• DSLAM
• Line Code Violation alarms
• On-chip digital clock recovery circuit
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
RCLKINV
DATA_INV
DATAMUT
JAEN
Reference Inputs
MCLK1
(1.544 MHz for T1)
Master Clock
Generator
MCLK2
(2.048 MHz for E1
or 64 kbps)
RPOS
Clock
RNEG
Extractor
RCLK
RTIP
(64kHz,1544kHz or 2048kHz)
Clock and
Data
Recovery
Jitter
Attenuator
Rx
Equalizer
Peak Detector
and Slicer
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
Line Side
Line code
and clock
violation
Detector
RRING
(T1 or E1 or 64 kbps input)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
S1
Mode Select
T1, E1 or 64 kbps
S2
S3
LOS
Detector
RLOS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XRT85L61IG
28 Lead TSSOP
FIGURE 2. PIN OUT OF THE XRT85L61
1
28
RCLKINV
MCLK1
2
27
DATA_INV
JAEN
RCLK_LCV/ AIS
26
3
MCLK2
4
25
8 KHz_LCV/ BPV
400 Hz_LCV
8 KHz
JAVDD
5
24
JAGND
6
23
ICT
7
22
400 Hz
RTIP
RRING
AVDD
AGND
S1
RLOS
8
21
20
19
18
17
16
15
DVDD
DGND
RCLK
9
10
11
12
13
14
RPOS
RNEG
DATMUT
S2
S3
NC
2
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61 ............................................................................................................................... 1
ORDERING INFORMATION.....................................................................................................................2
FIGURE 2. PIN OUT OF THE XRT85L61............................................................................................................................................ 2
TABLE OF CONTENTS ............................................................................................................I
PIN DESCRIPTIONS ..........................................................................................................3
ELECTRICAL CHARACTERISTICS ..................................................................................6
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 6
DC Electrical Characteristics....................................................................................................................6
FUNCTIONAL DESCRIPTION ...........................................................................................7
1.0 OPERATING MODE: ..............................................................................................................................7
1.1 64 KHZ CLOCK MODE: .................................................................................................................................... 7
TABLE 1: OPERATING MODE SELECTION........................................................................................................................................... 7
TABLE 2: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT ............................................................................... 7
1.1.1 64 KHZ + 8 KHZ CLOCK EXTRACTION...................................................................................................................... 8
1.1.2 64 KHZ + 8 KHZ + 400 HZ CLOCK EXTRACTION ...................................................................................................... 8
TABLE 3: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT............................................................................ 8
FIGURE 3. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)................................................................................... 8
1.2 2048 KHZ RZ E1 MODE ................................................................................................................................... 9
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1) ................................................................... 9
FIGURE 5. E1 PULSE MASK (G.703) ................................................................................................................................................ 9
TABLE 4: G.703 SPECIFICATION E1................................................................................................................................................ 10
1.3 2048 KHZ NRZ MODE .................................................................................................................................... 11
FIGURE 6. E1 CLOCK SIGNAL WAVE SHAPE - G.703 ...................................................................................................................... 11
TABLE 5: G.703 2048 KHZ CLOCK INTERFACE ............................................................................................................................... 11
1.4 1544 KHZ T1 MODE ....................................................................................................................................... 12
FIGURE 7. G.703 DS1 WAVE FORM............................................................................................................................................... 12
2.0 AIS DETECTION TIMING ....................................................................................................................13
FIGURE 8. AIS DETECTION FOR E1 MODE...................................................................................................................................... 13
FIGURE 9. AIS DETECTION FOR T1 MODE ...................................................................................................................................... 13
ORDERING INFORMATION...................................................................................................................14
REVISION HISTORY............................................................................................................................. 15
I
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
1
MCLK1
I
Reference T1 Clock input:
This signal is an independent 1544 kHz clock with accuracy better than
+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in T1 mode.
NOTE: If T1 mode is not used, this clock is not necessary for the device
to operate.
2
JAEN
I
Jitter Attenuator Enable:
Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit
FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 kΩ resistor
3
MCLK2
I
Reference E1 and 64 kHz Clock Input:
This signal is an independent 2048 kHz clock with accuracy better than +
50 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in E1 and 64 kHz mode.
NOTE:
To reduce intrinsic jitter when the JA is enabled, it is
recommended to have a reference clock with an accuracy of ±
25 ppm or better. If E1 mode or 64 kHz mode is not used, this
clock is not necessary for the device to operate.
4
5
6
JAVDD
JAGND
ICT
***
***
I
VDD for Jitter Attenuator (3.3V ± 5%)
Jitter Attenuator Ground
In circuit Testing
When this pin is grounded, all output pins are Tri-stated for testing pur-
poses.
NOTE: Internally Pulled up with 50 kΩ resistor
7
8
RTIP
RRING
AVDD
AGND
I
Receive Positive Input
I
Receive Negative Input
9
***
***
Analog VDD (3.3V ± 5%)
Analog Ground
10
3
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
11
S1
I
Mode Select
S1
S2
0
S3
0
MODE
64 kHz + 8 kHz
64kHz+8kHz+400Hz
E1 RZ
0
0
0
0
1
1
1
1
0
1
1
0
1
1
E1 NRZ
0
0
T1
0
1
T1 (output full width data)
E1 (output full width data)
Reserved
1
0
1
1
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG
are 1 RCLK wide.
12
13
14
15
S2
S3
I
I
Mode Select
Mode Select
NC
***
I
This pin must be grounded for normal operation
Data Muting:
DATMUT
Connect this pin “High” to mute data output to “Low” state at RPOS/
RNEG. The RLOS pin can be connected to this pin to mute the output
when RLOS occurs.
NOTE: Internally Pulled down with 50 kΩ resistor
16
17
18
RNEG
RPOS
RCLK
O
O
O
Receive Negative Data Output:
The data is half clock cycle wide.
Receive Positive Data Output:
The data is half clock cycle wide
Receive Clock Output
Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock
19
20
21
22
23
24
DGND
DVDD
***
***
O
Digital Supply Ground
Digital Supply Voltage (3.3V ± 5%)
Receive Loss of Signal Output
RLOS
400Hz
O
400 Hz Clock output for 64 kHz Operation
8 kHz clock output for 64 kHz Operation
8 kHz
O
400Hz_LCV
O
Line Code Violation for 400 Hz
This pin will stay “High” when 400 Hz is not in sync.
4
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
25
8 kHz_LCV/
BPV
O
Line Code Violation for 8 kHz in 64 kHz operation
Bipolar Violation:
In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated
at this pin.
This pin will stay “High” when 8 kHz is not in sync.
26
RCLK_LCV/AIS
O
Receive Clock Violation.
In 64 kbps operation, every missing pulse will cause this pin to go “High”
for half the clock cycle
AIS Indication
In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay
“High” for 250 µs in E1 RZ mode, and in T1 mode, AIS will stay “High” for
3 ms.
27
28
DATA_INV
RCLK_INV
I
I
Data Invert:
Connect this pin “High” to output active “Low” data at RPOS/RNEG.
NOTE: Internally Pulled down with 50 kΩ resistor
Receive Clock Invert:
Connect this pin “High” to align the data to change at the falling edge of
RCLK.
NOTE: Internally Pulled down with 50 kΩ resistor
5
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
Supply Voltage Range
ESD
- 65°C to + 150°C
- 40°C to + 85°C
-0.5V to +6.0V
2000 V
Theta-JA
68°C/W
Theta-JC
13°C/W
ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 3.3 V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
DC Electrical Characteristics
VDDD
VDDA
VIL
DC Supply Voltage (Digital)
DC Supply Voltage (Analog)
Input Low Voltage
3.135
3.135
3.3
3.3
3.465
3.465
0.8
V
V
V
VIH
VOL
VOH
IL
Input High Voltage
2.0
0
VDD
0.4
V
Output Low Voltage, IOUT = -4.0mA
Output High Voltage, IOUT = 4.0mA
Input Leakage Current*
V
2.4
VDD
±10
V
µA
pF
pF
CI
Input Capacitance
5
CL
Output Load Capacitance
25
NOTE: * Not applicable to pins with pull-down resistors.
6
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
FUNCTIONAL DESCRIPTION
The XRT85L61 is an integrated BITS (Building Integrated Timing Supply) Clock Generator. Simplified block
diagram of the chip is shown in Figure 1.
The XRT85L61 extracts the clock signals from the following synchronization lines:
■ Balanced 100 Ω lines with 1544 kbps DS1 pattern.
■ Balanced 120 Ω or unbalanced 75 Ω lines with 2048 kbps RZ pattern.
■ Balanced 120 Ω or unbalanced 75 Ω line with 2048 kbps NRZ pattern.
■ Balanced 110 Ω line with 64 kbps having 8 kHz violations; a “64 kHz + 8 kHz sync pattern.
■ Balanced 110 Ω line with a 64 kbps pattern having both 8 kHz and 400 Hz violations; a “64 kHz + 8 kHz
+ 400 Hz” sync pattern.
1.0 OPERATING MODE:
The operating mode for the XRT85L61 is shown in Table 1.
TABLE 1: OPERATING MODE SELECTION
DATA OUTPUT AT
S1
S2
S3
MODE
RPOS / RNEG
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64 kHz + 8 kHz
64 kHz + 8 kHz + 400 Hz
E1RZ
RZ
RZ
RZ
RZ
RZ
E1NRZ
T1
T1 (full width)
E1 (full width)
Reserved
1.1
64 kHz Clock Mode:
The XRT85L61 receives the 64 kbps ternary RZ signal. Two modes of 64 kHz operation is possible by selecting
S1, S2 and S3 as shown in Table 1.
TABLE 2: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT
FREQUENCY
(A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
(a) AMI with 8 kHz Bipolar Violation
Signal Format
(b) AMI with 8 kHz Bipolar Violation removed at every 400 Hz.
Alarm Condition
Alarm should not occur against the amplitude range from 0.63 V to 1.1 V
7
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE 3: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT
FREQUENCY
Load Impedance
Transmission Media
Pulse Width (FWHM)
Amplitude
(A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
110 Ω resistive
Symmetric Pair Cable
< 7.8 ± 0.78 µs
< 1 V ± 0.1 V
1.1.1
64 kHz + 8 kHz Clock Extraction
The input data is shown in Figure 3. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation.
Both the 64 kHz and 8 kHz components are extracted from the composite received signal and presented at the
64 kHz and 8 kHz output pins.
FIGURE 3. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)
Missing Pulse
Missing Pulse or Wrong Polarity Pulse
RTIP/
RRING
V
V
V
64kHz
Clock
Missing Pulse
RPOS
Not Valid Violation
RNEG
V
8kHz Clock
Missing Pulse
Missing Pulse
If Pulse Missing at RTIP/RRING
Missing Pulse or No Violation Bit
RClk_LCV
8kH_LCV
Not Valid Violation
out of sync
1.1.2
64 kHz + 8 kHz + 400 Hz Clock Extraction
Figure 4 shows the input data for this mode. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar
Violation removed every 400 Hz. The 64 kHz, 8 kHz and 400 Hz components are extracted from the composite
received signal and presented at the RClk, 8 kHz and 400 Hz output pins.
NOTE: The inputs are not aligned with all output signals. The above diagram is used to depict the output activity when the
input signals have errors.
8
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1)
nV
V1
V1
V2
V2
nV
125µs
125µs
125µs
125µs
(8 kHz)
(8 kHz)
(8 kHz)
(8 kHz)
(8 kHz)
(400 Hz)
(400 Hz)
LCV
if nV is
Missing
NOTES:
1.
V1 and V2 indicate AMI code-rule violations, and give the 8kHz timing.
2. V1 and V2 have different violation polarity with respect to each other.
3. nV indicates no violation (violation stealing) and gives the 400 Hz timing.
1.2
2048 kHz RZ E1 Mode
In this mode, the XRT85L61 receives a standard E1 signal as shown in Figure 5. Table 4 gives the details of
the E1 pulse.
FIGURE 5. E1 PULSE MASK (G.703)
269 ns
(244 + 25)
V = 100%
194 ns
(244 – 50)
N o m ina l pulse
50%
24 4 ns
219 ns
(24 4 – 2 5)
0%
48 8 n s
(24 4 + 244)
N ote
– V corresponds to the nom in al pea k value.
9
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE 4: G.703 SPECIFICATION E1
PULSE
INTERFACE
Pulse Shape (nominally rectangular)
All Marks of a valid signal must conform with the mask irrespective of
the sign. The value V corresponds to the nominal peak value.
Pair(s) in each direction
One coaxial pair
75 Ω Resistive
2.37 V
One symmetrical pair
120 Ω Resistive
3 V
Test Load Impedance
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal Pulse Width
0 ± 0.237 V
0 ± 0.3 V
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05
Maximum peak to peak jitter at an output port
Refer to ITU-T G.823 specification
10
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
1.3
2048 kHz NRZ Mode
In this mode, XRT85L61 receives 2048 kbps synchronization signal as shown in Figure 6.
FIGURE 6. E1 CLOCK SIGNAL WAVE SHAPE - G.703
T
T
T
T
T
T
3 0
30
3 0
3 0
3 0
3 0
+
+
V
V
1
0
–
V
1
–
V
T
4
T
4
T
4
T
4
T
T 1818 900-92
S h ad ed a rea in w h ich
sig nal sho uld be
m on oton ic
T
A verag e p eriod o f
synchronizing sig nal
F IG U R E 21 /G .7 03
W ave sha pe at an o utp ut p o rt
TABLE 5: G.703 2048 KHZ CLOCK INTERFACE
PULSE
INTERFACE
Frequency
Pulse Shape
2048 kHz ± 50 ppm
The signal must conform with the mask.
The value V corresponds to maximum peak value
The value V1 corresponds to minimum peak value
Pair(s) in each direction
Test Load Impedance
Coaxial pair
75 Ω Resistive
1.5
Symmetrical pair
120 Ω Resistive
Maximum peak value (Vop
)
1.9
Minimum peak value (Vop)
0.75
1.0
Maximum jitter at an output port
0.05 UI peak to peak measured within the frequency range f1 = 20 Hz
to f4 = 100 kHz
NOTE: This value is valid for network timing distribution equipment.
Other values may be specified for timing output ports of digital
links carrying the network timing.
11
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
1.4
1544 kHz T1 Mode
In this mode, the XRT85L61 receives a standard DS1 signal as shown in Figure 7.
FIGURE 7. G.703 DS1 WAVE FORM
N orm alized amplitude
1.5
1.0
0.5
0
– 0.5
– 1.0
– 1.0
– 0.5
0
0.5
1.0
1.5
T1528670-98
Tim e, in U nit Intervals
12
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
2.0 AIS DETECTION TIMING
In E1 mode, AIS is set when the incoming signal has 2 or less Zeros in sequence of 512 bits. AIS will stay
“High” for 250 µs and AIS is cleared upon receiving three or more zeros in the subsequent 512 bits (250µs)
time-frame. Figure 8 shows the AIS timing.
FIGURE 8. AIS DETECTION FOR E1 MODE
250µs
250µs
E1
DATA
AIS
0
0
0
0
0
In T1 mode, AIS is cleared when 5 or more zeros is detected in the subsequent 4632 bits (3 ms) time-frame.
Figure 9 shows the AIS timing for T1 mode.
FIGURE 9. AIS DETECTION FOR T1 MODE
3 ms
3 ms
T1
DATA
AIS
0
0
0
0
0
0
0
0
0
13
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XRT85L61IG
28 Lead TSSOP
PACKAGE OUTLINE DRAWING
D
28
15
E1
E
1
14
C
A
Seating
Plane
A2
α
B
e
A1
L
Note: The control dimension is in the millimeter column
INCHES MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
B
0.033
0.002
0.031
0.007
0.004
0.378
0.248
0.169
0.047
0.006
0.041
0.012
0.008
0.386
0.260
0.177
0.85
0.05
0.80
0.19
0.09
9.60
6.30
4.30
1.20
0.15
1.05
0.30
0.20
9.80
6.60
4.50
C
D
E
E1
e
0.0256 BSC
0.65 BSC
L
0.018
0.030
0.45
0.75
α
0°
8°
0°
8°
14
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
REVISION HISTORY
REVISION #
DATE
CHANGES
P1.0.1
P1.0.2
P1.0.3
1.0.0
August 2002
original
November 2002 Edits to text
December 2002 Ordering information changed from XRT85L61IV to XRT85L61IG
January 2004
Final Release
1.0.1
February 2004 Added description for MCLK1 and MCLK2.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained here in are
only for illustration purposes and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked; no responsibility, however, is assumed for
inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of
injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet February 2004.
15
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