EM5103VT [EXCELLIANCE]
3A Low Dropout LDO;型号: | EM5103VT |
厂家: | Excelliance MOS |
描述: | 3A Low Dropout LDO |
文件: | 总10页 (文件大小:331K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EM5103
3A Low Dropout LDO
General Description
Pin Configuration
EM5103 is a 3A low dropout linear regulator
designed for low dropout and high current
applications. This device works with dual supplies,
a control input for the control circuitry and a power
input as low as 1.2V for providing current to output.
It features 3A output current and ultra-low-drop
output voltage as well as full protection functions.
VOUT can be as low as 0.8V.
Ordering Information
1
10
9
VOUT
CNTL
Part Number
EM5103GE
Package
PSOP-8
Lead-Free
DFN3X3-10L
Lead-Free
Remark
2
VIN
VOUT
GND
3
8
VOUT
VIN
VIN
EN
4
7
FB
EM5103VT
5
6
POK
11
Features
DFN3x3-10L
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VIN Range 1.2V to 5.5V
Typical Application Circuit
VOUT is Adjustable (0.8V Min)
Excellent Line Regulation
Excellent Load Regulation
PSOP8
VIN
R3
100K
VIN
EN
POK
VOUT
FB
C4
10uF
3A Guaranteed Output Current*
300mV @ 3A Dropout Voltage
OTP and OCP Functions
EN
VOUT
R1
100K
R5
10
VCNTL
CNTL
NC
C1
22uF
Very Low On-Resistance
R2
100K
C3
1uF
Enable & Power good Signal
GND
*Check thermal design information.
Applications
DFN3X3-10L
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notebook & Netbook
Graphic Cards & MB
Low Voltage Logic Supplies
Chipset Supplies
Server System
SMPS Post Regulators
2011/11/14
Rev.A.8
1
EM5103
Pin Assignment
Pin No.
PSOP8 DFN3X3-10L
Pin Name
Pin Function
Power OK Indication. POK is an open-drain output. An external pull high
resistor connected to this pin is required.
POK
EN
1
2
3
5
6
Enable Input. Pulling the pin below 0.4V turns the regulator off
Input Voltage. This is the drain input to the power device that supplies
current to the output pin. VIN cannot be forced higher than VCNTL.
Supply Input for Control Circuit. CNTL provides supply voltage to the control
circuitry and driver for the pass transistor. The driving capability of output
current is proportioned to the VCNTL. For the device to regulate, the voltage on
this pin must be at least 2.0V greater than the output voltage, and no less
VIN
7,8,9
CNTL
4
10
than VCNTL_MIN.
No Connection inside chip.
NC
5
6
-
Output Voltage. VOUT is power output pin. An internal pull low resistance
exists when the device is disabled. Minimum 22uF low ESR ceramic holding
capacitor is required at this pin for stabilizing VOUT voltage.
Feedback Voltage. FB is the inverting input to the error amplifier. A resistor
divider from the output to GND is used to set the regulation voltage as
VOUT = (1 + R1/R2) x 0.8V (V). This pin has high impedance and should be kept
from noisy source to guarantee stable operation.
VOUT
1,2,3
FB
7
8
4
GND
11
Ground.
Function Block Diagram
EN
VIN
ZEN
Thermal
Protection
Control
Logic
Current
Limit
Soft Start
Power On
Reset
CNTL
0.8V
+
0.8V
Voltage
Reference
0.72V
VOUT
POK
+
GND
Delay
0.72V
FB
2011/11/14
Rev.A.8
2
EM5103
Absolute Maximum Ratings (Note1)
ꢀ VIN ---------------------------------------------------------------------------------- -0.3V to +6V
ꢀ VCNTL (Note 1) ------------------------------------------------------------------- -0.3V to +6V
ꢀ Other Pins ------------------------------------------------------------------------ -0.3V to (VCNTL+0.3V)
ꢀ Package Thermal Resistance,θJA,
PSOP8 (Note 2) ------------------------------------------------------------- 75°C/W
DFN3X3-10L ---------------------------------------------------------------- 60°C/W
ꢀ Power Dissipation, PD @ TA = 25°C,
PSOP8 (Note 3) -------------------------------------------------------------- 1.9W
DFN3X3-10L ------------------------------------------------------------------ 1.67W
ꢀ Junction Temperature -------------------------------------------------------- 150°C
ꢀ Lead Temperature (Soldering, 10 sec.) ---------------------------------- 260°C
ꢀ Storage Temperature --------------------------------------------------------- -65°C to +150°C
ꢀ ESD susceptibility (Note4)
ꢀ HBM (Human Body Mode) --------------------------------------------------
2KV
ꢀ MM (Machine Mode) ---------------------------------------------------------- 200V
Recommended Operating Conditions (Note5)
ꢀ Supply Input Voltage, VIN ---------------------------------------------------- 1.0V to VCNTL
ꢀ Control Voltage, VCNTL -------------------------------------------------------- 3.0V to 5.5V
ꢀ Junction Temperature -------------------------------------------------------- -40°C to 125°C
ꢀ Ambient Temperature -------------------------------------------------------- -40°C to 85°C
Electrical Characteristics
VCNTL=5V, TA=25°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Supply Input Section
Control Input Voltage
POR Threshold
VCNTL
VCNTLRTH
VCNTLHYS
VIN
VOUT= VREF
3.0
-
-
5.5
V
V
V
V
2.7
0.2
-
-
-
POR Hysteresis
-
Power Input Voltage
Control Input Current in
Shutdown
VOUT=VREF
1.0
VCNTL
ICNTL_SD VIN=VCNTL=5V, IOUT=0A,VEN=0V
-
-
10
30
uA
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
Quiescent Current
IQ
0.9
1.5
mA
Feedback
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
Reference Voltage
Feedback Input Current
VIN Line Regulation
VREF
0.788
0.8
5
0.812
-
V
IFB
-
-
nA
1.2V<VIN<5V, VCNTL=VEN=5V,
VREF(LINE)
0.01
0.1
%/V
IOUT=0A, VOUT=VREF
10mA<IOUT<3A,
VREF(LOAD)
Load Regulation (Note 6)
-
-
0.8
-
1.5
3
%/A
%
VIN=VCNTL=VEN=5V, VOUT=VREF
10mA<IOUT<3A,
VREF(TOTAL) VIN=VCNTL=VEN=5V, VOUT=VREF,
-40oC<Tj<125 oC by design
Load Regulation over
Temperature
2011/11/14
Rev.A.8
3
EM5103
IOUT=2A, VCNTL=VEN=5V, VOUT= VREF
IOUT=3A, VCNTL=VEN=5V, VOUT=VREF
-
-
200
300
-
240
mV
mV
V
Dropout Voltage (Note 7)
VDROP
VOUT
360
VCNTL-2
-
Output Voltage
VOUT Pull Low Resistance
Enable
0.8
-
VIN=VCNTL=5V, VEN=0V
70
Ω
Enable High Level
VEN
VSD
IEN
1.4
-
-
-
0.4
18
-
V
V
Disable Low Level
Enable Source Current
Enable Input Impedance
Output Voltage Ramp Up
Time
-
-
-
VCNTL=5V, VEN=0V
7
μA
KΩ
ZEN
700
1.5
2.5
90
4.5
ms
PWROK
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
FB Power OK Threshold
Power OK Hysteresis
VPOKTH
-
-
%
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
VPOKHYS
-
8
-
%
POK Delay Time
Over Current Protection
OCP Threshold Level
Output Short Circuit
Current
From VOUT>90% to POK rising
0.5
1.0
2.0
ms
IOCP
ISC
VIN=VCNTL=VEN=5V, VOUT=VREF
VIN=VCNTL=VEN=5V, VOUT=0V
3.2
1.5
4.0
2.5
-
-
A
A
Thermal Protection
Thermal Shutdown
Temperature
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
TSD
-
-
160
30
-
-
°C
°C
Thermal Shutdown
Hysteresis
VIN=VCNTL=VEN=5V, IOUT=0A,
VOUT=VREF
TSDHYS
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2.
θ
JA is measured in the natural convection at TA=25oC on a 4-layers high effective thermal conductivity test board with
minimum copper area of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for
PSOP-8 package.
Note 3. θJA PSOP-8 packages is 52°C /W on JEDEC 51-7 (4 layers,2S2P) thermal test board with 50mm2 copper area.
Note 4. Devices are ESD sensitive. Handling precaution is recommended.
Note 5. The device is not guaranteed to function outside its operating conditions.
Note 6. Load regulation is measured by a current pulse with 50Hz frequency and 10% duty cycle.
Note 7. The dropout voltage is defined as (VIN-VOUT), which is measured when VOUT equal to (VOUT,(NORMAL)-100mV).
2011/11/14
Rev.A.8
4
EM5103
Typical Operating Characteristics
Power On from VIN
Power On from VCNTL
VIN
VCNTL
VOUT
VOUT
POK
IIN
POK
IIN
VCNTL=5V,VIN=3.3V,COUT=1000uF,No Load.
VCNTL=5V,VIN=3.3V,COUT=1000uF,No Load.
Dropout Voltage vs. Output Current
Turn On from EN
VEN
VOUT
POK
IIN
VCNTL=5V,VIN=3.3V,COUT=1000uF,No Load.
VCNTL=5V,VOUT =1.6V.
Output Voltage vs. Output Current
Output Short Circuit
0.8V
0.6V
0.4V
0.2V
0V
0A
1A
2A 3A
4A 5A
Output Current (A)
VIN=VCNTL=5V,VOUT=VREF
.
VIN=VCNTL=5V,VOUT=1.0V.
2011/11/14
Rev.A.8
5
EM5103
Load Transient Response
Quiescent Current vs. Input Voltage
VOUT
IOUT
VCNTL=5V,VIN=3.3V,COUT=22uF.
VOUT=VREF
.
Shutdown Current vs. Input Voltage
Line Regulation
VCNTL=5V,VOUT=VREF
.
VOUT=VREF
Quiescent Current vs. Temperature
FB Voltage vs. Temperature
VIN=VCNTL=5V,VOUT=VREF
.
VIN=VCNTL=5V,VOUT=VREF.
2011/11/14
Rev.A.8
6
EM5103
On Resistance vs. Temperature
VCNTL=5V,VOUT=1.6V.
2011/11/14
Rev.A.8
7
EM5103
Functional Description
Enable Function
Power Dissipation
EM5103 is enabled if the voltage of the EN pin is
greater than 1.4V. If the voltage of the EN pin is
less than 0.4V, the IC will be disabled. The
quiescent current can be decreased to be less than
10uA typically.
The max power depends on some conditions,
including of thermal impedance, PCB layout,
airflow, and so on. The max power dissipation can
be calculated by the formula as below
PD(max)=(TJ(max)-TA) / θJA
POR – Power ON Reset
To let EM5103 start to operation, CNTL voltage
must be higher than its POR voltage even when EN
voltage is pulled higher than enable high voltage.
Typical POR voltage is 2.7V.
TJ(max) is the max junction temperature; θJA is the
thermal impedance from junction to ambient. The
thermal impedance θJA of exposed SOP-8 is
package design and PCB design dependent. The
thermal impedance can be reduced by increasing
the copper area under the exposed pad of the
SOP-8 package. So, to let the copper area as large
as possible is helpful for the thermal performance
of the exposed SOP-8 package.
VOUT Voltage Adjustment
The VOUT voltage of EM5103 can be adjusted by
external voltage divider. Refer to typical
application circuit, VOUT voltage is calculated by
the following equation,
VOUT = (1 + R1/R2) x 0.8V
For recommended specification of EM5103, the
max junction temperature is 125 degree C. The θJA
of exposed SOP-8 is 75°C/W on the standard JEDEC
51-7(4 layers, 2S2P, copper 2 oz) thermal test
board. The max power dissipation (at 25°C ambient,
on the min exposed pad layout) can be calculated
as below:
Over Current Limit Function
EM5103 features over current limiting function as
well as output short circuit current fold back
function. Typically, before the thermal protection is
triggered, EM5103 can limit its output current to
4.0A. When output voltage is decreased, the
limiting current level also decreases. When VOUT is
short to GND, or VOUT voltage is zero, the output
current level is limited to 2.5A, typically.
PD(max at 25°C)=(125°C–25°C)/(75°C/W) = 1.33W
Input and Output Capacitor Selection
For CNTL pin, a 1uF ceramic capacitor is enough for
bypass the supply of CNTL to GND. For VIN pin,
10uF or larger ceramic capacitor is required to
provide bypass path in transient current demand.
VOUT pin is also recommended to have 22uF or
larger ceramic capacitor to be stable and reduce
the VOUT voltage dip when fast loading transient is
happened. A feed-forward capacitor can be placed
between VOUT and FB pin to speed up the
transient response, optionally.
2011/11/14
Rev.A.8
8
EM5103
Ordering & Marking Information
Device Name: EM5103GE for PSOP-8
EM
5103
EM5103 Device Name
ABCDEFG: Date Code
ABCDEFG
Device Name: EM5103VT for DFN3X3-10L
EM
5103
EM5103 Device Name
ABCDEFG: Date Code
ABCDEFG
1
Outline Drawing
SOP-8 EP
J
F
I
I
K
G
H
D
E
M
N
B
C
A
Dimension in mm
Dimension
Min.
A
B
C
D
E
F
G
H
I
J
K
M
N
4.70 3.70 5.80 0.33
1.20 0.02 0.40 0.19 0.25 0∘ 1.94 1.94
Typ.
1.27
Max.
5.10 4.10 6.20 0.51
1.62 0.15 0.83 0.26 0.50 8∘ 2.49 2.49
2011/11/14
Rev.A.8
9
EM5103
DFN3X3-10L
E
A1
A3
E2
A
1
10
5
6
L
K
Dimension in mm
Dimension
Min.
Typ.
A
A1
A3
b
0.18
D
E
D2 E2
2.20 1.40
e
L
K
0.30 0.20
0.7 0.00
0.75 0.02
0.80 0.05
0.2
0.25 3.0 3.0
0.30
0.50 0.40
0.50
Max.
2.70 1.75
2011/11/14
Rev.A.8
10
相关型号:
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