6N135TSR2M [FAIRCHILD]
Logic IC Output Optocoupler;
| 型号： | 6N135TSR2M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Logic IC Output Optocoupler 输出元件 光电 |
| 文件： | 总19页 (文件大小：3540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2014
Single-Channel: 6N135M, 6N136M, HCPL4503M
Dual-Channel: HCPL2530M, HCPL2531M
High Speed Transistor Optocouplers
Features
Description
■ High Speed –1 MBit/s
The HCPL4503M, 6N135M, 6N136M, HCPL2530M, and
HCPL2531M optocouplers consist of an AlGaAs LED
optically coupled to a high speed photodetector transistor.
■ Superior CMR – 10 kV/µs
■ Dual-Channel: HCPL2530M, HCPL2531M
■ CTR Guaranteed 0°C to 70°C
■ U.L. Recognized (File # E90700, Vol. 2)
■ DIN EN/IEC60747-5-5
A separate connection for the bias of the photodiode
improves the speed by several orders of magnitude over
conventional phototransistor optocouplers by reducing
the base-collector capacitance of the input transistor.
– Ordering Option ‘V’, e.g., 6N135VM
The HCPL4503M has no internal connection to the
phototransistor base for improved noise immunity.
■ 5,000 V
(1 Minute) Isolation Rating
RMS
■ Superior CMR of 15,000 V/µs Minimum (HCPL4503M)
An internal noise shield provides superior common
mode rejection of up to 50,000 V/µs.
■ No Base Connection for Improved Noise Immunity
(HCPL4503M)
Related Resources
■ www.fairchildsemi.com/products/opto/
Applications
■ Line Receivers
■ www.fairchildsemi.com/pf/HC/HCPL0500.html
■ www.fairchildsemi.com/pf/FO/FODM452.html
■ www.fairchildsemi.com/pf/FO/FOD050L.html
■ Pulse Transformer Replacement
■ Output Interface to CMOS-LSTTL-TTL
■ Wide-Bandwidth Analog Coupling
Schematics
Package Outlines
8
VCC
+
VCC
8
1
8
N/C
1
8
1
1
VF1
_
V01
VB
+
2
7
6
5
2
3
4
7
6
5
VF
_
8
8
_
V02
3
VO
1
1
VF2
+
Figure 2. Package Outlines
N/C
GND
GND
4
HCPL2530M/HCPL2531M
6N135M, 6N136M, HCPL4503M
Pin 7 is not connected in the
HCPL4503M
Figure 1. Schematics
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
Safety and Insulation Ratings for 8-Pin DIP White
As per DIN EN/IEC 60747-5-5. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max. Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 V
For Rated Mains Voltage < 300 V
For Rated Mains Voltage < 450 V
For Rated Mains Voltage < 600 V
Climatic Classification
I–IV
I–IV
RMS
RMS
RMS
RMS
I–III
I–III
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
CTI
175
V
Input to Output Test Voltage, Method b,
1,669
PR
V
x 1.875 = V , 100% Production Test with
IORM
PR
t
= 1 s, Partial Discharge < 5 pC
m
Input to Output Test Voltage, Method a,
x 1.5 = V , Type and Sample Test with
1,335
V
IORM
PR
t
= 60 s, Partial Discharge < 5 pC
m
V
Max Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
890
6,000
8.0
V
V
IORM
PEAK
V
IOTM
PEAK
mm
mm
mm
mm
External Clearance
7.4
External Clearance (for Option T, 0.4” Lead Spacing)
Insulation Thickness
10.16
0.5
Safety Limit Values, Maximum Values Allowed in the
Event of a Failure
T
Case Temperature
150
200
300
°C
mA
mW
Ω
S
I
Input Current
S,INPUT
P
Output Power (Duty Factor ≤ 2.7%)
Insulation Resistance at T , V = 500 V
S,OUTPUT
9
R
10
IO
S
IO
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T = 25°C unless otherwise specified.
A
Symbol
Parameter
Storage Temperature
Operating Temperature
Lead Solder Temperature
Condition
Value
Units
°C
T
-40 to +125
-40 to +100
260 for 10 s
STG
T
°C
OPR
T
°C
SOL
EMITTER
I (avg) DC/Average Forward Input
25
50
1.0
5
mA
mA
A
F
(1)
Current Each Channel
I (pk)
Peak Forward Input Current
Each Channel
50% Duty Cycle, 1 ms P.W.
F
(2)
I (trans) Peak Transient Input Current
≤ 1 µs P.W., 300 pps
F
Each Channel
V
P
Reverse Input Voltage Each
Channel
V
R
D
Input Power Dissipation Each 6N135M, 6N136M, and HCPL4503M
45
mW
(3)
Channel
HCPL2530M and HCPL2531M
DETECTOR
I
(avg) Average Output Current Each
Channel
8
mA
mA
O
I
(pk)
Peak Output Current Each
Channel
16
O
V
Emitter-Base Reverse Voltage 6N135M and 6N136M
5
-0.5 to 30
-0.5 to 20
5
V
V
EBR
V
Supply Voltage
Output Voltage
CC
V
V
O
I
Base Current
6N135M and 6N136M
mA
mW
mW
B
PD
Output Power Dissipation
Each Channel
6N135M, 6N136M, and HCPL4503M
HCPL2530M and HCPL2531M
100
(4)
35
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
3
Electrical Characteristics
A
T = 0°C to 70°C unless otherwise specified. Typical value is measured at T = 25ºC and V = 5.0 V.
A
CC
Individual Component Characteristics
Symbol
Parameter
Test Conditions
Device
Min. Typ. Max. Unit
EMITTER
V
Input Forward Voltage
I = 16 mA, T = 25°C
All
All
All
1.45
1.7
1.8
V
F
F
A
I = 16 mA
F
B
Input Reverse
I = 10 µA
5.0
21
V
VR
R
Breakdown Voltage
ΔV /ΔT Temperature Coefficient I = 16 mA
All
All
-1.7
mV/°C
F
A
F
of Forward Voltage
DETECTOR
I
Logic High Output
Current
I = 0 mA, V = V = 5.5 V,
0.0007 0.5
µA
OH
F
O
CC
T = 25°C
A
I = 0 mA, V = V = 15 V,
6N135M
6N136M
0.0019
1
F
O
CC
T = 25°C
A
HCPL4503M
I = 0 mA, V = V = 15 V
All
50
F
O
CC
I
Logic Low Supply
Current
I = 16 mA, V = Open,
6N135M
6N136M
HCPL4503M
163
200
µA
µA
CCL
F
O
V
= 15 V
CC
I
= I = 16 mA,
HCPL2530M
HCPL2531M
400
1
F1
F2
V = Open, V = 15 V
O
CC
I
Logic High Supply
Current
I = 0 mA, V = Open,
6N135M
6N136M
HCPL4503M
0.0002
0.0004
CCH
F
O
V
= 15 V, T = 25°C
CC
A
I = 0 mA, V = Open,
6N135M
6N136M
HCPL4503M
2
4
F
O
V
= 15 V
CC
I = 0 mA, V = Open,
HCPL2530M
HCPL2531M
F
O
V
= 15 V
CC
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
4
Electrical Characteristics (Continued)
A
T = 0 to 70°C unless otherwise specified. Typical value is measured at T = 25ºC and V = 5.0 V.
A
CC
Transfer Characteristics
Symbol
COUPLED
CTR
Parameter
Test Conditions
Device
Min. Typ. Max. Unit
Current Transfer
I = 16 mA, V = 0.4 V,
6N135M
7
38
38
50
50
%
%
F
V
O
(5)
Ratio
= 4.5 V, T = 25°C
CC A
HCPL2530M
6N136M
19
HCPL4503M
HCPL2531M
6N135M
I = 16 mA,
V
V
V
= 0.4 V
5
%
%
F
OL
OL
OL
V
= 4.5 V
CC
= 0.5 V HCPL2530M
= 0.4 V
6N136M
15
HCPL4503M
V
= 0.5 V HCPL2531M
6N135M
OL
V
Logic LOW Output
Voltage
I = 16 mA, I = 1.1 mA,
0.12
0.20
0.4
0.5
0.4
V
OL
F
O
V
= 4.5 V, T = 25°C
CC
A
HCPL2530M
I = 16 mA, I = 3 mA,
6N136M
F
O
V
= 4.5 V, T = 25°C
HCPL4503M
CC
A
HCPL2531M
6N135M
0.5
0.5
I = 16 mA, I = 0.8 mA,
0.11
0.18
F
O
V
= 4.5 V
CC
HCPL2530M
HCPL4503M
HCPL2531M
I = 16 mA, I = 2.4 mA,
0.5
F
O
V
= 4.5 V
CC
Note:
5. Current Transfer Ratio is defined as a ratio of output collector current, I , to the forward LED input current, I ,
O
F
times 100%.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
A
T = 0 to 70°C unless otherwise specified. Typical values are measured at T = 25°C and V = 5V.
A
CC
Switching Characteristics (V = 5V)
CC
Symbol Parameter
Test Conditions
Device
6N135M
Min.
Typ. Max. Unit
t
Propagation Delay
T = 25°C, R = 4.1 kΩ,
0.23
1.5
µs
PHL
A
L
(6)
Time to Logic LOW I = 16 mA (Figure 15)
F
HCPL2530M
R = 1.9 kΩ, I = 16 mA,
A
6N136M
HCPL4503M
0.25
0.8
µs
L
F
(7)
T = 25°C (Figure 15)
HCPL2531M
(6)
(7)
R = 4.1 kΩ, I = 16 mA
6N135M
HCPL2530M
2.0
1.0
µs
µs
L
F
(Figure 15)
R = 1.9 kΩ, I = 16 mA
6N136M
HCPL4503M
HCPL2531M
L
F
(Figure 15)
t
Propagation Delay
Time to Logic HIGH I = 16 mA (Figure 15)
T = 25°C, (R = 4.1 kΩ,
F
6N135M
0.45
0.26
1.5
0.8
µs
µs
PLH
A
L
(6)
HCPL2530M
(7)
R = 1.9 kΩ, I = 16 mA
A
,
6N136M
HCPL4503M
L
F
T = 25°C (Figure 15)
HCPL2531M
(6)
(7)
R = 4.1 kΩ, I = 16 mA
6N135M
HCPL2530M
2.0
1.0
µs
µs
L
F
(Figure 15)
R = 1.9 kΩ, I = 16 mA
6N136M
HCPL4503M
HCPL2531M
L
F
(Figure 15)
|CM | Common Mode
I = 0 mA, V
= 10 V
,
6N135M
HCPL2530M
10,000
10,000
V/µs
V/µs
H
F
CM
P-P
(8)
Transient
Immunity at
Logic High
R = 4.1 kΩ, T = 25°C
L
A
(Figure 16)
I = 0 mA, V
= 10 V
,
6N136M
HCPL2531M
F
CM
P-P
(8)
R = 1.9 kΩ, T = 25°C
L
A
(Figure 16)
I = 0 mA, V
= 1,500 V
,
F
CM
P-P
(8)
R = 1.9 kΩ, T = 25°C
HCPL4503M 15,000 50,000
L
A
(Figure 16)
|CM |
Common Mode
Transient
Immunity at
Logic Low
I = 16 mA, V
= 10 V
,
6N135M
HCPL2530M
10,000
10,000
V/µs
V/µs
L
F
CM
P-P
(8)
R = 4.1 kΩ, T = 25°C
L
A
(Figure 16)
I = 16 mA, V
= 10 V ,
P-P
6N136M
HCPL2531M
F
CM
(8)
R = 1.9 kΩ (Figure 16)
L
I = 0 mA, V
= 1,500 V
,
F
CM
P-P
(8)
R = 1.9 kΩ, T = 25°C
HCPL4503M 15,000 50,000
L
A
(Figure 16)
Notes:
6. The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1 kΩ pull-up resistor.
7. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and 5.6 kΩ pull-up resistor.
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV /dt on the leading edge
cm
of the common mode pulse signal V , to assure that the output will remain in a logic high state (i.e., V > 2.0 V).
CM
O
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV /dt on the trailing edge
cm
of the common mode pulse signal, V , to assure that the output will remain in a logic low state (i.e., V < 0.8 V).
CM
O
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
T = 0 to 70°C unless otherwise specified. Typical values are measured at T = 25°C and V = 5 V.
A
A
CC
Isolation Characteristics
Symbol
Characteristics
Test Conditions
Min.
Typ.
Max.
Unit
V
Withstand Insulation Test
Voltage
RH ≤ 50%, T = 25°C, I ≤ 10 µA,
5,000
V
ISO
A
I-O
(9)(11)
RMS
t = 1 minute, f = 50 Hz
(9)
11
R
Resistance (Input to Output)
V
= 500 VDC
10
Ω
I-O
I-O
(9)
C
I
Capacitance (Input to Output) f = 1 MHz, V = 0V
1
pF
nA
I-O
I-I
I-O
(10)
Input-Input Insulation
Leakage Current
RH ≤ 45%, V = 500 VDC
t = 5 s, (HCPL2530M/2531M only)
< 1
I-I
(10)
12
R
Input-Input Resistance
V
= 500 VDC
10
0.2
Ω
I-I
I-I
I-I
(HCPL2530M/2531M only)
(10)
C
Input-Input Capacitance
f = 1 MHz
pF
(HCPL2530M/2531M only)
Notes:
9. Device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are
shorted together.
10. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
11. 5,000 V
for 1 minute duration is equivalent to 6,000 V
for 1 second duration.
RMS
RMS
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
7
Typical Performance Curves
For single-channel devices; 6N135M, 6N136M, and HCPL4503M.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
V
= 0.4 V
O
I
V
V
= 16mA
F
Normalized to:
= 16 mA
Normalized to:
T = 25°C
A
= 5 V
CC
= 4.5V
CC
I
F
T
= 25°C
A
= 0.4V
O
0.1
1
10
100
-40
-20
0
20
40
60
80
100
120
I
- FORWARD CURRENT (mA)
T - TEMPERATURE (°C)
A
F
Figure 3. Normalized CTR vs. Forward Current
Figure 4. Normalized CTR vs.Temperature
25
20
15
10
5
1000
100
10
TA = 25°C
CC = 5 V
I
V
V
= 0 mA
F
V
= 5.5 V
CC
= 5.5 V
IF = 40 mA
O
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
1
5 mA
0
0.1
-40
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
T
– TEMPERATURE (°C)
V
– OUTPUT VOLTAGE (V)
A
O
Figure 5. Output Current vs. Output Voltage
Figure 6. Logic High Output Current vs.Temperature
800
700
600
500
400
300
200
100
0
Frequency = 10 kHz
Duty Cycle = 10%
Frequency = 10 kHz
Duty Cycle = 10%
V
= 5 V
CC
V
= 5 V
= 4.1 kΩ (t
)
RL
CC
PLH
1000
I
F
= 16 mA (t )
PLH
I
= 10 mA (t )
PLH
F
RL = 1.9 kΩ (t
PLH
)
I
= 10 mA (t )
PHL
F
RL = 1.9 kΩ (t
PHL
)
RL = 4.1 kΩ (t
)
PHL
I
F
= 16 mA (t
)
PHL
100
-40
-20
0
20
40
60
80
100
120
1
10
T
– TEMPERATURE (°C)
R – LOAD RESISTANCE (kΩ)
L
A
Figure 8. Propagation Delay vs. Load Resistance
Figure 7. Propagation Delay vs.Temperature
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
8
Typical Performance Curves (Continued)
For dual-channel devices; HCPL2530M and HCPL2531M.
1.6
1.4
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
V
= 0.4 V
O
I
V
V
= 16 mA
F
Normalized to:
= 16 mA
Normalized to:
T = 25°C
A
0.4
0.2
0.0
= 5 V
CC
= 4.5 V
CC
= 0.4 V
I
F
T
= 25°C
A
O
0.1
1
10
100
-40
-20
0
20
40
60
80
100
120
I
- FORWARD CURRENT (mA)
T - TEMPERATURE (°C)
A
F
Figure 9. Normalized CTR vs. Forward Current
Figure 10. Normalized CTR vs.Temperature
20
15
10
5
1000
100
10
T
V
= 25°C
CC
A
I
V
V
= 0 mA
F
= 5 V
= 5.5 V
CC
= 5.5 V
O
I
F
= 40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
1
5 mA
0.1
-40
0
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
T
– TEMPERATURE (°C)
V
– OUTPUT VOLTAGE (V)
A
O
Figure 12. Logic High Output Current vs.Temperature
Figure 11. Output Current vs. Output Voltage
600
500
400
300
200
100
0
Frequency = 10 kHz
Duty Cycle = 10%
Frequency = 10 kHz
Duty Cycle = 10%
V
= 5 V
CC
V
= 5 V
CC
T
= 25°C
A
= 4.1 kΩ (t
= 1.9 kΩ (t
)
1000
R
R
PLH
L
)
PHL
L
I
= 10 mA (t
= 16 mA (t
)
)
F
PHL
R
R
= 1.9 kΩ (t
)
PLH
L
I
)
F
PHL
= 4.1 kΩ (t
)
PHL
L
I
= 16 mA (t
F
PLH
I
= 10 mA (t
)
F
PLH
100
-40
-20
0
20
40
60
80
100
120
1
10
T
– TEMPERATURE (°C)
R – LOAD RESISTANCE (kΩ)
L
A
Figure 13. Propagation Delay vs.Temperature
Figure 14. Propagation Delay vs. Load Resistance
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
9
Test Circuits
Noise
Shield
Noise
Shield
Pulse
+
VCC
I
F
V
CC
Generator
tr = 5 ns
+5 V
+5 V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
Pulse
ZO = 50
Ω
R
L
Generator
V
F1
IF
+
VB
tr = 5ns
ZO= 50
10% D.C.
I/f< 100 μs
V01
-
10% DUTY CYCLE
I/f < 100 μS
VO
RL
Ω
VF
-
C
L
= 15 pF
VO
V02
-
VO
I
F
V
F2
0.1 μF
MONITOR
+
0.1 μF
IF Monitor
GND
Rm
Rm
C
L = 15 pF
GND
Test Circuit for HCPL2530M and HCPL2531M
Test Circuit for 6N135M, 6N136M, and HCPL4503M
IF
0
5 V
VO
1.5 V
1.5 V
VOL
TPHL
TPLH
Figure 15. Switching Time Test Circuit
IF
Noise
Shield
Noise
Shield
VCC
V
CC
+
+5 V
+5 V
VO
1
2
3
4
8
7
6
5
1
8
7
6
5
IF
R
L
V
F1
+
VB
V01
-
RL
2
3
4
A
VF
-
A
VO
V02
B
-
0.1 μF
VO
0.1 μF
B
VFF
V
F2
VFF
+
GND
GND
–
VCM
+
-
VCM
-
+
Pulse Gen
Pulse Gen
Test Circuit for HCPL2530M and HCPL2531M
Test Circuit for 6N135M, 6N136M, and HCPL4503M
VCM 10 V
0 V
90% 90%
10%
tr
10%
tf
VO
5 V
Switch at A : IF = 0 mA
VO
VOL
Switch at A : IF = 16 mA
Figure 16. Common Mode Immunity Test Circuit
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
10
Reflow Profile
Maximum Ramp-up Rate = 3°C/S
Maximum Ramp-down Rate = 6°C/S
T
P
260
240
220
200
180
160
140
120
100
80
t
P
T
L
Tsmax
t
L
Preheat Area
Tsmin
t
s
60
40
20
0
120
Time 25°C to Peak
240
360
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
150°C
Temperature Min. (Tsmin)
Temperature Max. (Tsmax)
200°C
Time (t ) from (Tsmin to Tsmax)
60 to 120 s
S
Ramp-up Rate (t to t )
3°C/second maximum
217°C
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60 to 150 s
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
260°C +0°C / –5°C
30 s
P
Ramp-down Rate (T to T )
6°C/s maximum
8 minutes maximum
P
L
Time 25°C to Peak Temperature
Figure 17. Relow Profile
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
11
Ordering Information
Option
No option
S
Example Part Number
6N135M
Description
Standard through hole lead form (50 units per tube)
Surface mount lead bend
6N135SM
SD
6N135SDM
Surface mount; tape and reel
V
6N135VM
DIN EN/IEC60747-5-5
TSV
TSR2
TV
6N135TSVM
6N135TSR2M
6N135TVM
DIN EN/IEC60747-5-5; surface mount
DIN EN/IEC60747-5-5; surface mount; tape and reel
DIN EN/IEC60747-5-5; 0.4" lead spacing
DIN EN/IEC60747-5-5; surface mount
DIN EN/IEC60747-5-5; surface mount; tape and reel
SV
6N135SVM
SDV
6N135SDVM
Marking Information
1
2
6N135
6
V XX YY B
5
3
4
Definitions
1
Fairchild logo
Device number
(1)
2
3
DIN EN/IEC60747-5-5 mark (Note: Only appears on parts
ordered with this option – See order entry table)
4
Two-digit year code, e.g., ‘08’
5
6
Two-digit work week ranging from ‘01’ to ‘53’
Assembly package code
Notes:
1. ‘HCPL’ devices are marked with only the numeric characters
(for example, HCPL4503M is marked as ‘4503’).
2. The ‘M’ suffix is an ordering identifier only. It is used to indicated the
white package version. The ‘M’ does no appear in the top mark.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
12
Package Dimensions
Figure 18. 8-Pin DIP Through Hole
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/N0/N08G.pdf.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
13
Package Dimensions (Continued)
Figure 19. 8-Pin DIP Surface Mount (Option S)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/N0/N08H.pdf.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
14
Package Dimensions (Continued)
Figure 20. 8-Pin DIP Through Hole 0.4” Lead Spacing (Option T)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/N0/N08A.pdf.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
15
Package Dimensions (Continued)
Figure 21. 8-Pin DIP Surface Mount 0.4” Lead Spacing (Option TS)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/N0/N08L.pdf.
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
16
Carrier Tape Specifications (Option SD)
D0
P0
P2
t
E
K0
F
W
W1
P
User Direction of Feed
d
D1
Symbol
Description
Dimension in mm
16.0 0.3
0.30 0.05
4.0 0.1
W
t
Tape Width
Tape Thickness
P
Sprocket Hole Pitch
Sprocket Hole Diameter
Sprocket Hole Location
Pocket Location
0
D
1.55 0.05
1.75 0.10
7.5 0.1
0
E
F
P
2.0 0.1
2
P
Pocket Pitch
12.0 0.1
10.30 0.20
10.30 0.20
4.90 0.20
13.2 0.2
0.1 Maximum
10°
A
Pocket Dimensions
0
0
0
B
K
W
Cover Tape Width
1
d
Cover Tape Thickness
Maximum Component Rotation or Tilt
Minimum Bending Radius
R
30
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
17
Carrier Tape Specifications (Option TSR2)
D0
P0
P2
t
E
K0
F
W
W1
P
User Direction of Feed
d
D1
Symbol
Description
Dimension in mm
24.0 0.3
0.40 0.1
4.0 0.1
W
t
Tape Width
Tape Thickness
P
Sprocket Hole Pitch
Sprocket Hole Diameter
Sprocket Hole Location
Pocket Location
0
D
1.55 0.05
1.75 0.10
11.5 0.1
2.0 0.1
0
E
F
P
2
P
Pocket Pitch
16.0 0.1
12.80 0.1
10.35 0.1
5.7 0.1
A
Pocket Dimensions
0
0
0
B
K
W
Cover Tape Width
21.0 0.1
0.1 Maximum
10°
1
d
Cover Tape Thickness
Maximum Component Rotation or Tilt
Minimum Bending Radius
R
30
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
18
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.11
www.fairchildsemi.com
19
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