74ABT377CMTCX [FAIRCHILD]
Octal D-Type Flip-Flop ; 八D型触发器\n
| 型号： | 74ABT377CMTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop
|
| 文件： | 总9页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1993
Revised November 1999
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
Features
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
■ Clock enable for address and data synchronization
applications
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
■ See ABT273 for master reset version
■ See ABT373 for transparent latch version
■ See ABT374 for 3-STATE version
■ Output sink capability of 64 mA, source capability
of 32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT377CSC
74ABT377CSJ
74ABT377CMSA
74ABT377CMTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Descriptions
Data Inputs
D0–D7
Clock Enable (Active LOW)
Clock Pulse Input
CE
CP
Q0–Q7
Data Outputs
Truth Table
Operating Mode
Inputs
Output
Qn
CP
Dn
CE
I
Load “1”
Load “0”
Hold
h
I
H
I
L
h
X
X
No Change
No Change
(Do Nothing)
X
H
H
X
h
= HIGH Voltage Level
= Immaterial
= HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
L = LOW Voltage Level
= LOW-to-HIGH Clock Transition
I
= LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
© 1999 Fairchild Semiconductor Corporation
DS011550
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Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−65°C to +150°C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
−0.5V to +7.0V
50 mV/ns
20 mV/ns
−30 mA to +5.0 mA
Enable Input
Power-OFF State
−0.5V to +4.75V
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
Twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
−500 mA
Note 2: Either voltage limit or current limit is sufficient to protect inputs
VCC + 4.5V
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
Min
Min
Max
I
I
I
I
IN = −18 mA
OH = −3 mA
OH = −32 mA
OL = 64 mA
2.5
2.0
V
V
VOL
IIH
Output LOW Voltage
Input HIGH Current
0.55
1
V
V
IN = 2.7V (Note 3)
IN = VCC
µA
1
IBVI
Input HIGH Current
Breakdown Test
7
µA
Max
V
IN = 7.0V
IIL
Input LOW Current
−1
−1
V
V
IN = 0.5V (Note 3)
IN = 0.0V
µA
Max
0.0
VID
Input Leakage Test
4.75
V
I
ID = 1.9 µA
All Other Pins Grounded
IOS
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
−100
−275
50
mA
µA
Max
Max
Max
Max
V
V
OUT = 0.0V
OUT = VCC
ICEX
ICCH
ICCL
ICCT
50
µA
All Outputs HIGH
Power Supply Current
30
mA
All Outputs LOW
Maximum ICC/Input
Outputs Enabled
VI = VCC − 2.1V
1.5
0.3
mA
Max
Max
Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open (Note 4)
One bit Toggling, 50% Duty Cycle
ICCD
Dynamic ICC
No Load
mA/
MHz
Note 3: Guaranteed but not tested.
Note 4: For 8 bits toggling, ICCD < 0.5 mA/MHz.
3
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AC Electrical Characteristics
(SOIC Package)
T
A = +25°C
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 50 pF
Max
VCC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
150
2.2
Typ
Max
Min
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay
CP to On
200
150
2.2
2.8
MHz
ns
6.0
6.8
6.0
6.8
2.8
AC Operating Requirements
T
A = +25°C
CC = +5.0V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 50 pF
V
V
Symbol
Parameter
Units
C
C
Min
2.0
2.0
1.8
1.8
3.0
3.0
Max
Min
2.0
2.0
1.8
1.8
3.0
3.0
Max
tS(H)
Setup Time, HIGH
ns
ns
ns
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Setup Time, HIGH
or LOW CE to CP
Hold Time, HIGH
tH(H)
tH(L)
1.0
1.0
1.0
1.0
ns
ns
or LOW CE to CP
Pulse Width, CP,
HIGH or LOW
tW(H)
tW(L)
3.3
3.3
3.3
3.3
Capacitance
(SOIC Package) (Note 5)
Symbol
Parameter
Input Capacitance
Output Capacitance
Typ
5
Units
Conditions
CIN
OUT (Note 5)
pF
pF
V
V
CC = 0V, TA = 25°C
CC = 5.0V
C
9
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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4
AC Loading
*Includes jig and probe capacitance
FIGURE 2. VM = 1.5V
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude Rep. Rate
3.0V 1 MHz
FIGURE 3. Test Input Signal Requirements
tW
tr
tf
500 ns
2.5 ns
2.5 ns
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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