74ABT646CMSAX [FAIRCHILD]
Single 8-bit Bus Transceiver ; 一个8位总线收发器\n
| 型号： | 74ABT646CMSAX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Single 8-bit Bus Transceiver
|
| 文件： | 总9页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1992
Revised November 1999
74ABT646
Octal Transceivers and Registers with 3-STATE Outputs
General Description
Features
The ABT646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ A and B output sink capability of 64 mA, source capabil-
ity of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT646CSC
74ABT646CMSA
74ABT646CMTC
M24B
MSA24
MTC24
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
B0–B7
CPAB, CPBA
SAB, SBA
OE
Select Inputs
Output Enable Input
DIR
Direction Control Input
© 1999 Fairchild Semiconductor Corporation
DS010978
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Truth Table
Inputs
Data I/O
(Note 1)
Function
OE
DIR
CPAB CPBA
SAB
SBA A0–A7 B0–B7
H
H
H
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
Isolation
X
X
X
X
X
X
X
L
Input
Input Clock An Data into A Register
Clock Bn Data into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
L
Input Output Clock An Data into A Register
A Register to Bn (Stored Mode)
H or L
H
H
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An—Real Time (Transparent Mode)
Output Input Clock Bn Data into B Register
X
X
X
X
L
L
L
H or L
H
H
B Register to An (Stored Mode)
L
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
FIGURE 1.
FIGURE 3.
Real Time Transfer
B-Bus to A-Bus
Transfer from
Register to Bus
FIGURE 2.
FIGURE 4.
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disable or
−0.5V to +7.0V
50 mV/ns
20 mV/ns
100 mV/ns
−30 mA to +5.0 mA
Enable Input
Clock Input
Power-Off State
−0.5V to +5.5V
−0.5V to VCC
in the HIGH State
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500 mA
10V
DC Electrical Characteristics
VCC
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
VIH
2.0
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
I
I
I
I
IN = −18 mA (Non I/O Pins)
OH = −3 mA, (An, Bn)
OH = −32 mA, (An, Bn)
OL = 64 mA, (An, Bn)
2.5
2.0
VOL
VID
IIH
Output LOW Voltage
Input Leakage Test
Input HIGH Current
0.55
4.75
V
0.0
I
ID = 1.9 µA, (Non-I/O Pins)
All Other Pins Grounded
1
1
V
V
IN = 2.7V (Non-I/O Pins) (Note 4)
IN = VCC (Non-I/O Pins)
µA
µA
µA
µA
Max
Max
Max
Max
IBVI
IBVIT
IIL
Input HIGH Current
Breakdown Test
7
V
V
IN = 7.0V (Non-I/O Pins)
IN = 5.5V (An, Bn)
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
100
−1
−1
V
V
IN = 0.5V (Non-I/O Pins) (Note 4)
IN = 0.0V (Non-I/O Pins)
I
I
IH + IOZH Output Leakage Current
IL + IOZL Output Leakage Current
10
µA
µA
0V–5.5V
0V–5.5V
V
OUT = 2.7V (An, Bn); OE = 2.0V
−10
V
V
V
V
OUT = 0.5V (An, Bn); OE = 2.0V
OUT = 0V (An, Bn)
IOS
ICEX
IZZ
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
Max
Max
0.0V
OUT = VCC (An, Bn)
100
OUT = 5.5V (An, Bn);
All Others GND
ICCH
ICCL
ICCZ
ICCT
Power Supply Current
Power Supply Current
Power Supply Current
Additional ICC/Input
250
30
µA
mA
µA
Max
Max
Max
Max
All Outputs HIGH
All Outputs LOW
50
Outputs 3-STATE; All Others GND
2.5
mA
VI = VCC − 2.1V
All Other Outputs at VCC or GND
Outputs OPEN
ICCD
Dynamic ICC
(Note 4)
No Load
0.18
mA/MHz
Max
OE and DIR = GND,
Non-I/O = GND or VCC (Note 5)
One Bit toggling, 50% duty cycle
Note 4: Guaranteed but not tested.
Note 5: For 8-bit toggling, ICCD < 1.4 mA/MHz.
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4
DC Electrical Characteristics
Conditions
VCC
Symbol
Parameter
Min
Typ
Max
Units
C
L = 50 pF, RL = 500Ω
VOLP
VOLV
VOHV
VIHD
VILD
Quiet Output Maximum Dynamic VOL
0.6
−0.9
3.0
0.8
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
TA = 25°C (Note 6)
TA = 25°C (Note 6)
TA = 25° (Note 7)
TA = 25°C (Note 8)
TA = 25°C (Note 8)
Quiet Output Minimum Dynamic VOL
−1.2
2.5
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.2
1.8
0.8
0.5
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
T
A = +25°C
T
A = −55°C to +125°C
CC = 4.5V–5.5V
L = 50 pF
Max
T
A = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
CL = 50 pF
Min
200
1.7
1.7
1.5
1.5
1.5
1.5
1.5
1.5
Typ
Max
Min
200
2.2
1.7
1.5
1.5
1.5
1.5
1.0
1.9
Min Max
fMAX
Maximum Clock Frequency
Propagation Delay
Clock to Bus
200
1.7
1.7
1.5
1.5
1.5
1.5
1.5
1.5
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
3.0
3.4
2.6
3.0
3.0
3.4
3.2
3.5
5.6
5.6
4.8
4.8
5.9
5.9
6.3
6.3
8.8
8.8
7.9
7.9
8.1
8.9
7.3
8.8
5.6
5.6
4.8
4.8
5.9
5.9
6.3
6.3
Propagation Delay
Bus to Bus
ns
ns
ns
Propagation Delay
SBA or SAB to An to Bn
Enable Time
OE to Anor Bn
Disable Time
tPHZ
tPLZ
1.5
1.5
3.7
3.2
6.0
6.0
1.5
1.5
9.3
9.3
1.5
1.5
6.0
6.0
ns
ns
ns
OE to Anor Bn
Enable Time
tPZH
tPZL
tPHZ
tPLZ
1.5
1.5
1.5
1.5
3.4
3.7
3.8
3.2
6.3
6.3
6.0
6.0
1.0
2.2
1.5
1.5
7.7
9.5
8.7
9.2
1.5
1.5
1.5
1.5
6.3
6.3
6.0
6.0
DIR to An or B n
Disable Time
DIR to An or B n
AC Operating Requirements
T
A = +25°C
CC = +5.0V
L = 50 pF
Max
T
A = −55°C to +125°C
CC = 4.5V–5.5V
L = 50 pF
Max
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
Max
V
V
V
Symbol
Parameter
Units
C
C
C
Min
Min
Min
tS(H)
Setup Time, HIGH
1.5
1.5
3.0
1.0
4.0
1.5
ns
ns
ns
tS(L)
or LOW Bus to Clock
Hold Time, HIGH
or LOW Bus to Clock
Pulse Width,
tH(H)
1.0
3.0
1.0
3.0
1.0
3.0
t
H(L)
tW(H)
tW(L)
HIGH or LOW
5
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Extended AC Electrical Characteristics
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
V
C
C
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 9)
1 Output Switching
(Note 10)
8 Outputs Switching
(Note 11)
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max
5.5
5.5
6.0
6.0
6.0
6.0
6.0
6.0
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
7.5
7.5
7.0
7.0
7.5
7.5
8.0
8.0
Min
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Max
10.0
10.0
9.5
tPLH
Propagation Delay
ns
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
Clock to Bus
Propagation Delay
Bus to Bus
ns
ns
9.5
Propagation Delay
SBA or SAB to An or Bn
Output Enable Time
10.0
10.0
10.5
10.5
ns
ns
OEn or DIR to An or Bn
Output Disable Time
OEn or DIR to An or Bn
tPHZ
tPLZ
1.5
1.5
6.0
6.0
(Note 12)
(Note 12)
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 12: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
C
C
Symbol
Parameter
Units
8 Outputs Switching
8 Outputs Switching
(Note 13)
Max
1.3
(Note 14)
Max
2.5
tOSHL (Note 15) Pin to Pin Skew, HL Transitions
tOSLH (Note 15) Pin to Pin Skew, LH Transitions
ns
ns
ns
ns
ns
1.0
2.0
t
PS (Note 16)
OST (Note 15)
tPV (Note 17)
Duty Cycle, LH–HL Skew
2.0
4.0
t
Pin to Pin Skew, LH/HL Transitions
Device to Device Skew, LH/HL Transitions
2.0
4.0
2.5
4.5
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST). This specification is guaranteed but not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
T
A = 25°C
CIN
CI/O (Note 18)
Input Capacitance
Output Capacitance
5
pF
pF
V
V
CC = 0V (non I/O pins)
CC = 5.0V (An, Bn)
11
Note 18: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012.
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6
AC Loading
*Includes jig and probe capacitance
FIGURE 6. Test Input Signal Levels
Input Pulse Requirements
FIGURE 5. Standard AC Test Load
Amplitude Rep. Rate
3.0V 1 MHz
tW
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 7. Test Input Signal Requirements
AC Waveforms
FIGURE 8. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
FIGURE 10. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 11. Setup Time, Hold Time
and Recovery Time Waveforms
FIGURE 9. Propagation Delay,
Pulse Width Waveforms
7
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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