74AC161_03 [FAIRCHILD]
Synchronous Presettable Binary Counter; 同步可预置二进制计数器
| 型号： | 74AC161_03 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Synchronous Presettable Binary Counter |
| 文件： | 总11页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised September 2003
74AC161 • 74ACT161
Synchronous Presettable Binary Counter
General Description
Features
The AC/ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
■ ICC reduced by 50%
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count rate of 125 MHz
■ Outputs source/sink 24 mA
■ ACT161 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC161SC
74AC161SJ
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC161MTC
74AC161PC
74ACT161SC
74ACT161SJ
74ACT161MTC
74ACT161PC
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M16A
M16D
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
Description
CEP
CET
CP
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
MR
Asynchronous Master Reset Input
Parallel Data Inputs
P0–P3
PE
Parallel Enable Inputs
Flip-Flop Outputs
Q0–Q3
TC
Terminal Count Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS009931
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its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Functional Description
The AC/ACT161 count in modulo-16 binary sequence.
From state 15 (HHHH) they increment to state 0 (LLLL).
The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the AC/ACT161) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous reset, parallel load, count-up and hold. Five
control inputs—Master Reset, Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET)—
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on PE overrides counting and allows information on
the Parallel Data (Pn) inputs to be loaded into the flip-flops
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
Action on the Rising
PE
CET
CEP
Clock Edge (
Reset (Clear)
)
X
L
X
X
H
L
X
X
H
X
L
Load (Pn→Qn)
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
on the next rising edge of CP. With PE and MR HIGH, CEP
and CET permit counting when both are HIGH. Conversely,
a LOW signal on either CEP or CET inhibits counting.
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
The AC/ACT161 use D-type edge-triggered flip-flops and
changing the PE, CEP, and CET inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
State Diagram
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
the Up mode, or min to max in the Down mode, to start its
final cycle. Since this final cycle requires 16 clocks to com-
plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
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2
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
5.5
±0.1
±1.0
µA
VI = VCC, GND
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
IOHD
−75
ICC
5.5
4.0
40.0
µA
(Note 4)
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
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4
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
OUT = −50 µA
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
V
V
V
V
V
IN = VIL or VIH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
I
I
I
OH = −24 mA
OH = −24 mA (Note 5)
OUT = 50 µA
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
70
Typ
111
167
7.0
5.0
7.0
5.0
9
Max
Min
fMAX
Maximum Count
60
95
MHz
ns
Frequency
5.0
110
2.0
1.5
1.5
1.5
3.0
2.0
3.5
2.0
2.0
1.5
2.5
2.0
2.0
1.5
3.5
2.5
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
3.3
12
9.0
12
1.5
1.0
1.5
1.5
2.5
1.5
2.5
2.0
1.5
1.0
2.0
1.5
1.5
1.5
3.0
2.5
13.5
9.5
5.0
3.3
13
ns
5.0
9.5
15
10
3.3
16.5
11.5
15.5
11.5
11
ns
5.0
6
10.5
14
Propagation Delay
CP to TC
3.3
8.5
6.5
5.5
3.5
6.5
5
ns
5.0
11
Propagation Delay
CET to TC
3.3
9.5
6.5
11
ns
5.0
7.5
Propagation Delay
CET to TC
3.3
12.5
9.5
ns
5.0
8.5
12
Propagation Delay
MR to Qn
3.3
6.5
5.5
10
13.5
10
ns
5.0
9.5
15
Propagation Delay
MR to TC
3.3
17.5
13.5
ns
5.0
8.5
13
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
5
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AC Operating Requirements for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
tS
tH
tS
tH
tS
tH
tW
Setup Time, HIGH or LOW
Pn to CP
6.0
3.5
13.5
16
10.5
−0.5
0
ns
ns
ns
ns
ns
ns
ns
ns
5.0
8.5
−1
0
Hold Time, HIGH or LOW
3.3
−7.0
−4.0
6.5
Pn to CP
5.0
Setup Time, HIGH or LOW
PE to CP
3.3
11.5
7.5
0
14
8.5
0
5.0
4.0
Hold Time, HIGH or LOW
PE to CP
3.3
−6.0
−3.5
3.0
5.0
0.5
6.0
4.5
0
1
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width
(Load) HIGH or LOW
Clock Pulse Width
(Count) HIGH or LOW
3.3
7
5.0
2.0
5
3.3
−3.5
−2
0
5.0
0
0.5
4
3.3
2.0
3.5
2.5
4.0
3.0
5.0
2.0
3
tW
3.3
2.0
4.5
3.5
5.0
2.0
tW
MR Pulse Width,
LOW
3.3
5.0
3.0
2.5
−2
5.5
4.5
−0.5
0
7.5
6.0
0
ns
ns
tREC
Recovery Time
MR to CP
−1
0.5
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min Max
fMAX
Maximum Count
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
115
125
5.5
6.0
7.0
8.0
5.5
6.5
6.0
8.0
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
MHz
ns
Frequency
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
1.5
1.5
2.0
1.5
1.5
1.5
1.5
2.5
9.5
10.5
11.0
12.5
8.5
10.5
11.5
12.5
13.5
10.0
10.5
11.0
14.5
ns
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
9.5
ns
Propagation Delay
MR to Qn
10.0
13.5
ns
Propagation Delay
MR to TC
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
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6
AC Operating Requirements for ACT
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
tH
tS
tH
tS
tH
tW
tW
Setup Time, HIGH or LOW
Pn to CP
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
−5.0
4.0
9.5
11.5
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time, HIGH or LOW
0
0
P
n to CP
Setup Time, HIGH or LOW
PE to CP
8.5
9.5
Hold Time, HIGH or LOW
PE to CP
−5.5
2.5
−0.5
5.5
0
−0.5
6.5
0
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width,
(Load) HIGH or LOW
Clock Pulse Width,
(Count) HIGH or LOW
−3.0
2.0
3.0
3.0
3.5
3.5
2.0
tW
MR Pulse Width, LOW
Recovery Time
MR to CP
5.0
5.0
3.0
0
3.0
0
7.5
0.5
ns
ns
tREC
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
45.0
7
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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