74AC240SJ [FAIRCHILD]
Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器
| 型号： | 74AC240SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC240 • 74ACT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The AC/ACT240 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus oriented transmitter or receiver which provides
improved PC board density.
■ ICC and IOZ reduced by 50%
■ Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
■ Outputs source/sink 24 mA
■ ACT240 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC240SC
74AC240SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC240MTC
74AC240PC
74ACT240SC
74ACT240SJ
74ACT240MTC
74ACT240PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
IEEE/IEC
Pin Names
Description
OE1, OE2
I0–I7
3-STATE Output Enable Inputs
Inputs
O0–O7
Outputs
Truth Tables
Inputs
OE1
Outputs
In
(Pins 12, 14, 16, 18)
L
L
L
H
X
H
L
H
Z
Connection Diagram
Inputs
OE2
Outputs
In
(Pins 3, 5, 7, 9)
L
L
L
H
X
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009941
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
−40°C to +85°C
O = VCC + 0.5V
Minimum Input Edge Rate (∆V/∆t)
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
125 mV/ns
or Sink Current (IO)
±50 mA
Minimum Input Edge Rate (∆V/∆t)
DC VCC or Ground Current
per Output Pin (ICC or IGND
ACT Devices
VIN from 0.8V to 2.0V
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
CC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for AC
T
A = +25°C
TA = −40°C to +85°C
VCC
(V)
Symbol
VIH
Parameter
Units
Conditions
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
1.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
IOZ
Maximum 3-STATE
Leakage Current
5.5
±0.25
±2.5
V
V
V
V
O = VCC, GND
IOLD
IOHD
Minimum Dynamic
5.5
5.5
5.5
75
mA
mA
µA
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
40.0
ICC (Note 4) Maximum Quiescent Supply Current
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
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2
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
5.5
5.5
5.5
±0.1
±1.0
±2.5
1.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
IOZ
±0.25
VO = VCC, GND
ICCT
0.6
mA
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
−75
V
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ
6.0
4.5
5.5
4.5
6.0
5.0
7.0
5.5
7.0
6.5
7.5
6.5
Max
8.0
Min
tPLH
Propagation Delay
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.0
7.0
ns
ns
ns
ns
ns
ns
Data to Output
5.0
6.5
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Data to Output
3.3
8.0
8.5
5.0
6.0
6.5
Output Enable Time
3.3
10.5
7.0
11.0
8.0
5.0
Output Enable Time
Output Disable Time
Output Disable Time
3.3
10.0
8.0
11.0
8.5
5.0
3.3
10.0
9.0
10.5
9.5
5.0
3.3
10.5
9.0
11.5
9.5
5.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 8)
Min
Typ
Max
Min
tPLH
Propagation Delay
5.0
5.0
1.5
6.0
5.5
8.5
1.5
1.5
9.5
8.5
ns
ns
Data to Output
tPHL
Propagation Delay
Data to Output
1.5
7.5
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.5
2.0
2.0
2.5
7.0
7.0
8.0
6.5
8.5
9.5
1.0
1.5
2.0
2.0
9.5
ns
ns
ns
ns
10.5
10.5
10.5
9.5
10.0
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
45.0
V
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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