74AC377SC [FAIRCHILD]
Octal D-Type Flip-Flop with Clock Enable; 八路D型触发器与时钟使能
| 型号： | 74AC377SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with Clock Enable |
| 文件： | 总9页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC377 • 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
Features
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
■ ICC reduced by 50%
■ Ideal for addressable register applications
■ Clock enable for address and data synchronization
applications
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
■ Outputs source/sink 24 mA
■ See 273 for master reset version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
■ ACT377 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC377SC
74AC377SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377MTC
74AC377PC
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
CE
Clock Enable (Active LOW)
Data Outputs
Q0–Q7
CP
Clock Pulse Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009961
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Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
CE
Outputs
Operating Mode
CP
Dn
Qn
Load ‘1'
L
L
H
L
H
Load ‘0'
L
Hold (Do Nothing)
H
H
X
X
No Change
No Change
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
2.25
2.75
1.5
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
VOUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
VI = VCC,
5.5
± 0.1
± 1.0
µA
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
GND
5.5
5.5
75
mA
mA
VOLD = 1.65V Max
IOHD
−75
VOHD = 3.85V Min
ICC
5.5
4.0
40.0
µA
VIN = VCC or GND
(Note 4)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC −0.1V
OUT = 0.1V
or VCC −0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
Typ
125
175
8.0
6.0
8.5
6.5
Max
Min
75
Max
fMAX
Maximum Clock
90
140
3.0
2.0
3.5
2.5
MHz
ns
Frequency
5.0
125
1.5
1.5
2.0
1.5
tPLH
Propagation Delay
CP to Qn
3.3
13.0
9.0
14.0
10.0
14.5
11.0
5.0
tPHL
Propagation Delay
CP to Qn
3.3
13.0
10.0
ns
5.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements for AC
VCC
TA = +25°C
TA = −40°C to +85°C
C
L = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
3.5
2.5
Guaranteed Minimum
tS
tH
tS
tH
tW
Setup Time, HIGH or LOW
Dn to CP
5.5
4.0
0
6.0
4.5
0
ns
ns
ns
ns
ns
5.0
Hold Time, HIGH or LOW
3.3
−2.0
−1.0
4.0
Dn to CP
5.0
1.0
6.0
4.0
0
1.0
7.5
4.5
0
Setup Time, HIGH or LOW
CE to CP
3.3
5.0
2.5
Hold Time, HIGH or LOW
CE to CP
3.3
−3.5
−2.0
3.5
5.0
1.0
5.5
4.0
1.0
6.0
4.5
CP Pulse Width
HIGH or LOW
3.3
5.0
2.5
Note 8: Voltage Range 3.3 is 3.0V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
(V)
C
L = 50 pF
C
Units
(Note 9)
Min
Typ
Max
Min
fMAX
Maximum Clock
5.0
5.0
5.0
140
175
6.5
7.0
125
2.5
2.5
MHz
ns
Frequency
tPLH
Propagation Delay
CP to Qn
3.0
3.5
9.0
10.0
11.0
tPHL
Propagation Delay
CP to Qn
10.0
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
tH
tS
tH
tW
Setup Time, HIGH or LOW
5.0
5.0
5.0
5.0
5.0
2.5
4.5
1.0
4.5
1.0
4.0
5.5
ns
ns
ns
ns
ns
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
−1.0
2.5
1.0
5.5
1.0
4.5
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH or LOW
CE to CP
−1.0
2.0
CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Parameter
Typ
Units
Conditions
Input Capacitance
4.5
pF
pF
V
CC = OPEN
CC = 5.0V
Power Dissipation Capacitance
90.0
V
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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