74AC573 [FAIRCHILD]
Octal Latch with 3-STATE Outputs; 八进制锁存器与3态输出
| 型号： | 74AC573 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Latch with 3-STATE Outputs |
| 文件： | 总10页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised October 1999
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE) inputs.
Features
■ ICC and IOZ reduced by 50%
■ Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
■ Useful as input or output port for microprocessors
■ Functionally identical to 74AC373 and 74ACT373
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ 74ACT573 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC573SC
74AC573SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC
74AC573PC
74ACT573SC
74ACT573SJ
74ACT573MTC
74ACT573PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Data Inputs
Latch Enable Input
D0–D7
LE
OE
3-STATE Output Enable Input
3-STATE Latch Outputs
O0–O7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009973
www.fairchildsemi.com
Functional Description
The 74AC573 and 74ACT573 contain eight D-type latches
with 3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
present on the D-type inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the buff-
ers are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D-type input changes.
When LE is LOW the latches store the information that was
Truth Table
Inputs
Outputs
OE
LE
D
On
L
L
H
H
L
H
L
H
L
L
X
X
O0
Z
H
X
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
= Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
ACT Devices
or Sink Current (IO)
±50 mA
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Storage Temperature (TSTG
Junction Temperature (TJ)
(PDIP)
)
−65°C to +150°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for AC
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
1.5
2.1
2.1
3.15
3.85
0.9
V
= 0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
V
= 0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
I
= −50 µA
OUT
OH
4.4
4.4
5.4
5.4
V
= V or V
IN
OH
OH
OH
IL
IH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
= −12 mA
= −24 mA
V
V
V
= −24 mA (Note 2)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
OL
IL
IH
3.0
4.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
75
I
I
I
= 12 mA
= 24 mA
= 24 mA (Note 2)
I
(Note 3) Maximum Input Leakage Current
µA
mA
mA
V = V , GND
IN
I
CC
I
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
V
V
= 1.65V Max
OLD
OLD
OHD
I
−75
= 3.85V Min
OHD
I
CC
5.5
4.0
40.0
µA
V
= V or GND
IN CC
(Note 3)
I
Maximum 3-STATE
Leakage Current
V (OE) = V , V
I IL IH
OZ
5.5
±0.25
±2.5
µA
V = V , GND
I
CC
V
= V , GND
CC
O
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics for AC
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 5)
3.3
Units
L
Min
0.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
Typ
8.5
5.5
8.5
6.0
8.5
6.0
9.0
6.0
Max
10.5
7.0
Min
Max
t
Propagation Delay
to O
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
11.0
7.5
PHL
ns
ns
ns
ns
t
D
5.0
PLH
n
n
t
Propagation Delay
LE to O
3.3
12.0
8.0
12.5
8.5
PLH
t
5.0
PHL
n
t
Output Enable Time
3.3
13.0
8.5
13.5
9.0
PZL
t
5.0
PZH
t
Output Disable Time
3.3
14.5
9.5
15.0
10.0
PHZ
t
5.0
PLZ
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Operating Requirements for AC
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 6)
3.3
Units
L
Typ
0
Guaranteed Minimum
t
Setup Time, HIGH or LOW
3.0
3.0
1.5
1.5
4.0
4.0
3.0
3.0
1.5
1.5
4.0
4.0
S
ns
ns
ns
D
to LE
5.0
0
n
t
t
Hold Time, HIGH or LOW
to LE
3.3
0
H
W
D
5.0
0
n
LE Pulse Width, HIGH
3.3
2.0
2.0
5.0
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
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4
DC Electrical Characteristics for ACT
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
Typ
1.5
1.5
1.5
5.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
IH
OUT
V
V
V
2.0
0.8
1.5
4.4
5.4
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
V
= 0.1V
IL
OUT
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
4.5
5.5
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IN
OH
OH
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
= −24 mA
= −24 mA (Note 7)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
= 24 mA
= 24 mA (Note 7)
I
I
I
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
IN
5.5
5.5
5.5
±0.1
±1.0
±2.5
1.5
µA
µA
V = V , GND
I CC
V = V , V
OZ
I
IL
IH
±0.25
V
= V , GND
CC
O
CCT
0.6
mA
V = V − 2.1V
I
CC
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
= 1.65V Max
= 3.85V Min
OLD
OHD
CC
OLD
−75
OHD
5.5
4.0
40.0
µA
V
= V or GND
IN CC
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for ACT
V
T
= +25°C
= 50 pF
Typ
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 9)
Min
Max
Min
Max
t
t
t
Propagation Delay
to O
PLH
5.0
5.0
5.0
2.5
6.0
6.0
5.5
10.5
2.0
2.5
2.0
12.0
12.0
10.5
ns
ns
ns
D
PHL
PLH
n
n
Propagation Delay
LE to O
3.0
2.5
10.5
9.5
n
t
Propagation Delay
LE to O
PHL
n
t
t
t
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
2.5
1.5
5.5
5.5
6.5
5.0
10.0
9.5
1.5
1.5
1.5
1.0
11.0
10.5
12.5
9.5
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
11.0
8.5
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
5
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AC Operating Requirements for ACT
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 10)
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
S
5.0
1.5
3.0
3.5
ns
D
to LE
n
Hold Time, HIGH or LOW
to LE
H
W
5.0
5.0
−1.5
0
0
ns
ns
D
n
LE Pulse Width, HIGH
2.0
3.5
4.0
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
C
Input Capacitance
5.0
pF
V
V
= OPEN
= 5.0V
IN
CC
CC
Power Dissipation Capacitance for AC
for ACT
25.0
42.0
PD
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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