74AC646 [FAIRCHILD]
Octal Transceiver/Register with 3-STATE Outputs; 八路收发器/寄存器与3态输出
| 型号： | 74AC646 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transceiver/Register with 3-STATE Outputs |
| 文件： | 总10页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised December 1998
74AC646 • 74ACT646
Octal Transceiver/Register with 3-STATE Outputs
General Description
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data transfers
■ 3-STATE outputs
The AC/ACT646 consist of registered bus transceiver cir-
cuits, with outputs, D-type flip-flops and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental data handling
functions available are illustrated in Figure 1, Figure 2, Fig-
ure 3, and Figure 4.
■ 300 mil dual-in-line package
■ Outputs source/sink 24 mA
■ ACT646 has TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC646SC
M24B
N24C
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74AC646SPC
74ACT646SPC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
Pin Descriptions
Pin Names
Description
A0–A7
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
B0–B7
CPAB, CPBA Clock Pulse Inputs
SAB, SBA
Transmit/Receive Inputs
Output Enable Input
G
DIR
Direction Control Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010132.prf
www.fairchildsemi.com
Function Table
Inputs
DIR CPAB CPBA SAB SBA
Data I/O (Note 1)
Function
G
A0–A7
B0–B7
H
X
H or L H or
L
X
X
Isolation
H
H
L
L
L
L
L
L
L
L
X
X
H
H
H
H
L
X
X
X
L
X
X
X
X
X
X
L
Input
Input Clock An Data into A Register
Clock Bn Data into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
Output Clock An Data into A Register
A Register to Bn (Stored Mode)
L
Input
H or L
H
H
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An —Real Time (Transparent Mode)
Input Clock Bn Data into B Register
B Register to An (Stored Mode)
X
X
X
X
L
L
Output
L
H or L
H
H
L
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
FIGURE 3.
FIGURE 1.
Transfer from
Register to Bus
Real Time Transfer
B-Bus to A-Bus
FIGURE 4.
FIGURE 2.
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
AC
)
−20 mA
+20 mA
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
or Sink Current (IO)
±50 mA
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
V
= 0.1V
OUT
IH
2.25
2.75
1.5
3.15
3.85
0.9
V
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
V
= 0.1V
OUT
IL
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
I
= −50 µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V
IL IH
IN
OH
OH
OH
OUT
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
I
= −12 mA
V
V
= −24 mA
= −24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
= 50 µA
OL
0.1
0.1
0.1
0.1
V
= V or V
IN
OH
OL
OH
IL
IH
3.0
4.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
75
I
I
I
= 12 mA
= 24 mA
V
= 24 mA (Note 3)
I
I
I
I
I
(Note 5) Maximum Input Leakage Current
µA
mA
mA
µA
V = V , GND
IN
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max
OLD
OHD
OLD
OHD
Output Current (Note 4)
−75
= 3.85V Min
(Note 5) Maximum Quiescent Supply Current
8.0
80.0
= V or GND
IN CC
CC
Maximum I/O
V (OE) = V , V
I IL IH
OZT
Leakage Current
5.5
±0.6
±6.0
µA
V = V , GND
I
CC
V
= V , GND
CC
O
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
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4
DC Electrical Characteristics for ACT
Symbol
Parameter
V
T
= +25°C
T = −40°C to +85°C
A
Units
Conditions
CC
A
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
V
= 0.1V
IH
OUT
1.5
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
Maximum LOW Level
Input Voltage
1.5
V
= 0.1V
IL
OUT
1.5
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
= −50 µA
OH
OUT
V
= V or V
IN
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
I
= −24 mA
OH
OH
OUT
= −24 mA (Note 6)
V
Maximum LOW Level
Output Voltage
0.001
0.001
= 50 µA
OL
0.1
0.1
V
= V or V
IL IH
IN
4.5
5.5
5.5
0.36
0.36
± 0.1
0.44
0.44
± 1.0
V
I
= 24 mA
OL
OL
I
= 24 mA (Note 6)
Maximum Input
Leakage Current
µA
mA
V = V , GND
I CC
Maximum
V = V − 2.1V
I
CC
5.5
0.6
1.5
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
75
−75
80.0
mA
mA
µA
V
V
= 1.65V Max
= 3.85V Min
OLD
OHD
CC
OLD
OHD
8.0
V
= V
IN CC
or GND
V (OE) = V , V
IH
I
Maximum I/O
OZT
I
IL
Leakage Current
5.5
±0.6
±6.0
µA
V = V , GND
I
CC
V
= V , GND
CC
O
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 8)
3.3
Units
ns
L
Min
4.0
2.5
3.0
2.0
2.5
1.5
1.5
1.5
2.0
1.5
Typ
10.5
7.5
9.5
6.5
7.5
5.0
7.5
5.0
8.5
6.0
Max
16.5
12.0
14.5
10.5
12.0
8.0
Min
Max
t
Propagation Delay
3.0
2.0
2.5
1.5
2.0
1.0
1.5
1.0
1.5
1.5
18.5
13.0
16.0
11.5
13.5
9.0
PLH
Clock to Bus
5.0
t
Propagation Delay
Clock to Bus
3.3
ns
PHL
5.0
t
Propagation Delay
Bus to Bus
3.3
ns
PLH
5.0
t
Propagation Delay
Bus to Bus
3.3
12.5
9.0
13.5
9.5
ns
PHL
5.0
t
Propagation Delay
3.3
13.5
10.0
15.5
11.0
PLH
SBA or SAB to A or B
5.0
ns
n
n
(w/ A or B HIGH or LOW)
n
n
t
Propagation Delay
SBA or SAB to A or B
3.3
5.0
1.5
1.5
8.5
6.0
13.5
10.0
1.5
1.5
15.0
11.0
PHL
ns
ns
n
n
(w/ A or B HIGH or LOW)
n
n
t
Enable Time
G to A or B
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.5
2.0
1.5
12.5
9.0
PZH
n
n
5
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AC Electrical Characteristics for AC (Continued)
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 8)
3.3
Units
ns
L
Min
2.5
1.5
3.0
2.0
2.0
1.5
2.0
1.5
2.5
1.5
2.5
1.5
1.5
1.5
Typ
7.5
5.5
8.0
6.5
7.5
6.0
6.5
5.0
7.0
5.0
7.5
5.5
7.5
5.5
Max
12.5
9.0
Min
Max
t
t
t
t
t
t
t
Enable Time
G to A or B
2.0
1.5
2.5
2.0
2.0
1.5
1.5
1.0
2.0
1.0
1.5
1.5
1.5
1.5
14.0
10.0
13.5
11.0
13.5
10.5
12.0
8.5
PZL
5.0
n
n
Disable Time
G to A or B
3.3
12.5
10.0
12.0
9.5
ns
PHZ
PLZ
PZH
PZL
PHZ
PLZ
5.0
n
n
Disable Time
G to A or B
3.3
ns
5.0
n
n
Enable Time
3.3
11.0
7.5
ns
DIR to A or B
n
5.0
n
n
n
n
Enable Time
3.3
11.5
8.0
13.0
9.0
ns
DIR to A or B
n
5.0
Disable Time
3.3
11.5
9.5
12.5
10.0
13.5
10.5
ns
DIR to A or B
n
5.0
Disable Time
3.3
12.0
9.5
ns
DIR to A or B
5.0
n
Note 8: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements for AC
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
ns
L
(Note 9)
3.3
Typ
2.0
Guaranteed Minimum
t
Setup Time, HIGH or LOW
Bus to Clock
5.0
5.5
4.5
0
S
5.0
1.5
4.0
0
t
t
Hold Time, HIGH or LOW
Bus to Clock
3.3
−1.5
−0.5
2.0
ns
H
W
5.0
0.5
3.5
3.5
1.0
4.5
3.5
Clock Pulse Width
HIGH or LOW
3.3
ns
5.0
2.0
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
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6
AC Electrical Characteristics for ACT
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 10)
5.0
Units
ns
L
Min
Typ
Max
Min
Max
t
t
t
t
t
Propagation Delay
3.5
12.0
14.5
3.0
3.5
2.5
2.0
16.0
16.0
11.5
11.5
PLH
Clock to Bus
Propagation Delay
Clock to Bus
5.0
5.0
5.0
4.0
3.0
2.5
12.0
8.5
14.5
10.5
10.5
ns
PHL
PLH
PHL
PLH
Propagation Delay
Bus to Bus
ns
Propagation Delay
Bus to Bus
8.5
ns
Propagation Delay
SBA or SAB to A to B
5.0
5.0
3.0
3.0
9.5
9.5
11.5
11.5
2.5
2.5
12.5
12.5
ns
ns
n
n
n
(w/A or B
n
n
HIGH or LOW)
t
Propagation Delay
PHL
SBA or SAB to A to B
n
(w/A or B
n
n
HIGH or LOW)
Enable Time
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
3.5
5.0
3.5
2.0
3.5
5.0
3.5
9.0
9.0
11.0
11.0
13.0
12.5
10.5
10.5
12.5
12.5
1.5
3.0
4.5
3.0
1.5
3.0
4.5
3.0
12.0
12.0
14.5
14.0
11.5
11.5
13.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
G to A or B
n
n
Enable Time
G to A or B
n
n
Disable Time
G to A or B
10.5
10.0
6.5
n
n
Disable Time
G to A or B
n
n
Enable Time
DIR to A or B
n
n
n
n
n
Enable Time
6.5
DIR to A or B
n
Disable Time
8.5
DIR to A or B
n
Disable Time
8.5
DIR to A or B
n
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
7
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AC Operating Requirements for ACT
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 11)
5.0
Units
ns
L
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
BUS to Clock
2.5
7.0
8.0
S
Hold Time, HIGH or LOW
Bus to Clock
5.0
5.0
0
2.5
7.0
2.5
8.0
ns
H
W
Clock Pulse Width
HIGH or LOW
4.5
ns
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
pF
Conditions
C
Input Capacitance
4.5
V
V
V
= OPEN
= 5.0V
= 5.0V
IN
CC
CC
CC
C
Input/Output Capacitance
Power Dissipation Capacitance
15.0
60.0
pF
I/O
PD
C
pF
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8
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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