74AC821SCX_NL [FAIRCHILD]
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| 型号： | 74AC821SCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 触发器 |
| 文件： | 总8页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised August 2000
74AC821 • 74ACT821
10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE
Features
■ 3-STATE outputs for bus interfacing
outputs arranged in a broadside pinout.
■ Noninverting outputs
■ Outputs source/sink 24 mA
■ TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC821SC
M24B
N24C
M24B
MTC24
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74AC821SPC
74ACT821SC
74ACT821MTC
74ACT821SPC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Data Inputs
Data Outputs
D0–D9
O0–O9
OE
Output Enable Input
Clock Input
CP
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010139
www.fairchildsemi.com
Functional Description
The AC/ACT821 consists of ten D-type edge-triggered flip-
flops. The buffered Clock (CP) and buffered Output Enable
(OE) are common to all flip-flops. The flip-flops will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH CP transition.
With OE LOW the contents of the flip-flops are available at
the outputs. When OE is HIGH the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip-flops.
Function Table
Inputs
Internal
Outputs
Function
OE
H
CP
D
L
Q
L
O
Z
Z
L
High Z
High Z
Load
H
H
L
H
L
L
L
H
H
H
Load
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
− 0.5V to + 7.0V
DC Input Diode Current (IIK
VI = − 0.5V
)
Supply Voltage (VCC
)
− 20 mA
+ 20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
− 0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
− 20 mA
+ 20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
− 40°C to + 85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
− 0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
− 65°C to + 150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = − 50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = − 12 mA
V
V
OH = − 24 mA
OH = − 24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4)
IOZ
Maximum Input Leakage Current
Maximum 3-STATE Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
5.5
±0.5
±5.0
V
V
V
V
O = VCC, GND
IOLD
IOHD
Minimum Dynamic
5.5
5.5
5.5
75
mA
mA
µA
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
80.0
ICC (Note 4) Maximum Quiescent Supply Current
8.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = − 50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = − 24 mA
OH = − 24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum 3-STATE
Current
5.5
5.5
5.5
±0.1
±0.5
±1.0
±5.0
1.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
(Note 4)
IOZ
VO = VCC, GND
ICCT
Maximum
0.6
mA
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
8.0
80.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
Typ
145
160
8.0
6.0
8.0
5.5
6.0
4.5
6.5
5.0
6.5
5.0
6.0
4.5
Max
Min
fMAX
Maximum Clock
110
120
3.0
2.0
3.0
2.0
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.5
100
110
3.0
2.0
3.0
2.0
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.5
MHz
ns
Frequency
5.0
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
CP to On
3.3
13.0
9.5
15.0
10.5
15.0
10.5
12.0
9.0
5.0
Propagation Delay
CP to On
3.3
13.0
9.5
ns
5.0
Output Enable Time
OE to On
3.3
11.0
8.0
ns
5.0
Output Enable Time
OE to On
3.3
11.0
8.0
12.0
9.0
ns
5.0
Output Disable Time
OE to On
3.3
10.5
8.0
11.0
8.5
ns
5.0
Output Disable Time
OE to On
3.3
10.5
8.0
11.0
8.5
ns
5.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements for AC
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
C
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
−1.0
−1.0
−1.0
−1.0
3.5
1.5
1.5
3.5
3.5
5.0
4.0
1.5
1.5
4.0
4.0
5.5
4.0
ns
ns
ns
5.0
tH
Hold Time, HIGH or LOW
3.3
Dn to CP
5.0
tW
CP Pulse Width
HIGH or LOW
3.3
5.0
2.5
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min
fMAX
Maximum Clock
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
150
110
1.5
2.0
2.0
2.0
1.0
1.0
MHz
ns
Frequency
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
CP to On
2.0
2.5
2.5
2.5
1.5
1.5
6.0
6.0
7.0
7.0
7.5
7.0
9.5
9.5
10.5
10.5
11.5
12.0
13.0
11.5
Propagation Delay
CP to On
ns
Output Enable Time
OE to On
10.5
10.5
12.0
10.5
ns
Output Enable Time
OE to On
ns
Output Disable Time
OE to On
ns
Output Disable Time
OE to On
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
2.5
2.0
2.0
4.5
2.5
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
−0.5
2.5
5.5
tW
CP Pulse Width
HIGH or LOW
3.0
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
CIN
Input Capacitance
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
35.0
pF
5
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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