74ACQ573SMTCX [FAIRCHILD]
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153, TSSOP-20;
| 型号： | 74ACQ573SMTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153, TSSOP-20 锁存器 |
| 文件： | 总12页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1990
Revised October 2000
74ACQ573 • 74ACTQ573
Quiet Series Octal Latch with 3-STATE Outputs
General Description
Features
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Series technology to guarantee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■ Outputs source/sink 24 mA
Ordering Code:
Order Number Package Number
Package Description
74ACQ573SC
74ACQ573SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC
74ACQ573PC
74ACTQ573SC
74ACTQ573SJ
74ACTQ573QSC
74ACTQ573MTC
74ACTQ573PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MQA20
MTC20
N20A
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE
3-STATE Output Enable Input
3-STATE Latch Outputs
O0–O7
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation
DS010633
www.fairchildsemi.com
Functional Description
Truth Table
The ACQ/ACTQ573 contains eight D-type latches with 3-
STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
Inputs
Outputs
On
OE
L
LE
H
H
L
D
H
L
dition the latches are transparent, i.e., a latch output will
change state each time its D-type input changes. When LE
is LOW the latches store the information that was present
on the D-type inputs at setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the buff-
ers are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
H
L
L
L
X
X
O0
Z
H
X
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
DC Latchup Source
or Sink Current
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
±300 mA
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics for ACQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
75
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
mA
mA
µA
VI = VCC, GND
IOLD
IOHD
Minimum Dynamic
V
V
V
OLD = 1.65 VMax
OHD = 3.85 VMin
IN = VCC or GND
Output Current (Note 3)
−75
ICC (Note 4) Maximum Quiescent Supply Current
4.0
40.0
IOZ
Maximum 3-STATE
Leakage Current
VI (OE) = VIL, VIH
VI = VCC, GND
5.5
5.0
±0.25
±2.5
µA
V
O = VCC, GND
VOLP
Quiet Output
Figures 1, 2
1.1
1.5
V
Maximum Dynamic VOL
(Note 5)(Note 6)
3
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DC Electrical Characteristics for ACQ (Continued)
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
Symbol
VOLV
Parameter
Quiet Output
Units
Conditions
Figures 1, 2
Typ
Guaranteed Limits
5.0
5.0
5.0
−0.6
−1.2
3.5
V
V
V
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
(Note 5)(Note 6)
VIHD
3.1
1.9
(Note 5)(Note 7)
VILD
1.5
(Note 5)(Note 7)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 8)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 8)
IIN
Maximum Input
5.5
5.5
±0.1
±1.0
±2.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
Leakage Current
IOZ
Maximum 3-STATE
Leakage Current
±0.25
V
O = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
µA
VI = VCC − 2.1V
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 9)
Maximum Quiescent Supply Current
Quiet Output
−75
40.0
4.0
1.5
VOLP
Figures 1, 2
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
V
V
V
V
Maximum Dynamic VOL
Quiet Output
(Note 10)(Note 11)
Figures 1, 2
VOLV
VIHD
VILD
−1.2
2.2
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
1.2
0.8
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: Plastic DIP package.
Note 11: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
Note 12: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f =1 MHz.
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4
AC Electrical Characteristics for ACQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 13)
3.3
Units
Min
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
Typ
8.5
5.5
8.5
6.0
8.5
6.0
9.0
6.0
1.0
0.5
Max
10.5
7.0
Min
tPHL
Propagation Delay
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
11.0
7.5
ns
ns
ns
ns
ns
tPLH
tPLH
tPHL
tPZL
Dn to On
5.0
Propagation Delay
LE to On
3.3
12.0
8.0
12.5
8.5
5.0
Output Enable Time
3.3
13.0
8.5
13.5
9.0
tPZH
tPHZ
tPLZ
5.0
Output Disable Time
3.3
14.5
9.5
15.0
10.0
1.5
5.0
tOSHL
tOSLH
Output to Output Skew (Note 14)
Dn to On
3.3
1.5
5.0
1.0
1.0
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACQ
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
C
C
Symbol
Parameter
(V)
(Note 15)
3.3
Units
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to LE
0
0
3.0
3.0
3.0
1.5
1.5
4.0
4.0
ns
ns
ns
5.0
3.0
1.5
1.5
4.0
4.0
tH
Hold Time, HIGH or LOW
Dn to LE
3.3
0
5.0
0
tW
LE Pulse Width, HIGH
3.3
2.0
2.0
5.0
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
Max
C
C
Symbol
Parameter
(V)
Units
(Note 16)
Min
Typ
Max
Min
tPHL
Propagation Delay
5.0
5.0
2.0
6.5
7.5
2.0
2.5
8.0
9.0
ns
ns
tPLH
Dnto On
tPLH
Propagation Delay
LE to On
2.5
7.0
8.5
tPHL
tPZL, tPZH
tPHZ, tPLZ
tOSHL
tOSLH
Output Enable Time
Output Disable Time
Output to Output Skew (Note 17)
Dn to On
5.0
5.0
2.0
1.0
7.0
8.0
9.0
2.0
1.0
9.5
ns
ns
10.0
10.5
5.0
0.5
1.0
1.0
ns
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5
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AC Operating Requirements for ACTQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 18)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to LE
5.0
0
3.0
3.0
ns
tH
Hold Time, HIGH or LOW
5.0
5.0
0
1.5
4.0
1.5
4.0
ns
ns
Dn to LE
tW
LE Pulse Width, HIGH
2.0
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
42.0
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are the cor-
rect voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 19: VOHV and VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics:
f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
7
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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12
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