74ACT00SCTR [FAIRCHILD]
NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14;
| 型号： | 74ACT00SCTR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14 栅 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised February 2005
74AC00 • 74ACT00
Quad 2-Input NAND Gate
General Description
The AC/ACT00 contains four 2-input NAND gates.
Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT00 has TTL-compatible inputs
Ordering Code:
Package
Order Number
Package Description
Number
74AC00SC
M14A
M14A
M14D
MTC14
N14A
N14A
M14A
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74AC00SCX_NL
74AC00SJ
74AC00MTC
74AC00PC
74AC00PC_NL
74ACT00SC
74ACT00SCX_NL
74ACT00SJ
74ACT00MTC
74ACT00PC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. PC not available in Tape and Reel.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009911
www.fairchildsemi.com
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC 0.5V
ACT
DC Input Voltage (VI)
0.5V to VCC 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
VO 0.5V
)
0V to VCC
20 mA
20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ( V/ t)
AC Devices
40 C to 85 C
VO VCC 0.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate ( V/ t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
65 C to 150 C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140 C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
V
0.1V
0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
CC
V
Maximum LOW Level
Input Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V
CC
V
Minimum HIGH Level
Output Voltage
OH
4.49
5.49
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
V
V
24 mA
24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
OL
IL
3.0
4.5
5.5
5.5
0.36
0.36
0.36
0.1
0.44
0.44
0.44
1.0
I
I
I
12 mA
24 mA
V
A
24 mA (Note 3)
V , GND
CC
I
Maximum Input
V
IN
I
(Note 4) Leakage Current
I
Minimum Dynamic
5.5
5.5
5.5
75
75
mA
mA
A
V
V
V
1.65V Max
3.85V Min
OLD
OLD
OHD
IN
I
Output Current (Note 5)
Maximum Quiescent Supply Current
OHD
I
2.0
20.0
V
or GND
CC
CC
(Note 4)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
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2
DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
0.1V
0.1V
0.1V
IH
OUT
V
V
V
or V
CC
V
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
V
Minimum HIGH Level
Output Voltage
4.49
5.49
OH
I
50
A
OUT
V
V
IL
or V
IN
OH
OH
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
I
I
24 mA
V
V
24 mA (Note 6)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
5.5
0.36
0.36
0.1
0.44
0.44
1.0
V
A
I
I
24 mA
24 mA (Note 6)
I
Maximum Input
Leakage Current
V
V
, GND
IN
I
CC
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
A
V
V
V
V
V
2.1V
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
1.65V Max
3.85V Min
OLD
OHD
IN
75
2.0
20.0
V
CC
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 8)
3.3
Units
L
Min
2.0
1.5
1.5
1.5
Typ
Max
9.5
8.0
8.0
6.5
t
Propagation Delay
7.0
6.0
5.5
4.5
2.0
1.5
1.0
1.0
10.0
8.5
PLH
ns
ns
5.0
t
Propagation Delay
3.3
8.5
PHL
5.0
7.0
Note 8: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics for ACT
V
T
25 C
50 pF
Typ
T
A
40 C to 85 C
50 pF
Max
CC
A
C
C
L
Symbol
Parameter
(V)
(Note 9)
5.0
Units
L
Min
1.5
1.5
Max
9.0
Min
1.0
1.0
t
t
Propagation Delay
Propagation Delay
5.5
4.0
9.5
8.0
ns
ns
PLH
PHL
5.0
7.0
Note 9: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
C
Input Capacitance
4.5
pF
pF
V
V
Open
5.0V
IN
CC
Power Dissipation Capacitance
30.0
PD
CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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