74ACT16374 [FAIRCHILD]
16-Bit D-Type Flip-Flop with 3-STATE Outputs; 16位D型触发器带3态输出
| 型号： | 74ACT16374 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
Revised October 1999
74ACT16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The ACT16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
■ Buffered Positive edge-triggered clock
■ Separate control logic for each byte
■ 16-bit version of the ACT374
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number
74ACT16374SSC
74ACT16374MTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
Inputs
I0–I15
O0–O15
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500298
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Functional Description
Truth Tables
The ACT16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
L
L
H
L
H
L
(Previous)
Z
L
L
X
X
X
H
transition. With the Output Enable (OEn) LOW, the con-
Inputs
OE2
Outputs
O8–O15
tents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
CP2
I8–I15
Operation of the OEn input does not affect the state of the
flip-flops.
L
L
H
L
H
L
(Previous)
Z
L
L
X
X
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X= Immaterial
Z = HIGH Impedance
= LOW-to-HIGH Transition
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
V
V
O = −0.5V
−20 mA
+20 mA
O = VCC + 0.5V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
±50 mA
V
CC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
± 50 mA
Storage Temperature
−65°C to +150°C
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
V
V
Minimum HIGH
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
IH
OUT
V
V
V
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
V
= 0.1V
IL
OUT
or V − 0.1V
CC
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IN
OH
OH
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
= −24 mA
= −24 mA (Note 2)
V
Maximum LOW
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
I
= 24 mA
= 24 mA (Note 2)
I
I
Maximum 3-STATE
Leakage Current
Maximum Input
V = V , V
OZ
I
IL
IH
5.5
± 0.5
± 0.1
± 5.0
µA
V
= V , GND
CC
O
IN
5.5
5.5
5.5
± 1.0
1.5
µA
mA
µA
V = V , GND
I CC
Leakage Current
I
I
Maximum I /Input
CC
0.6
V = V − 2.1V
CCT
CC
I
CC
Maximum Quiescent
Supply Current
8.0
80.0
V
= V or GND
CC
IN
I
I
Minimum Dynamic
Output Current (Note 3)
75
mA
mA
V
V
= 1.65V Max
= 3.85V Min
OLD
OHD
OLD
5.5
−75
OHD
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
3
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AC Electrical Characteristics
V
T
= +25°C
= 50 pF
Typ
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
(Note 4)
5.0
Units
L
Min
71
Max
Min
Max
f
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
67
3.1
3.0
2.5
2.0
2.1
2.0
MHz
ns
MAX
3.1
3.0
2.5
3.0
2.1
2.0
5.3
5.1
4.7
5.4
5.1
4.8
7.9
7.3
7.4
8.0
7.9
7.4
8.4
7.8
7.9
8.5
8.2
7.9
PLH
PHL
PZH
PZL
PHZ
PLZ
5.0
5.0
5.0
CP to O
n
Output Enable Time
Output Disable Time
ns
ns
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 5)
Typ
Guaranteed Limits
t
Setup Time, HIGH or
S
5.0
0.7
3.0
1.0
5.0
3.0
ns
ns
ns
LOW, Input to Clock
Hold Time, HIGH or
LOW, Input to Clock
CP Pulse Width,
t
t
H
W
5.0
5.0
0.8
1.5
1.0
5.0
HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
4.5
30
Units
pF
Conditions
C
C
Input Capacitance
V
V
= 5.0V
= 5.0V
IN
CC
CC
Power Dissipation Capacitance
pF
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
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6
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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