74ACT175 [FAIRCHILD]
Quad D-Type Flip-Flop; 四D型触发器
| 型号： | 74ACT175 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad D-Type Flip-Flop |
| 文件： | 总9页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC175 • 74ACT175
Quad D-Type Flip-Flop
General Description
Features
The AC/ACT175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran-
sition. Both true and complemented outputs of each flip-
flop are provided. A Master Reset input resets all flip-flops,
independent of the Clock or D-type inputs, when LOW.
■ ICC reduced by 50%
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output
■ Outputs source/sink 24 mA
■ ACT175 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC175SC
74AC175SJ
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC
74AC175PC
74ACT175SC
74ACT175SJ
74ACT175MTC
74ACT175PC
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M16A
M16D
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D3
CP
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
MR
Q0–Q3
Q0–Q3
Complement Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009936
www.fairchildsemi.com
Functional Description
Truth Table
The AC/ACT175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the state of their individual D inputs on the LOW-
to-HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH indepen-
dent of Clock or Data inputs. The AC/ACT175 is useful for
general logic applications where a common Master Reset
and Clock are acceptable.
Inputs
Outputs
@ tn+1
@ tn, MR = H
Dn
Qn
Qn
L
L
H
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
VOUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN
(Note 4)
Maximum Input
Leakage Current
5.5
±0.1
± 1.0
µA
VI = VCC, GND
IOLD
IOHD
Minimum Dynamic
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
Output Current (Note 3)
−75
VOHD = 3.85V Min
ICC
(Note 4)
Maximum Quiescent
Supply Current
5.5
4.0
40.0
µA
VIN = VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
www.fairchildsemi.com
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
1.5
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
± 1.0
1.5
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input Leakage Current
Maximum ICC/Input
µA
mA
mA
mA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
IOLD
IOHD
ICC
0.6
Minimum Dynamic
75
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
or GND
Output Current(Note 6)
Maximum Quiescent
Supply Current
−75
V
5.5
4.0
40.0
µA
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
fMAX
Parameter
(V)
(Note 7)
3.3
Units
Min
149
187
2.0
Typ
214
244
9.5
Max
Min
Maximum Clock
Frequency
139
187
2.0
MHz
ns
5.0
tPLH
Propagation Delay
3.3
12.0
9.0
13.5
9.5
5.0
1.5
7.0
1.0
CP to Qn or Qn
tPHL
tPLH
tPHL
Propagation Delay
3.3
5.0
2.5
1.5
8.5
6.0
13.0
9.5
2.0
1.5
14.5
10.5
ns
ns
ns
CP to Qn or Qn
Propagation Delay
3.3
5.0
3.0
2.0
7.5
5.5
12.5
9.0
2.5
1.5
13.5
10.0
MR to Qn
Propagation Delay
3.3
5.0
3.0
2.0
8.5
6.0
11.0
8.5
2.5
1.5
12.5
9.0
MR to Qn
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
www.fairchildsemi.com
4
AC Operating Requirements for AC
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
C
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
2.0
1.0
1.0
1.0
2.5
2.0
4.5
4.5
3.0
1.0
1.0
4.5
3.5
ns
ns
ns
5.0
3.0
1.0
1.0
4.5
3.5
tH
Hold Time, HIGH or LOW
3.3
Dn to CP
5.0
tW
CP Pulse Width
HIGH or LOW
3.3
5.0
tW
3.3
2.5
4.5
5.0
MR Pulse Width, LOW
ns
ns
5.0
3.3
5.0
2.0
3.5
0
3.5
0
tREC
Recovery Time
MR to CP
−2.0
−1.0
0
0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min
fMAX
Maximum Clock
5.0
5.0
5.0
175
236
6.0
7.0
145
1.5
1.5
MHz
ns
Frequency
tPLH
tPHL
tPLH
Propagation Delay
CP to Qn or Qn
Propagation Delay
CP to Qn or Qn
Propagation Delay
2.0
2.0
10.0
11.0
11.0
12.0
ns
5.0
5.0
2.0
2.0
6.0
5.5
9.5
9.5
1.5
1.5
10.5
10.5
ns
ns
MR to Qn
tPHL
Propagation Delay
MR to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 10)
5.0
Units
Typ
3.0
3.0
Guaranteed Minimum
tS (H)
Setup Time
Dn to CP
2.0
2.0
2.5
ns
ns
ns
tS (L)
tH
2.5
Hold Time, HIGH or LOW
Dn to CP
5.0
5.0
0
1.0
1.0
3.5
tW
CP Pulse Width
HIGH or LOW
4.0
3.0
tW
5.0
5.0
4.0
0
3.0
0
4.0
0
ns
ns
MR Pulse Width, LOW
trec
Recovery Time, MR to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
45.0
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M16A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9
www.fairchildsemi.com
相关型号：
74ACT175DC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CDIP16, CERAMIC, DIP-16
ROCHESTER
74ACT175FCXR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CDFP16, CERAMIC, FP-16
FAIRCHILD
74ACT175LC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT175PC
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, 0.300 INCH, PLASTIC, DIP-16
TI
74ACT175PCQR
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16
TI
74ACT175SC
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16
TI
74ACT175SCQR
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOIC-16
TI
©2020 ICPDF网 联系我们和版权申明