74ACT240SCTR [FAIRCHILD]
Bus Driver, ACT Series, 2-Func, 4-Bit, Inverted Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20;
| 型号： | 74ACT240SCTR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 2-Func, 4-Bit, Inverted Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC240, 74ACT240
Octal Buffer/Line Driver with 3-STATE Outputs
Features
General Description
■ I and I reduced by 50%
The AC/ACT240 is an octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver
which provides improved PC board density.
CC
OZ
■ Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
■ Outputs source/sink 24mA
■ ACT240 has TTL-compatible inputs
Ordering Information
Package
Order Number
74AC240SC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC240SJ
M20D
74AC240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC240PC
N20A
M20B
M20D
MTC20
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT240SC
74ACT240SJ
74ACT240MTC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT240PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
Connection Diagram
Logic Symbol
IEEE/IEC
EN
1
20
19
18
17
16
15
14
13
12
11
OE1
2
VCC
OE2
O0
I4
O1
I5
O2
I6
O3
I7
OE1
I0
3
O4
4
I1
I0
I1
I2
I3
O0
O1
O2
O3
5
O5
6
I2
7
O6
8
I3
9
O7
10
GND
OE2
EN
I4
I5
I6
I7
O4
O5
O6
O7
Pin Description
Pin Names
Description
Truth Tables
OE , OE
3-STATE Output Enable Inputs
1
2
I –I
Inputs
Inputs
0
7
Outputs
(Pins 12, 14, 16, 18)
O –O
Outputs
0
7
OE
L
I
1
n
L
H
L
L
H
X
H
Z
Inputs
Outputs
OE
L
I
(Pins 3, 5, 7, 9)
2
n
L
H
L
L
H
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
−0.5V to +7.0V
V
I
Supply Voltage
CC
IK
DC Input Diode Current
V = −0.5V
−20mA
+20mA
I
V = V + 0.5
I
CC
V
DC Input Voltage
−0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= −0.5V
−20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
−0.5V to V + 0.5V
O
CC
I
±50mA
±50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
−65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
AC
CC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
−40°C to +85°C
A
∆V / ∆t
Minimum Input Edge Rate, AC Devices:
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
125mV/ns
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
3
DC Electrical Characteristics for AC
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
= 0.1V or
OUT
Typ.
Guaranteed Limits
Units
CC
3.0
V
Minimum HIGH Level
Input Voltage
V
V
1.5
2.1
2.1
V
IH
– 0.1V
CC
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
– 0.1V
V
V
IL
OUT
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
V
= V or V ,
0.36
0.36
0.44
0.44
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(2)
I
Maximum Input
Leakage Current
5.5
5.5
V = V , GND
0.1
1.0
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
V (OE) = V , V ;
±0.25
±2.5
OZ
I
IL IH
V = V , GND;
I
CC
V
= V , GND
O
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
-75
mA
mA
µA
OLD
OLD
OHD
(3)
I
OHD
(2)
I
Maximum Quiescent
Supply Current
= V or GND
4.0
40.0
CC
IN
CC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3. Maximum test duration 2.0ms, one output loaded at a time.
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
4
DC Electrical Characteristics for ACT
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
= 0.1V or
OUT
Typ.
Guaranteed Limits
Units
CC
4.5
V
Minimum HIGH Level
Input Voltage
V
V
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
− 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
V
Maximum LOW
Level Input Voltage
V
V
= 0.1V or
− 0.1V
1.5
V
V
IL
OUT
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= −50µA
4.49
5.49
OH
OUT
V
= V or V ,
3.86
3.76
IN
IL
IH
I
= −24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= −24mA
OH
V
Maximum LOW
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
Level Output Voltage
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 24mA
OL
5.5
V
= V or V ,
0.36
0.44
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
5.5
5.5
V = V , GND
±0.1
±1.0
±2.5
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
V = V , V ;
±0.25
OZ
I
IL IH
V
= V , GND
O
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V − 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
−75
40.0
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
5
AC Electrical Characteristics for AC
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(6)
Symbol
Parameter
V
(V)
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ.
6.0
4.5
5.5
4.5
6.0
5.0
7.0
5.5
7.0
6.5
7.5
6.5
Max.
8.0
Min.
Max.
9.0
Units
CC
3.3
t
Propagation Delay
Data to Output
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
PLH
PHL
PZH
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
6.5
7.0
t
Propagation Delay
Data to Output
8.0
8.5
ns
ns
ns
ns
ns
6.0
6.5
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
10.5
7.0
11.0
8.0
t
10.0
8.0
11.0
8.5
PZL
t
10.0
9.0
10.5
9.5
PHZ
t
10.5
9.0
11.5
9.5
PLZ
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(7)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
5.0
t
Propagation Delay,
Data to Output
1.5
6.0
8.5
1.5
9.5
ns
PLH
PHL
PZH
t
Propagation Delay,
Data to Output
5.0
1.5
5.5
7.5
1.5
8.5
ns
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.5
2.0
2.0
2.5
7.0
7.0
8.0
6.5
8.5
9.5
1.0
1.5
2.0
2.0
9.5
ns
ns
ns
ns
t
10.5
10.5
10.5
PZL
PHZ
t
9.5
t
10.0
PLZ
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
= OPEN
Typ.
4.5
Units
C
V
V
pF
pF
IN
CC
C
= 5.0V
45.0
PD
CC
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
6
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.65
0.51
0.35
1.27
PIN ONE
INDICATOR
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
7
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
9
Physical Dimensions (Continued)
26.92
24.89
PIN #1
7.11
6.09
3.43
3.17
5.33 MAX
(0.97)
1.78
7.87
7.62
7° TYP
1.14
7° TYP
3.55
2.54
0.36
3.17
0.38 MIN
10.92 MAX
0.56
0.20
0.35
.001[.025]
C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
10
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SyncFET™
®
FPS™
Power220®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
UniFET™
VCX™
FAST®
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©2006 Fairchild Semiconductor Corporation
74AC240, 74ACT240 Rev. 1.2.0
www.fairchildsemi.com
11
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