74ACT244SCX [FAIRCHILD]

Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器
74ACT244SCX
型号: 74ACT244SCX
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Octal Buffer/Line Driver with 3-STATE Outputs
八路缓冲器/ 3态输出线路驱动器

驱动器
文件: 总10页 (文件大小:113K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
November 1988  
Revised March 2005  
74AC244 74ACT244  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The AC/ACT244 is an octal buffer and line driver designed  
to be employed as a memory address driver, clock driver  
and bus-oriented transmitter/receiver which provides  
improved PC board density.  
ICC and IOZ reduced by 50%  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Outputs source/sink 24 mA  
ACT244 has TTL-compatible inputs  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC244SC  
M20B  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
74AC244SCX_NL  
(Note 1)  
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
74AC244SJ  
M20D  
MTC20  
MTC20  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC244MTC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74AC244MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74AC244PC  
N20A  
M20B  
M20B  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
74ACT244SC  
74ACT244SCX_NL  
(Note 1)  
74ACT244SJ  
M20D  
MSA20  
MTC20  
MTC20  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74ACT244MSA  
74ACT244MTC  
74ACT244MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ACT244PC  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009943  
www.fairchildsemi.com  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
IEEE/IEC  
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
O0O7  
Outputs  
Truth Tables  
Inputs  
OE1  
Outputs  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
L
H
Z
H
Connection Diagram  
Inputs  
OE2  
Outputs  
In  
(Pins 3, 5, 7, 9)  
L
L
L
H
X
L
H
Z
H
X
Z
Immaterial  
High Impedance  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
DC Input Diode Current (IIK  
VI 0.5V  
)
0.5V to 7.0V  
)
Supply Voltage (VCC  
)
20 mA  
20 mA  
AC  
2.0V to 6.0V  
4.5V to 5.5V  
0V to VCC  
VI VCC 0.5V  
ACT  
DC Input Voltage (VI)  
0.5V to VCC 0.5V  
Input Voltage (VI)  
Output Voltage (VO)  
DC Output Diode Current (IOK  
VO 0.5V  
)
0V to VCC  
20 mA  
20 mA  
Operating Temperature (TA)  
Minimum Input Edge Rate ( V/ t)  
AC Devices  
40 C to 85 C  
VO VCC 0.5V  
DC Output Voltage (VO)  
DC Output Source  
0.5V to VCC 0.5V  
V
IN from 30% to 70% of VCC  
or Sink Current (IO)  
50 mA  
VCC @ 3.3V, 4.5V, 5.5V  
Minimum Input Edge Rate ( V/ t)  
ACT Devices  
125 mV/ns  
125 mV/ns  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
50 mA  
Storage Temperature (TSTG  
Junction Temperature (TJ)  
PDIP  
)
65 C to 150 C  
VIN from 0.8V to 2.0V  
VCC @ 4.5V, 5.5V  
140 C  
Note 2: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception, to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
DC Electrical Characteristics for AC  
V
T
25 C  
T
55 C to 125 C  
T
A
40 C to 85 C  
CC  
A
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
Minimum HIGH Level  
Input Voltage  
2.1  
2.1  
3.15  
3.85  
0.9  
2.1  
3.15  
3.85  
0.9  
V
0.1V  
0.1V  
IH  
OUT  
2.25  
2.75  
1.5  
3.15  
3.85  
0.9  
V
or V  
CC  
V
Maximum LOW Level  
Input Voltage  
V
0.1V  
0.1V  
IL  
OUT  
2.25  
2.75  
2.99  
4.49  
5.49  
1.35  
1.65  
2.9  
1.35  
1.65  
2.9  
1.35  
1.65  
2.9  
V
V
V
V
or V  
CC  
V
Minimum HIGH Level  
Output Voltage  
OH  
4.4  
4.4  
4.4  
I
50 A  
OUT  
5.4  
5.4  
5.4  
2.56  
3.86  
4.86  
0.1  
2.4  
2.46  
3.76  
4.76  
0.1  
I
I
I
12 mA  
24 mA  
OH  
OH  
OH  
3.7  
4.7  
24 mA (Note 3)  
V
Maximum LOW Level  
Output Voltage  
0.002  
0.001  
0.001  
0.1  
OL  
0.1  
0.1  
0.1  
I
50 A  
OUT  
0.1  
0.1  
0.1  
0.36  
0.36  
0.36  
0.1  
0.50  
0.50  
0.50  
1.0  
0.44  
0.44  
0.44  
1.0  
I
I
I
12 mA  
OL  
OL  
OL  
V
A
24 mA  
24 mA (Note 3)  
I
Maximum Input  
V
V
, GND  
IN  
I
CC  
(Note 5) Leakage Current  
I
Maximum  
V (OE)  
V
, V  
OZ  
I
IL IH  
3-STATE  
5.5  
0.25  
5.0  
2.5  
A
V
V
V
V
V
V
, V  
GND  
I
CC  
Current  
V
, GND  
O
CC  
I
Minimum Dynamic  
Output Current (Note 4)  
Maximum Quiescent  
5.5  
5.5  
5.5  
50  
50  
75  
75  
mA  
mA  
A
1.65V Max  
3.85V Min  
OLD  
OLD  
I
OHD  
OHD  
IN  
I
4.0  
80.0  
40.0  
V
CC  
CC  
(Note 5) Supply Current  
or GND  
Note 3: All outputs loaded; thresholds on input associated with output under test.  
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.  
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .  
CC  
IN  
CC  
3
www.fairchildsemi.com  
DC Electrical Characteristics for ACT  
V
T
25 C  
T
55 C to 125 C  
T
A
40 C to 85 C  
CC  
A
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
Minimum HIGH Level  
Input Voltage  
2.0  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
0.1V  
0.1V  
0.1V  
0.1V  
50  
IH  
OUT  
V
V
V
1.5  
2.0  
0.8  
0.8  
4.4  
5.4  
or V  
CC  
V
Maximum LOW Level  
Input Voltage  
1.5  
V
IL  
OUT  
1.5  
or V  
CC  
V
Minimum HIGH Level  
Output Voltage  
4.49  
5.49  
I
A
OH  
OUT  
I
I
I
I
12  
OH  
OH  
OH  
OUT  
4.5  
5.5  
4.5  
5.5  
3.86  
4.86  
0.1  
3.70  
4.70  
0.1  
3.76  
4.76  
0.1  
V
V
24 mA  
24 mA (Note 6)  
50  
V
Maximum LOW Level  
Output Voltage  
0.001  
0.001  
A
OL  
0.1  
0.1  
0.1  
I
I
I
12 mA  
OL  
OL  
OL  
4.5  
5.5  
5.5  
0.36  
0.36  
0.1  
0.50  
0.50  
1.0  
0.44  
0.44  
1.0  
V
A
24 mA  
24 mA (Note 6)  
I
I
I
Maximum Input  
Leakage Current  
Maximum 3-STATE  
Current  
V
V
, GND  
IN  
I
CC  
5.5  
5.5  
0.25  
5.0  
1.6  
2.5  
1.5  
A
V
V
V
V
, V  
OZ  
I
IL  
IH  
V
, GND  
O
I
CC  
Maximum  
0.6  
mA  
V
2.1V  
CCT  
CC  
I
/Input  
CC  
I
I
I
Minimum Dynamic  
Output Current (Note 7)  
Maximum Quiescent  
Supply Current  
5.5  
5.5  
5.5  
50  
50  
75  
75  
mA  
mA  
A
V
V
V
1.65V Max  
3.85V Min  
OLD  
OHD  
CC  
OLD  
OHD  
IN  
4.0  
80.0  
40.0  
V
CC  
or GND  
Note 6: All outputs loaded; thresholds on input associated with output under test.  
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.  
www.fairchildsemi.com  
4
AC Electrical Characteristics for AC  
V
T
25 C  
T
55 C to 125 C  
50 pF  
Max  
T
A
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
Symbol  
Parameter  
C
50 pF  
C
C
L
Units  
(V)  
(Note 8)  
3.3  
L
L
Min  
2.0  
1.5  
2.0  
1.5  
2.0  
1.5  
2.5  
1.5  
3.0  
2.5  
2.5  
2.0  
Typ  
Max  
9.0  
Min  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
t
t
t
t
t
t
Propagation Delay  
Data to Output  
6.5  
5.0  
6.5  
5.0  
6.0  
5.0  
7.5  
5.5  
7.0  
6.5  
7.5  
6.5  
12.5  
9.5  
1.5  
1.0  
2.0  
1.0  
1.5  
1.5  
2.0  
1.5  
1.5  
1.0  
2.5  
2.0  
10.0  
7.5  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
ns  
ns  
ns  
ns  
ns  
ns  
5.0  
7.0  
Propagation Delay  
Data to Output  
3.3  
9.0  
12.0  
9.0  
10.0  
7.5  
5.0  
7.0  
Output Enable Time  
3.3  
10.5  
7.0  
11.5  
9.0  
11.0  
8.0  
5.0  
Output Enable Time  
Output Disable Time  
Output Disable Time  
3.3  
10.0  
8.0  
13.0  
10.5  
12.5  
10.5  
13.0  
11.0  
11.0  
8.5  
5.0  
3.3  
10.0  
9.0  
10.5  
9.5  
5.0  
3.3  
10.5  
9.0  
11.5  
9.5  
5.0  
Note 8: Voltage Range 3.3 is 3.3V 0.3V  
Voltage Range 5.0 is 5.0V 0.5V  
AC Electrical Characteristics for ACT  
V
T
25 C  
T
55 C to 125 C  
50 pF  
Max  
T
A
40 C to 85 C  
CC  
A
A
Symbol  
Parameter  
C
50 pF  
C
C
L
50 pF  
Max  
Units  
(V)  
(Note 9)  
5.0  
L
L
Min  
Typ  
Max  
Min  
Min  
t
Propagation Delay  
2.0  
6.5  
9.0  
1.0  
10.0  
1.5  
10.0  
ns  
ns  
PLH  
Data to Output  
t
Propagation Delay  
Data to Output  
5.0  
2.0  
7.0  
9.0  
1.0  
10.0  
1.5  
10.0  
PHL  
t
Output Enable Time  
Output Enable Time  
Output Disable Time  
Output Disable Time  
5.0  
5.0  
5.0  
5.0  
1.5  
2.0  
2.0  
2.5  
6.0  
7.0  
7.0  
7.5  
8.5  
9.5  
1.0  
1.0  
1.0  
1.0  
9.5  
1.0  
1.5  
1.5  
2.0  
9.5  
ns  
ns  
ns  
ns  
PZH  
t
11.0  
11.0  
11.5  
10.5  
10.5  
10.5  
PZL  
t
9.5  
PHZ  
t
10.0  
PLZ  
Note 9: Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation Capacitance  
Typ  
Units  
pF  
Conditions  
C
C
4.5  
V
V
OPEN  
5.0V  
IN  
CC  
CC  
45.0  
pF  
PD  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
10  

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