74ACT377SJX [FAIRCHILD]
Octal D-Type Flip-Flop with Clock Enable; 八路D型触发器与时钟使能
| 型号： | 74ACT377SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with Clock Enable |
| 文件： | 总9页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised March 2005
74AC377 • 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
Features
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
■ ICC reduced by 50%
■ Ideal for addressable register applications
■ Clock enable for address and data synchronization
applications
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
■ Outputs source/sink 24 mA
■ See 273 for master reset version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
■ ACT377 has TTL-compatible inputs
Ordering Code:
Package
Order Number
Package Description
Number
74AC377SC
74AC377SJ
74AC377MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC20
MTC20
74AC377MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC377PC
N20A
M20B
M20D
MTC20
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
CE
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Q0–Q7
CP
Clock Pulse Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009961
www.fairchildsemi.com
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
CE
Outputs
Operating Mode
CP
Dn
Qn
Load ‘1'
L
L
H
L
H
L
Load ‘0'
Hold (Do Nothing)
H
H
X
X
No Change
No Change
X
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC 0.5V
ACT
DC Input Voltage (VI)
0.5V to VCC 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
VO 0.5V
)
0V to VCC
20 mA
20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ( V/ t)
AC Devices
40 C to 85 C
VO VCC 0.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate ( V/ t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
65 C to 150 C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140 C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
1.5
2.1
2.1
3.15
3.85
0.9
V
0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
0.1V
CC
Maximum LOW Level
Input Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V
CC
Minimum HIGH Level
Output Voltage
OH
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
24 mA
V
V
24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
OL
IL
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
12 mA
24 mA
V
A
24 mA (Note 3)
I
Maximum Input
V
V
,
IN
I
CC
5.5
0.1
1.0
(Note 5)
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
GND
I
I
I
5.5
5.5
75
75
mA
mA
V
V
1.65V Max
3.85V Min
OLD
OHD
CC
OLD
OHD
5.5
4.0
40.0
A
V
V
or GND
IN
CC
(Note 5)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3
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DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
CC
Maximum LOW Level
Input Voltage
V
IL
OUT
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
OH
I
50
A
OUT
V
V
IL
or V
IN
OH
OH
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
24 mA
24 mA (Note 6)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
0.36
0.36
0.44
0.44
I
I
24 mA
24 mA (Note 6)
I
I
Maximum Input
Leakage Current
Maximum
IN
5.5
5.5
0.1
1.0
1.5
A
V
V
V
, GND
2.1V
I
CC
CCT
0.6
mA
V
I
CC
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
5.5
5.5
75
75
mA
mA
V
V
V
1.65V Max
3.85V Min
OLD
OHD
CC
OLD
OHD
IN
V
CC
5.5
4.0
40.0
A
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
CC
T
25 C
Typ
T
40 C to 85 C
Min Max
Symbol
Parameter
(V)
(Note 8)
3.3
Units
A
A
Min
Max
f
t
t
Maximum Clock
90
140
3.0
2.0
3.5
2.5
125
175
8.0
6.0
8.5
6.5
75
125
1.5
1.5
2.0
1.5
MAX
MHz
ns
Frequency
5.0
Propagation Delay
3.3
13.0
9.0
14.0
10.0
14.5
11.0
PLH
PHL
CP to Q
5.0
n
Propagation Delay
CP to Q
3.3
13.0
10.0
ns
5.0
n
Note 8: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
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4
AC Operating Requirements for AC
V
T
25 C
T
A
40 C to 85 C
50 pF
CC
A
Symbol
Parameter
(V)
C
50 pF
C
Units
L
L
(Note 9)
3.3
Typ
3.5
2.5
Guaranteed Minimum
t
t
t
t
t
Setup Time, HIGH or LOW
5.5
4.0
0
6.0
4.5
0
S
ns
ns
ns
ns
ns
D
to CP
5.0
n
Hold Time, HIGH or LOW
to CP
3.3
2.0
1.0
4.0
2.5
3.5
2.0
3.5
2.5
H
S
D
5.0
1.0
6.0
4.0
0
1.0
7.5
4.5
0
n
Setup Time, HIGH or LOW
CE to CP
3.3
5.0
Hold Time, HIGH or LOW
CE to CP
3.3
H
W
5.0
1.0
5.5
4.0
1.0
6.0
4.5
CP Pulse Width
HIGH or LOW
3.3
5.0
Note 9: Voltage Range 3.3 is 3.0V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics for ACT
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
Symbol
Parameter
(V)
C
50 pF
C
Units
L
L
(Note 10)
Min
Typ
Max
f
t
Maximum Clock Frequency
Propagation Delay
5.0
140
175
125
MHz
ns
MAX
PLH
5.0
5.0
3.0
3.5
6.5
9.0
2.5
10.0
11.0
CP to Q
n
t
Propagation Delay
CP to Q
PHL
7.0
10.0
2.5
ns
n
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
V
T
25 C
50 pF
T
A
40 C to 85 C
50 pF
CC
A
Symbol
Parameter
(V)
C
C
Units
L
L
(Note 11)
Typ
Guaranteed Minimum
t
t
t
t
t
Setup Time, HIGH or LOW
S
5.0
5.0
5.0
5.0
5.0
2.5
4.5
1.0
4.5
1.0
4.0
5.5
ns
ns
ns
ns
ns
D
to CP
n
Hold Time, HIGH or LOW
to CP
H
S
1.0
2.5
1.0
2.0
1.0
5.5
1.0
4.5
D
n
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH or LOW
CE to CP
H
W
CP Pulse Width
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
C
C
Input Capacitance
V
V
OPEN
5.0V
IN
PD
CC
Power Dissipation Capacitance
90.0
pF
CC
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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