74ACT533 [FAIRCHILD]
Octal Transparent Latch with 3-STATE Outputs; 八路透明锁存器具有三态输出
| 型号： | 74ACT533 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transparent Latch with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
Revised October 1999
74ACT533
Octal Transparent Latch
with 3-STATE Outputs
General Description
Features
■ ICC and IOZ reduced by 50%
The ACT533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
■ Eight latches in a single package
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Inverted version of the ACT373
■ TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT533SC
74ACT533MTC
74ACT533PC
M20B
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE
Output Enable Input
3-STATE Latch Outputs
O0–O7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500311
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Functional Description
Truth Table
The ACT533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
Inputs
Outputs
On
LE
OE
Dn
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
X
H
H
L
H
L
L
L
X
L
Z
H
H
X
L
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
= Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
− 0.5V to + 7.0V
DC Input Diode Current (IIK
VI = − 0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
− 20 mA
+ 20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
−40°C to +85°C
DC Output Diode Current (IOK
)
V
V
O = − 0.5V
− 20 mA
+ 20 mA
O = VCC + 0.5V
V
CC @ 4.5V, 5.5V
125 mV/ns
DC Output Voltage (VO)
DC Output Source
− 0.5V to VCC + 0.5V
or Sink Current (IO)
± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
DC Latchup Source
or Sink Current
)
− 65°C to + 150°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
± 300 mA
140°C
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
Conditions
= 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT
IH
V
V
V
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
V
V
Maximum LOW Level
Input Voltage
V
= 0.1V
IL
OUT
or V − 0.1V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IL IH
IN
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
= −24 mA
OH
OH
= −24 mA (Note 2)
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
= 24 mA
OL
OL
= 24 mA (Note 2)
I
I
I
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
IN
5.5
5.5
5.5
±0.1
±1.0
±2.5
1.5
µA
µA
mA
V = V , GND
I CC
V = V , V
OZ
I
IL
IH
±0.25
V
= V , GND
CC
O
CCT
0.6
V = V − 2.1V
I
CC
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
= 1.65V Max
= 3.85V Min
OLD
OHD
CC
OLD
−75
OHD
= V
IN
CC
5.5
4.0
40.0
µA
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
V
T
= + 25°C
= 50 pF
Typ
T = − 40°C to + 85°C
A
CC
A
Symbol
Parameter
C
C
= 50 pF
Units
(V)
L
L
(Note 4)
Min
Max
Min
Max
t
Propagation Delay
D to O
n
PHL
5.0
5.0
2.0
6.0
7.0
8.0
2.0
2.5
8.5
9.5
ns
ns
t
t
PLH
n
t
Propagation Delay
LE to O
PHL
2.5
9.0
PLH
n
t
, t
Output Enable Time
Output Disable Time
5.0
5.0
2.0
1.0
7.0
8.0
9.0
2.0
1.0
9.5
ns
ns
PZL PZH
t
, t
10.0
10.5
PHZ PLZ
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
V
T
= + 25°C
= 50 pF
T = − 40°C to + 85°C
A
CC
A
Symbol
Parameter
C
C
= 50 pF
Units
(V)
L
L
(Note 5)
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
to LE
S
5.0
0
3.0
3.0
ns
D
n
Hold Time, HIGH or LOW
to LE
H
5.0
5.0
0
1.5
4.0
1.5
4.0
ns
ns
D
n
LE Pulse Width, HIGH
2.0
W
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
= OPEN
= 5.0V
IN
CC
C
Power Dissipation Capacitance
PD
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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