74ACT574 [FAIRCHILD]
Octal D-Type Flip-Flop with 3-STATE Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | 74ACT574 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1988
Revised November 1999
74AC574 • 74ACT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The AC/ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered com-
mon Output Enable (OE). The information presented to the
D-type inputs is stored in the flip-flops on the LOW-to-HIGH
Clock (CP) transition.
■ ICC and IOZ reduced by 50%
■ Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to AC/ACT374
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
The AC/ACT574 is functionally identical to the AC/ACT374
except for the pinouts.
■ ACT574 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC574SC
74AC574SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC574MTC
74AC574PC
74ACT574SC
74ACT574SJ
74ACT574MTC
74ACT574PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-01
M20B
M20D
MTC20
N20A
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009910
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Functional Description
Function Table
The AC/ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When OE
is HIGH, the outputs go to the high impedance state. Oper-
ation of the OE input does not affect the state of the flip-
flops.
Inputs
Internal Outputs
Function
OE CP
D
Q
ON
H
H
H
H
L
H
H
L
H
L
NC
NC
L
Z
Z
Hold
Hold
Load
Load
Z
H
L
H
Z
L
L
Data Available
L
H
L
H
H
Data Available
L
H
H
NC
NC
NC
NC
No Change in Data
No Change in Data
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC +0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC +0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC +0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
Per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = 25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
1.5
2.25
2.75
1.5
2.1
2.1
3.15
3.85
0.9
V
OUT = 0.1V
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
2.56
3.86
4.86
2.46
3.76
4.76
VIN = VIL or VIH
I
I
I
OH = −12 mA
OH = −24 mA IOH
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
I
OUT = 50 µA
VIN = VILor VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, VGND
IOZ
Maximum
3-STATE
5.5
±0.25
±2.5
Leakage Current
Minimum Dynamic
Output Current (Note 3)
V
V
V
V
O = VCC, GND
IOLD
IOHD
5.5
5.5
5.5
75
mA
mA
µA
OLD = 1.65V
−75
40.0
OHD = 3.85V
ICC (Note 4) Maximum Quiescent Supply Current
4.0
IN = VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = 25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
1.5
1.5
2.0
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
VIL
Maximum LOW Level
Input Voltage
1.5
0.8
0.8
4.4
5.4
V
1.5
VOH
Minimum HIGH Level
4.49
5.49
I
OUT = −50 µA
IN = VILor VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VILor VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
5.5
5.5
±0.1
±1.0
±2.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
IOZ
±0.25
V
O = VCC, GND
ICCT
I]OLD
IOHD
ICC
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
VI = VCC − 2.1V
V
V
V
OLD = 1.65V
OHD = 3.85V
IN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
Typ
112
153
8.5
6.0
7.5
5.5
7.0
5.0
6.5
5.0
7.5
6.0
5.5
4.5
Max
Min
fMAX
Maximum Clock
75
95
60
85
MHz
ns
Frequency
5.0
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
CP to On
3.3
3.5
2.0
3.5
2.0
2.5
2.0
3.0
2.0
3.5
2.0
2.0
1.0
13.5
9.5
3.5
2.0
3.5
2.0
2.5
2.0
3.0
1.5
2.5
1.5
1.5
1.0
15.0
11.0
13.5
9.5
5.0
Propagation Delay
CP to On
3.3
12.0
8.5
ns
5.0
Output Enable Time
3.3
11.0
8.5
12.0
9.0
ns
5.0
Output Enable Time
Output Disable Time
Output Disable Time
3.3
10.5
8.0
11.5
9.0
ns
5.0
3.3
12.0
9.5
13.0
10.5
10.0
8.5
ns
5.0
3.3
9.0
ns
5.0
7.5
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
0.5
0
tS
Set-Up Time, HIGH or LOW
Dn to CP
2.5
3.0
2.0
1.5
1.5
7.0
5.0
ns
ns
ns
5.0
1.5
1.5
1.5
6.0
4.0
tH
Hold Time, HIGH or LOW
3.3
−0.5
0
Dn to CP
5.0
tW
CP Pulse Width
HIGH or LOW
3.3
3.5
2.0
5.0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
C
L = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
(Note 9)
5.0
Units
Min
Typ
Max
Min Max
fMAX
tPLH
Maximum Clock Frequency
Propagation Delay
CP to On
100
110
85
ns
ns
5.0
5.0
2.5
2.0
7.0
6.5
11.0
10.0
2.0
12.0
11.0
tPHL
Propagation Delay
CP to On
1.5
ns
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
2.0
2.0
6.4
6.0
7.0
5.5
9.5
9.0
1.5
1.5
1.5
1.5
10.0
10.0
11.5
9.0
ns
ns
ns
ns
10.5
8.5
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements for ACT
VCC
TA = +25°C
TA = −40°C to +85°C
C
L = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Set-Up Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
1.5
−0.5
2.5
2.5
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
1.0
4.0
tW
CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
CIN
Input Capacitance
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
40.0
pF
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ Type II 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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