74ACT715SCX_NL [FAIRCHILD]
Consumer Circuit, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20;型号: | 74ACT715SCX_NL |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Consumer Circuit, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20 |
文件: | 总18页 (文件大小:424K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 2007
74ACT715, 74ACT715-R
tm
Programmable Video Sync Generator
Features
General Description
■ Maximum Input Clock Frequency > 130MHz
■ Interlaced and non-interlaced formats available
The ACT715 and ACT715-R are 20-pin TTL-input
compatible devices capable of generating Horizontal,
Vertical and Composite Sync and Blank signals for tele-
visions and monitors. All pulse widths are completely
definable by the user. The devices are capable of gener-
ating signals for both interlaced and noninterlaced
modes of operation. Equalization and serration pulses
can be introduced into the Composite Sync signal when
needed.
■ Separate or composite horizontal and vertical Sync
and Blank signals available
■ Complete control of pulse width via register
programming
■ All inputs are TTL compatible
■ 8mA drive on all outputs
■ Default RS170/NTSC values mask programmed into
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can
be used to generate horizontal or vertical gating pulses,
cursor position or vertical Interrupt signal.
registers
■ ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818MHz
RS170 timing
These devices make no assumptions concerning the
system architecture. Line rate and field/frame rate are all
a function of the values programmed into the data regis-
ters, the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all
respects except that the ACT715-R is mask pro-
grammed to default to a Clock Enabled state. Bit 10 of
the Status Register defaults to a logic “1”. Although
completely (re)programmable, the ACT715-R version is
better suited for applications using the default
14.31818MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
Ordering Information
Package
Order Number
74ACT715SC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT715-RSC
M20B
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
Connection Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the
ACT715.
CLR: The CLEAR pin is an asynchronous input that ini-
tializes the device when it is HIGH. Initialization consists
of setting all registers to their mask programmed values,
and initializing all counters, comparators and registers.
The CLEAR pin has been implemented as a Schmitt
trigger for better noise immunity. A CLEAR pulse should
be asserted by the user immediately after power-up to
ensure proper initialization of the registers—even if the
user plans to (re)program the device.
Data Inputs D0–D7: The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA signal is latched into
the device on the falling edge of the LOAD signal. The
signal determines if an address (0) or data (1) is present
on the data bus.
L/HBYTE: The L/HBYTE signal is latched into the device
on the falling edge of the LOAD signal. The signal deter-
mines if data will be read into the 8 LSB's (0) or the
4 MSB's (1) of the Data Registers. A 1 on this pin when
an ADDR/DATA is a 0 enables Auto-Load Mode.
Note: A CLEAR pulse will disable the CLOCK on the ACT715
and will enable the CLOCK on the ACT715-R.
ODD/EVEN: Output that identifies if display is in odd
(HIGH) or even (LOW) field of interlace when device is in
interlaced mode of operation. In noninterlaced mode of
operation this output is always HIGH. Data can be seri-
ally scanned out on this pin during Scan Mode.
LOAD: The LOAD control pin loads data into the
Address or Data Registers on the rising edge. ADDR/
DATA and L/HBYTE data is loaded into the device on
the falling edge of the LOAD. The LOAD pin has been
implemented as a Schmitt trigger input for better noise
immunity.
VCSYNC: Outputs Vertical or Composite Sync signal
based on value of the Status Register. Equalization and
Serration pulses will (if enabled) be output on the
VCSYNC signal in composite mode only.
CLOCK: System CLOCK input from which all timing is
derived. The clock pin has been implemented as a
Schmitt trigger for better noise immunity. The CLOCK
and the LOAD signal are asynchronous and indepen-
dent. Output state changes occur on the falling edge of
CLOCK.
VCBLANK: Outputs Vertical or Composite Blanking
signal based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking signal, Horizon-
tal Gating signal or Cursor Position based on value of
the Status Register.
HSYNVDR: Outputs Horizontal Sync signal, Vertical
Gating signal or Vertical Interrupt signal based on value
of Status Register.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
2
Logic Block Diagram
Figure 1.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current
V = –0.5V
–20mA
+20mA
I
V = V + 0.5V
I
CC
V
DC Input Voltage
–0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
O
CC
V
DC Output Voltage
DC Output Source or Sink Current
–0.5V to V + 0.5V
O
CC
I
15mA
20mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
–65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
4.5V to 5.5V
CC
V
Input Voltage
0V to V
0V to V
I
CC
CC
V
Output Voltage
O
T
Operating Temperature
Minimum Input Edge Rate:
–40°C to +85°C
125mV/ns
A
∆V / ∆t
V
from 0.8V to 2.0V, V @ 4.5V, 5.5V
CC
IN
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
4
Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with
respect to the number of clock pulses per line and verti-
cal pulses are specified with respect to the number of
lines per frame.
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9—
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
B10— Disable System Clock (0)
Enable System Clock (1)
REG0—Status Register
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
B11— Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
Bits 0–2
This bit is not intended for the user but is for
internal testing only.
B
B
B
0
VCBLANK VCSYNC HBLHDR HSYNVDR
2
1
Horizontal Interval Registers
0
0
0
CBLANK
CSYNC
HGATE
VGATE
The Horizontal Interval Registers determine the number
of clock cycles per line and the characteristics of the
Horizontal Sync and Blank pulses.
(DEFAULT)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC HBLANK
VGATE
HSYNC
HSYNC
VINT
VSYNC
VSYNC
CSYNC
HGATE
HBLANK
CUSOR
REG1— Horizontal Front Porch
REG2— Horizontal Sync Pulse End Time
REG3— Horizontal Blanking Width
CSYNC HBLANK
VINT
REG4— Horizontal Interval Width # of Clocks per Line
VSYNC
VSYNC
CUSOR
HSYNC
HSYNC
Vertical Interval Registers
HBLANK
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical
Blank and Sync Pulses.
Bits 3–4
B
B
Mode of Operation
4
3
REG5— Vertical Front Porch
0
0
Interlaced Double Serration and Equalization
REG6— Vertical Sync Pulse End Time
REG7— Vertical Blanking Width
(DEFAULT)
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
REG8— Vertical Interval Width # of Lines per Frame
Equalization and Serration Pulse Specification
Registers
Non Interlaced Single Serration and Equalization
Double Equalization and Serration mode will output
equalization and serration pulses at twice the HSYNC
frequency (i.e., 2 equalization or serration pulses for
every HSYNC pulse). Single Equalization and Serration
mode will output an equalization or serration pulse for
every HSYNC pulse. In Interlaced mode equalization
and serration pulses will be output during the VBLANK
period of every odd and even field. Interlaced Single
Equalization and Serration mode is not possible with this
part.
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9— Equalization Pulse Width End Time
REG10— Serration Pulse Width End Time
REG11— Equalization/Serration Pulse Vertical Interval
Start Time
REG12— Equalization/Serration Pulse Vertical Interval
End Time
Bits 5–8
Vertical Interrupt Specification Registers
Bits 5 through 8 control the polarity of the outputs. A
value of zero in these bit locations indicates an output
pulse active LOW. A value of 1 indicates an active HIGH
pulse.
These Registers determine the width of the Vertical
Interrupt signal if used.
REG13— Vertical Interrupt Activate Time
REG14— Vertical Interrupt Deactivate Time
B5—
B6—
B7—
B8—
VCBLANK Polarity
VCSYNC Polarity
HBLHDR Polarity
HSYNVDR Polarity
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
5
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location,
or they generate separate Horizontal and Vertical Gating
signals.
REG15— Horizontal Cursor Position Start Time
REG16— Horizontal Cursor Position End Time
REG17— Vertical Cursor Position Start Time
REG18— Vertical Cursor Position End Time
Signal Specification
always based on whole-lines and does not add 1 for the
first clock. The vertical counter starts at the value of 1
and counts until the value of VMAX. No restrictions exist
on the values placed in the vertical registers. Vertical
Blank will change on the leading edge of HBLANK. Verti-
cal Sync will change on the leading edge of HSYNC.
(See Figure 3.) Vertical Frame Period (VPER) = REG(8)
× hper
Horizontal Sync and Blank Specifications
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is consid-
ered pulse 1 not 0. All values of the horizontal timing reg-
isters are referenced to the falling edge of the Horizontal
Blank signal (See Figure 2). Since the first CLOCK edge,
CLOCK #1, causes the first falling edge of the Horizontal
Blank reference pulse, edges referenced to this first
Horizontal edge are n + 1 CLOCKs away, where “n” is
the width of the timing in question. Registers 1, 2, and 3
are programmed in this manner. The horizontal counters
start at 1 and count until HMAX. The value of HMAX
must be divisible by 2. This limitation is imposed because
during interlace operation this value is internally divided
by 2 in order to generate serration and equalization
pulses at 2 × the horizontal frequency. Horizontal signals
will change on the falling edge of the CLOCK signal.
Signal specifications are shown below.
Vertical Field Period (VPER/n) = REG(8) × hper/n
Vertical Blanking Width = [REG(7) – 1] × hper/n
Vertical Syncing Width = [REG(6) – REG(5)] × hper/n
Vertical Front Porch = [REG(5) – 1] × hper/n
where,
n = 1 for noninterlaced
n = 2 for interlaced
Composite Sync and Blank Specifications
Horizontal Period (HPER) = REG(4) × ckper
Horizontal Blanking Width = [REG(3) – 1] × ckper
Horizontal Sync Width = [REG(2) – REG(1)] × ckper
Horizontal Front Porch = [REG(1) – 1] × ckper
Composite Sync and Blank signals are created by logi-
cally ANDing (ORing) the active LOW (HIGH) signals of
the corresponding vertical and horizontal components of
these signals. The Composite Sync signal may also
include serration and/or equalization pulses. The Serra-
tion pulse interval occurs in place of the Vertical Sync
interval. Equalization pulses occur preceding and/or
following the Serration pulses. The width and location of
these pulses can be programmed through the registers
shown below. (See Figure 4.)
Vertical Sync and Blank Specifications
All vertical signals are defined in terms of number of
lines per frame. This is true in both interlaced and nonin-
terlaced modes of operation. Care must be taken to not
specify the Vertical Registers in terms of lines per field.
Since the first CLOCK edge, CLOCK #1, causes the first
falling edge of the Vertical Blank (first Horizontal Blank)
reference pulse, edges referenced to this first edge are n
+ 1 lines away, where “n” is the width of the timing in
question. Registers 5, 6, and 7 are programmed in this
manner. Also, in the interlaced mode, vertical timing is
based on half-lines. Therefore registers 5, 6, and 7 must
contain a value twice the total horizontal (odd and even)
plus 1 (as described above). In non-interlaced mode, all
vertical timing is based on whole-lines. Register 8 is
Horizontal
Equalization PW = [REG(9) – REG(1)] × ckper
REG 9 = (HFP) + (HEQP) + 1
Horizontal
Serration PW = [REG(4)/n + REG(1) – REG(10)] × ckper
REG 10 = (HFP) + (HPER/2) – (HSERR) + 1
where,
n = 1 for noninterlaced single serration/equalization
n = 2 for noninterlaced double serration/equalization
n = 2 for interlaced operation
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
6
Figure 2. Horizontal Wave Specification
Figure 3. Vertical Waveform Specification
Figure 4. Equalization/Serration Interval Programming
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
7
Horizontal and Vertical Gating Signals
Cursor Position and Vertical Interrupt
Horizontal Drive and Vertical Drive outputs can be uti-
lized as general purpose Gating Signals. Horizontal and
Vertical Gating Signals are available for use when Com-
posite Sync and Blank signals are selected and the
value of Bit 2 of the Status Register is 0. The Vertical
Gating signal will change in the same manner as that
specified for the Vertical Blank.
The Cursor Position and Vertical Interrupt signal are
available when Composite Sync and Blank signals are
selected and Bit 2 of the Status Register is set to the
value of 1. The Cursor Position generates a single pulse
of n clocks wide during every line that the cursor is spec-
ified. The signals are generated by logically ORing
(ANDing) the active LOW (HIGH) signals specified by
the registers used for generating Horizontal and Vertical
Gating signals. The Vertical Interrupt signal generates a
pulse during the vertical interval specified. The Vertical
Interrupt signal will change in the same manner as that
specified for the Vertical Blanking signal.
Horizontal
Gating
Signal Width = [REG(16) – REG(15)] × ckper
Vertical
Gating
Horizontal Cursor Width = [REG(16) – REG(15)] × ckper
Vertical Cursor Width = [REG(18) – REG(17)] × hper
Vertical Interrupt Width = [REG(14) – REG(13)] × hper
Signal Width = [REG(18) – REG(17)] × hper
Addressing Logic
The register addressing logic is composed of two blocks
of logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).
Byte is written the address counter is incremented by 1.
The counter has been implemented to loop on the initial
value loaded into the address register. For example: If a
value of 0 was written into the address register then the
counter would count from 0 to 18 before resetting back
to 0. If a value of 15 was written into the address register
then the counter would count from 15 to 18 before loop-
ing back to 15. If a value greater than or equal to 18 is
placed into the address register the counter will continu-
ously loop on this value. Auto addressing is initiated on
the falling edge of LOAD when ADDRDATA is 0 and
LHBYTE is 1. Incrementing and loading of data registers
will not commence until the falling edge of LOAD after
ADDRDATA goes to 1. The next rising edge of LOAD
will load the first byte of data. Auto Incrementing is dis-
abled on the falling edge of LOAD after ADDRDATA and
LHBYTE goes low.
ADDRCNTR Logic
Addresses for the data registers can be generated by
one of two methods. Manual addressing requires that
each byte of each register that needs to be loaded needs
to be addressed. To load both bytes of all 19 registers
would require a total of 57 load cycles (19 address and
38 data cycles). Auto Addressing requires that only the
initial register value be specified. The Auto Load
sequence would require only 39 load cycles to com-
pletely program all registers (1 address and 38 data
cycles). In the auto load sequence the low order byte of
the data register will be written first followed by the high
order byte on the next load cycle. At the time the High
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
8
Manual Addressing Mode
Cycle #
Load Falling Edge
Load Rising Edge
1
2
3
4
5
6
Enable Manual Addressing
Enable Lbyte Data Load
Load Address m
Load Lbyte m
Load Hbyte m
Load Address n
Load Lbyte n
Load Hbyte n
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Auto Addressing Mode
Cycle #
Load Falling Edge
Load Rising Edge
1
2
3
4
5
6
Enable Auto Addressing
Enable Lbyte Data Load
Load Start Address n
Load Lbyte (n)
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Load Hbyte (n); Inc Counter
Load Lbyte (n+1)
Load Hbyte (n+1); Inc Counter
Load Address
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
9
ADDRDATA pin (Auto Addressing Mode) will not cause
this address to automatically increment. The address will
loop back onto itself regardless of the state of
ADDRDATA unless the address on the Data inputs has
been changed with ADDRDATA at 0.
ADDRDEC Logic
The ADDRDEC logic decodes the current address and
generates the enable signal for the appropriate register.
The enable values for the registers and counters change
on the falling edge of LOAD. Two types of ADDRDEC
logic is enabled by 2 pair of addresses, Addresses 22 or
54 (Vectored Restart logic) and Addresses 23 or 55
(Vectored Clear logic). Loading these addresses will
enable the appropriate logic and put the part into either a
Restart (all counter registers are reinitialized with prepro-
grammed data) or Clear (all registers are cleared to
zero) state. Reloading the same ADDRDEC address will
not cause any change in the state of the part. The
outputs during these states are frozen and the internal
CLOCK is disabled. Clocking the part during a Vectored
Restart or Vectored Clear state will have no effect on the
part. To resume operation in the new state, or disable
the Vectored Restart or Vectored Clear state, another
non-ADDRDEC address must be loaded. Operation will
begin in the new state on the rising edge of the non-
ADDRDEC load pulse. It is recommended that an
unused address be loaded following an ADDRDEC oper-
ation to prevent data registers from accidentally being
corrupted. The following Addresses are used by the
device.
Figure 5. ADDRDEC Timing
Gen Locking
The ACT715 and ACT715-R is designed for master
SYNC and BLANK signal generation. However, the
devices can be synchronized (slaved) to an external tim-
ing signal in a limited sense. Using Vectored Restart, the
user can reset the counting sequence to a given loca-
tion, the beginning, at a given time, the rising edge of the
LOAD that removes Vector Restart. At this time the next
CLOCK pulse will be CLOCK 1 and the count will restart
at the beginning of the first odd line.
Address 0
Status Register REG0
Data Registers REG1–REG18
Unused
Address 1–18
Address 19–21
Address 22/54
Address 23/55
Address 24–31
Address 32–50
Address 51–53
Address 56–63
Restart Vector (Restarts Device)
Clear Vector (Zeros All Registers)
Unused
Preconditioning the part during normal operation, before
the desired synchronizing pulse, is necessary. However,
since LOAD and CLOCK are asynchronous and inde-
pendent, this is possible without interruption or data and
performance corruption. If the defaulted 14.31818MHz
RS-170 values are being used, preconditioning and
restarting can be minimized by using the CLEAR pulse
instead of the Vectored Restart operation. The ACT715-R
is better suited for this application because it eliminates
the need to program a 1 into Bit 10 of the Status Register
to enable the CLOCK. Gen Locking to another count
location other than the very beginning or separate
horizontal/vertical resetting is not possible with the
ACT715 nor the ACT715-R.
Register Scan Addresses
Counter Scan Addresses
Unused
At any given time only one register at most is selected. It
is possible to have no registers selected.
Vectored Restart Address
The function of addresses 22 (16H) or 54 (36H) are sim-
ilar to that of the CLR pin except that the preprogram-
ming of the registers is not affected. It is recommended
but not required that this address is read after the initial
Scan Mode Logic
device configuration load sequence.
A 1 on the
A scan mode is available in the ACT715 that allows the
user to non-destructively verify the contents of the regis-
ters. Scan mode is invoked through reading a scan
address into the address register. The scan address of a
given register is defined by the Data register address + 32.
The internal Clocking signal is disabled when a scan
address is read. Disabling the clock freezes the device in
it's present state. Data can then be serially scanned out
of the data registers through the ODD/EVEN Pin. The
LSB will be scanned out first. Since each register is
12 bits wide, completely scanning out data of the
addressed register will require 12 CLOCK pulses. More
ADDRDATA pin (Auto Addressing Mode) will not cause
this address to automatically increment. The address will
loop back onto itself regardless of the state of
ADDRDATA unless the address on the Data inputs has
been changed with ADDRDATA at 0.
Vectored Clear Address
Addresses 23 (17H) or 55 (37H) is used to clear all regis-
ters to zero simultaneously. This function may be desir-
able to use prior to loading new data into the Data or
Status Registers. This address is read into the device in
a similar fashion as all of the other registers. A 1 on the
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
10
than 12 CLOCK pulses on the same register will only
cause the MSB to repeat on the output. Re-scanning the
same register will require that register to be reloaded.
The value of the two horizontal counters and 1 vertical
counter can also be scanned out by using address num-
bers 51–53. Note that before the part will scan out the
data, the LOAD signal must be brought back HIGH.
Normal device operation can be resumed by loading in a
non-scan address. As the scanning of the registers is a
non-destructive scan, the device will resume correct
operation from the point at which it was halted.
RS170 Default Register Values
The tables below show the values programmed for the
RS170 Format (using a 14.31818 MHz clock signal) and
how they compare against the actual EIA RS170 Specifi-
cations. The default signals that will be output are
CSYNC, CBLANK, HDRIVE and VDRIVE. The device
initially starts at the beginning of the odd field of inter-
lace. All signals have active low pulses and the clock is
disabled at power up. Registers 13 and 14 are not
involved in the actual signal information. If the Vertical
Interrupt was selected so that a pulse indicating the
active lines would be output.
Reg
REG0
REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
REG10
REG11
REG12
REG13
REG14
REG15
REG16
REG17
REG18
D Value H
Register Description
0
000
400
017
05B
09D
38E
007
00D
029
20D
039
19A
001
013
029
20E
38F
05C
001
015
Status Register (715)
1024
23
Status Register (715-R)
HFP End Time
91
HSYNC Pulse End Time
HBLANK Pulse End Time
Total Horizontal Clocks
VFP End Time
157
910
7
13
VSYNC Pulse End Time
VBLANK Pulse End Time
Total Vertical Lines
41
525
57
Equalization Pulse End Time
Serration Pulse Start Time
Pulse Interval Start Time
Pulse Interval End Time
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
Horizontal Drive Start Time
Horizontal Drive End Time
Vertical Drive Start Time
Vertical Drive End Time
410
1
19
41
526
911
92
1
21
Rate
Period
Input Clock
Line Rate
14.31818MHz
15.73426kHz
59.94Hz
69.841ns
63.556µs
16.683ms
33.367ms
Field Rate
Frame Rate
29.97Hz
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
11
RS170 Horizontal Data
Signal
Width
µs
%H
Specification (µs)
1.5 0.1
HFP
22 Clocks
68 Clocks
156 Clocks
91 Clocks
34 Clocks
68 Clocks
910 Clocks
1.536
4.749
10.895
6.356
2.375
4.749
63.556
HSYNC Width
HBLANK Width
HDRIVE Width
HEQP Width
HSERR Width
HPER iod
7.47
17.15
10.00
3.74
7.47
100
4.7 0.1
10.9 0.2
0.1H 0.005H
2.3 0.1
4.7 0.1
RS170 Verticle Data
Signal
Width
3 Lines
µs
%H
Specification (µs)
6 EQP Pulses
VFP
190.67
190.67
1271.12
699.12
VSYNC Width
VBLANK Width
VDRIVE Width
VEQP Intrvl
3 Lines
6 Serration Pulses
0.075V 0.005V
0.04V 0.006V
9 Lines/Field
20 Lines
11.0 Lines
9 Lines
7.62
4.20
3.63
VPERiod (field)
VPERiod (frame)
262.5 Lines
525 Lines
16.683 ms
33.367 ms
16.683ms/Field
33.367ms/Frame
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
12
DC Electrical Characteristics
For ACT Family Devices over Operating Temperature Range (unless otherwise specified).
T = +25°C,
A
C = 50pF T = –40°C to +85°C
L
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH
4.5
V
= 0.1V
1.5
1.5
2.0
2.0
2.0
2.0
V
IH
OUT
Level Input Voltage
or V – 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
V
Maximum LOW
V
= 0.1V
1.5
0.8
0.8
V
V
V
V
V
IL
OUT
Level Input Voltage
or V – 0.1V
CC
1.5
0.8
0.8
V
Minimum HIGH
I
= –50 µA
OUT
4.49
5.49
4.4
4.4
OH
Level Output Voltage
5.4
5.4
V
I
= V /V ,
3.86
4.86
0.1
3.76
4.76
0.1
IN
IL IH
(1)
= –8 mA
OH
V
Maximum LOW
I
= 50µA
OUT
0.001
0.001
OL
Level Output Voltage
0.1
0.1
V
I
= V /V ,
0.36
0.36
0.44
0.44
32.0
IN
IL IH
(1)
= +8mA
= 1.65V
OLD
OH
I
Minimum Dynamic
Output Current
V
mA
mA
µA
OLD
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
5.5
V
= 3.85V
–32.0
1.0
OHD
OHD
I
Maximum Input
Leakage Current
V = V , GND
0.1
8.0
IN
I
CC
I
Supply Current
Quiescent
V
= V , GND
80
µA
CC
IN
IN
CC
I
Maximum I /Input
V
= V – 2.1V
0.6
1.5
mA
CCT
CC
CC
Notes:
1. All outputs loaded; thresholds on input associated with input under test.
2. Test Load 50pF, 500Ω to Ground.
AC Electrical Characteristics
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
f
Interlaced f
5.0
170
190
150
MHz
MAXI
MAX
(HMAX/2 is ODD)
f
Non-Interlaced f
5.0
190
220
175
MHz
MAX
MAX
(HMAX/2 is EVEN)
t
t
, t
Clock to Any Output
5.0
5.0
4.0
4.5
13.0
15.0
15.5
17.0
3.5
3.5
18.5
20.5
ns
ns
PLH1 PHL1
, t
Clock to ODDEVEN
(Scan Mode)
PLH2 PHL2
t
Load to Outputs
5.0
4.0
11.5
16.0
3.0
19.5
ns
PLH3
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
13
AC Operating Requirements
T = +25°C
T = –40°C to +85°C
A
A
Symbol
Parameter
Control Setup Time:
ADDR/DATA to LOAD–
L/HBYTE to LOAD–
Data Setup Time:
V
(V)
Typ.
Guaranteed Minimums
Units
CC
t
t
5.0
3.0
3.0
4.0
4.5
4.5
ns
ns
sc
4.0
sc
t
D7–D0 to LOAD+
5.0
5.0
2.0
4.0
4.5
ns
sd
hc
Control Hold Time:
LOAD– to ADDR/DATA
LOAD– to L/HBYTE
Data Hold Time:
t
0
0
1.0
1.0
1.0
1.0
ns
ns
t
t
hc
t
hd
LOAD+ to D7–D0
5.0
5.0
1.0
5.5
2.0
7.0
2.0
8.0
ns
ns
(3)
LOAD+ to CLK
rec
Load Pulse Width:
LOW
t
5.0
3.0
3.0
5.5
2.5
5.5
5.0
6.5
3.0
5.5
7.5
9.5
3.5
ns
ns
ns
ns
wld–
t
HIGH
wld+
t
CLR Pulse Width HIGH
5.0
5.0
wclr
t
CLOCK Pulse Width
(HIGH or LOW)
wck
Note:
3. Removal of Vectored Reset or Restart to Clock.
Capacitance
Symbol
Parameter
Conditions
Typ.
7.0
Units
pF
C
Input Capacitance
Power Dissipation Capacitance
V
V
= 5.0V
= 5.0V
IN
CC
CC
C
17.0
pF
PD
Figure 6. AC Specifications
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
14
Additional Applications Information
Powering Up
Preprogramming “On-the-Fly”
The ACT715 default value for Bit 10 of the Status Regis-
ter is 0. This means that when the CLEAR pulse is
applied and the registers are initialized by loading the
default values the CLOCK is disabled. Before operation
can begin, Bit 10 must be changed to a 1 to enable
CLOCK. If the default values are needed (no other pro-
gramming is required) then Figure 7 illustrates a hard-
wired solution to facilitate the enabling of the CLOCK
after power-up. Should control signals be difficult to
obtain, Figure 8 illustrates a possible solution to auto-
matically enable the CLOCK upon power-up. Use of the
ACT715-R eliminates the need for most of this circuitry.
Modifications of the Figure 8 circuit can be made to
obtain the lone CLEAR pulse still needed upon power-up.
Although the ACT715 and ACT715-R are completely
programmable, certain limitations must be set as to
when and how the parts can be reprogrammed. Care
must be taken when reprogramming any End Time reg-
isters to a new value that is lower than the current value.
Should the reprogramming occur when the counters are
at a count after the new value but before the old value,
then the counters will continue to count up to 4096
before rolling over.
For this reason one of the following two precautions are
recommended when reprogramming “on-the-fly”. The
first recommendation is to reprogram horizontal values
during the horizontal blank interval only and/or vertical
values during the vertical blank interval only. Since this
would require delicate timing requirements the second
recommendation may be more appropriate.
Note that, although during a Vectored Restart none of
the preprogrammed registers are affected, some signals
are affected for the duration of one frame only. These
signals are the Horizontal and Vertical Drive signals.
After a Vectored Restart the beginning of these signals
will occur at the first CLK. The end of the signals will
occur as programmed. At the completion of the first
frame, the signals will resume to their programmed start
and end time.
The second recommendation is to program a Vectored
Restart as the final step of reprogramming. This will
ensure that all registers are set to the newly pro-
grammed values and that all counters restart at the first
CLK position. This will avoid overrunning the counter
end times and will maintain the video integrity.
Figure 7. Default RS170 Hardwire Configuration
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
15
Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND
Components
R1: 4.7k
R2: 10k
C1: 10µF
C2: 50pF
Figure 8. Circuit for Clear and Load Pulse Generation
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
16
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 9. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
17
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
ACEx®
TinyLogic®
TINYOPTO¥
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TinyWire¥
TruTranslation¥
PSerDes¥
UHC®
UniFET¥
VCX¥
Wire¥
HiSeC¥
i-Lo¥
Programmable Active Droop¥
QFET®
QS¥
QT Optoelectronics¥
Quiet Series¥
RapidConfigure¥
RapidConnect¥
ScalarPump¥
SMART START¥
SPM®
STEALTH™
SuperFET¥
SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET™
Across the board. Around the world.¥
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IntelliMAX¥
ISOPLANAR¥
MICROCOUPLER¥
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CTL™
Current Transfer Logic™
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OCX¥
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PACMAN¥
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
18
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