74ACT818QCQR [FAIRCHILD]
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | 74ACT818QCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PQCC28, PLASTIC, LCC-28 |
| 文件： | 总6页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1988
Revised September 2000
74ACT818
8-Bit Diagnostic Register
General Description
The ACT818 is a high-speed, general-purpose pipeline
register with an on-board diagnostic register for performing
serial diagnostics and/or writable control store loading.
Features
■ On-line and off-line system diagnostics
■ Swaps the contents of diagnostic register and output
register
The D-to-Y path provides an 8-bit parallel data path pipe-
line register for normal system operation. The diagnostic
register can load parallel data to or from the pipeline regis-
ter and can output data through the D input port (as in
WCS loading).
■ Diagnostic register and diagnostic testing
■ Cascadable for wide control words as used in micropro-
gramming
■ Edge-triggered D registers
■ Outputs source/sink 24 mA
■ ACT818 has TTL-compatible inputs
The 8-bit diagnostic register has multiplexer inputs that
select parallel inputs from the Y-port or adjacent bits in the
diagnostic register to operate as a right-shift-only register.
This register can then participate in a serial loop throughout
the system where normal data, address, status and control
registers are replaced with ACT818 diagnostic pipeline reg-
isters. The loop can be used to scan in a complete test rou-
tine starting point (Data, Address, etc.). Then after a
specified number of machine cycles it scans out the results
to be inspected for the expected results. WCS loading can
be accomplished using the same technique. An instruction
word can be serially shifted into the shadow register and
written into the WCS RAM by enabling the D output.
■ ACT818 is functionally- and pin-compatible to AMD
Am29818 and MMI 74S818
Applications
•
•
•
•
•
•
•
•
Register for microprogram control store
Status register
Data register
Instruction register
Interrupt mask register
Pipeline register
General purpose register
Parallel-serial/serial-parallel converter
Ordering Code:
Order Number
Order Package
Package Description
74ACT818SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009801
www.fairchildsemi.com
Pin Descriptions
Functional Description
Data transfers into the diagnostic register occur on the
LOW-to-HIGH transition of DCLK. Mode and SDI deter-
mine what data source will be loaded. The pipeline register
is loaded on the LOW-to-HIGH transition of PCLK. Mode
selects whether the data source is the data input or the
diagnostic register output. Because of the independence of
the clock inputs, data can be shifted in the diagnostic regis-
ter via DCLK and loaded into the pipeline register from the
data input via PCLK simultaneously, as long as no setup or
hold times are violated. This simultaneous operation is
legal.
Pin Names
Description
Data Inputs
Serial Data Input
D0–D7
SDI
DCLK
MODE
PCLK
OEY
Diagnostics Clock
Control Input
Pipeline Register Clock
Output Enable Input
Serial Data Output
Data Outputs
SDO
Y0–Y7
Function Table
Inputs
Outputs
Operation
SDI MODE DCLK PCLK SDO Diagnostic Reg.
Pipeline Reg.
X
L
X
S7
SI<SI − 1,
SO<SDI
NA
NA
Serial Shift; D7–D0 Disabled
X
L
L
X
X
S7
L
PI<DI
Normal Load Pipeline Register
Load Diagnostic Register from Y;
DI Disabled
H
X
SI<YI
NA
X
H
H
H
SDI
H
NA
PI<SI
Load Pipeline Register from
Diagnostic Register
X
Hold
NA
Hold Diagnostic Register; DI
Enabled
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Diagnostic Register
Block Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC + 0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
± 50 mA
DC VCC or Ground Current
per Output Pin (I CC or IGND
)
± 50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
140°C
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
VIH
Minimum HIGH Level
2.0
2.0
2.0
V
Input Voltage
2.0
0.8
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
0.8
V
0.8
0.8
IIN
Maximum Input Leakage Current
± 0.1
± 1.0
µA
VIN = VCC
IOZ
Maximum 3-STATE
OE = VIH
5.5
5.5
5.5
± 0.5
± 5.0
80.0
1.5
µA
µA
mA
Leakage Current
VOUT = 0V, VCC
ICC
Maximum Quiescent Supply Current
Maximum Additional
8.0
V
IN = VCC or GND
IN = VCC − 2.1V
ICCT
V
I
CC/Input
VCC = 5.5V
VIN = VIL or VIH
VOH
Minimum HIGH
Level Output Voltage,
Y0–Y7 Outputs
4.5
5.5
3.86
4.86
3.76
4.76
V
V
I
OH = −24 mA
I
OH =−24 mA (Note 2)
Minimum HIGH
Level Output Voltage,
D0–D7, SDO Outputs
4.5
5.5
3.86
4.86
3.76
4.76
V
V
I
OH = −8 mA
OH = −8 mA
I
VOL
Maximum LOW
VIN = VIL or VIH
Level Output Voltage,
Y0–Y7 Outputs
4.5
5.5
4.5
5.5
0.36
0.36
0.36
0.36
0.44
0.44
0.44
0.44
V
V
V
V
I
I
I
I
OL = 24 mA
OL = 24 mA (Note 2)
OL = 8 mA
Maximum LOW Level Output Voltage,
D0–D7, SDO Outputs
OL = 8 mA
IOLD
IOHD
IOLD
Minimum Dynamic Output Current
Y0–Y7 Outputs
5.5
5.5
5.5
5.5
75
mA
mA
mA
mA
VOLD = 1.65V Max
Minimum Dynamic Output Current
Y0–Y7 Outputs
−75
VOHD = 3.85V Min
Minimum Dynamic Output Current
D0–D7, SDO Outputs (Note 3)
Minimum Dynamic Output Current
D0–D7, SDO Outputs (Note 3)
32
VOLD = 1.65V Max
IOHD
−32
VOHD = 3.85V Min
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Test load 50 pF, 500Ω to ground.
3
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AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 4)
Min
Typ
Max
Min
tPHL
Propagation Delay
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
3.0
6.0
6.5
8.0
8.0
7.5
7.5
9.0
9.5
6.0
5.5
8.0
8.5
8.0
9.0
6.5
7.5
9.0
2.5
2.5
3.5
4.0
3.0
3.5
4.0
4.0
2.5
1.0
3.0
1.5
2.5
2.0
3.0
2.0
9.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCLK to Y
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
Propagation Delay
PCLK to Y
3.0
4.0
4.0
3.5
3.5
4.5
4.5
2.5
1.5
3.0
2.0
3.0
2.5
3.0
3.0
9.0
11.0
11.5
10.5
10.5
12.5
13.0
9.0
10.0
12.0
12.5
12.0
12.0
14.0
14.5
10.0
9.0
Propagation Delay
MODE to SDO
Propagation Delay
MODE to SDO
Propagation Delay
SDI to SDO
Propagation Delay
SDI to SDO
Propagation Delay
DCLK to SDO
Propagation Delay
DCLK to SDO
Output Enable Time
OEY to Yn
Output Disable Time
OEY to Yn
8.0
Output Enable Time
DCLK to Dn
12.0
11.0
10.0
11.0
11.5
12.0
13.5
12.0
11.0
11.5
13.0
13.0
Output Disable Time
DCLK to Dn
Output Enable Time
OEY to Yn
Output Disable Time
OEY to Yn
Output Enable Time
DCLK to Dn
Output Disable Time
DCLK to Dn
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
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4
AC Operating Requirements
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 5)
Typ
Guaranteed Minimum
tS
tH
tH
tH
tS
tS
tS
tH
tS
tH
tS
tS
tW
tW
Setup Time
D to PCLK
Hold Time
D to PCLK
Setup Time
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
1.0
4.0
1.0
4.5
0.0
2.5
1.0
4.0
1.0
3.5
1.0
9.0
11.0
3.0
3.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.0
2.5
1.0
5.5
0.0
2.5
1.5
4.0
1.0
4.5
1.0
10.5
11.5
3.0
3.0
MODE to PCLK
Hold Time
−1.0
0.5
0
MODE to PCLK
Setup Time
Y to DCLK
Hold Time
Y to DCLK
Setup Time
2.0
−0.5
2.0
−0.5
6.0
6.0
2.0
2.0
MODE to DCLK
Hold Time
MODE to DCLK
Setup Time
SDI to DCLK
Hold Time
SDI to DCLK
Setup Time
DCLK to PCLK
Setup Time
PCLK to DCLK
Pulse Width
PCLK HIGH or LOW
Pulse Width
DCLK HIGH or LOW
Note 5: Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
4.5
20
Units
Conditions
CIN
Input Capacitance
pF
pF
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
V
5
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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