74ACT825DCQR
更新时间：2024-09-18 12:58:26
品牌：FAIRCHILD
描述：Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDIP24, CERAMIC, DIP-24
概述
规格参数
数据手册74ACT825DCQR 概述
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDIP24, CERAMIC, DIP-24 总线驱动器/收发器
74ACT825DCQR 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | DIP | 包装说明： | DIP, DIP24,.6 |
| 针数： | 24 | Reach Compliance Code： | unknown |
| 风险等级： | 5.37 | 其他特性： | WITH TRIPLE OUTPUT ENABLE |
| 系列： | ACT | JESD-30 代码： | R-GDIP-T24 |
| JESD-609代码： | e0 | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | BUS DRIVER | 最大I（ol）： | 0.024 A |
| 位数： | 8 | 功能数量： | 1 |
| 端口数量： | 2 | 端子数量： | 24 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | CERAMIC, GLASS-SEALED | 封装代码： | DIP |
| 封装等效代码： | DIP24,.6 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 5.715 mm | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 15.24 mm | Base Number Matches： | 1 |
74ACT825DCQR 数据手册
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PDF下载July 1988
Revised September 2000
74ACT825
8-Bit D-Type Flip-Flop
General Description
Features
The ACT825 is an 8-bit buffered register. They have Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming sys-
tems. Also included are multiple enables that allow multi-
use control of the interface. The ACT825 has noninverting
outputs.
■ Outputs source/sink 24 mA
■ Inputs and outputs are on opposite sides
■ TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT825SC
74ACT825MTC
74ACT825SPC
M24B
MTC24
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
O0–O7
Data Outputs
Output Enables
Clock Enable
Clear
OE1, OE2, OE3
EN
CLR
CP
Clock Input
FACT is a trademark of Fairchild Semiconductor.
© 2000 Fairchild Semiconductor Corporation
DS009895
www.fairchildsemi.com
Functional Description
The ACT825 consists of eight D-type edge-triggered flip-
flops. These devices have 3-STATE outputs for bus sys-
tems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3
Operation of the OE input does not affect the state of the
flip-flops. The ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
LOW, the contents of the flip-flops are available at the out-
puts. When one of OE1, OE2 or OE3 is HIGH, the outputs
go to the high impedance state.
Function Table
Inputs
Internal
Q
Output
O
Function
OE
CLR
EN
CP
Dn
H
H
H
L
X
X
L
L
L
L
H
X
X
X
X
L
L
H
Z
Z
High-Z
High-Z
Clear
Clear
Hold
X
X
H
H
L
X
X
X
X
L
Z
L
L
L
H
L
H
H
H
H
H
H
NC
NC
L
Z
NC
Z
Hold
H
H
L
Load
Load
Load
Load
L
H
L
H
Z
L
L
L
L
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to 7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
+0.5V
V
IN from 0.8V to 2.0V
O = VCC +0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source or Sink Current
(IO)
± 50 mA
DC VCC or Ground Current
Per Output Pin (ICC or IGND
)
± 50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
140°C
DC Electrical Characteristics
VCC
T
A = 25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
1.5
1.5
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC −0.1V
OUT = 0.1V
or VCC −0.1V
V
V
V
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
0.36
0.36
± 0.1
0.44
0.44
± 1.0
I
I
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input Leakage Current
Maximum
µA
µA
VI = VCC, GND
VI = VIL, VIH
IOZ
5.5
±0.5
±5.0
3-STATE Current
V
O = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
VI = VCC −2.1V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
−75
5.5
8.0
80
µA
V
IN = VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
(V)
Units
Parameter
(Note 4)
Min
Typ
Max
Min
fMAX
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
Maximum Clock
Frequency
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
158
5.5
5.5
8.0
6.0
6.5
6.5
6.0
109
1.5
1.5
2.0
1.5
1.5
1.5
1.5
MHz
ns
Propagation Delay
CP to On
1.5
2.0
2.5
1.5
2.0
1.5
1.5
9.5
9.5
10.5
10.5
15.5
11.5
12.0
12.0
11.5
Propagation Delay
CP to On
ns
Propagation Delay
CLR to On
13.5
10.5
11.0
11.0
10.5
ns
Output Enable Time
OE to On
ns
Output Enable Time
OE to On
ns
Output Disable Time
OE to On
ns
Output Disable Time
OE to On
ns
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 5)
Typ
Guaranteed Minimum
tS
tH
tS
tH
tW
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
5.0
0.5
0
2.5
2.5
2.0
1.0
2.5
ns
ns
ns
ns
Hold Time, HIGH or LOW
2.5
2.5
1.0
Dn to CP
Setup Time, HIGH or LOW
EN to CP
0
Hold Time, HIGH or LOW
EN to CP
0
CP Pulse Width
HIGH or LOW
5.0
5.0
5.0
2.5
3.0
1.5
4.5
5.5
3.5
5.5
5.5
4.0
ns
ns
ns
tW
CLR Pulse Width, LOW
tREC
CLR to CP
Recovery Time
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
44
Units
pF
Conditions
CIN
Input Capacitance
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
pF
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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74ACT825DCQR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 74ACT825FC | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERAMIC, FP-24 | 获取价格 |
|
| 74ACT825FCQR | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERAMIC, FP-24 | 获取价格 |
|
| 74ACT825FCT | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERAMIC, FP-24 | 获取价格 |
|
| 74ACT825FCX | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERAMIC, FP-24 | 获取价格 |
|
| 74ACT825FCXR | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CDFP24, CERAMIC, FP-24 | 获取价格 |
|
| 74ACT825LC | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC28, CERAMIC, LCC-28 | 获取价格 |
|
| 74ACT825LCT | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC28, CERAMIC, LCC-28 | 获取价格 |
|
| 74ACT825LCX | FAIRCHILD | 暂无描述 | 获取价格 |
|
| 74ACT825LCXR | FAIRCHILD | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC28, CERAMIC, LCC-28 | 获取价格 |
|
| 74ACT825MTC | FAIRCHILD | 8-Bit D-Type Flip-Flop | 获取价格 |
|
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