74ACT841SCX [FAIRCHILD]
10-Bit D-Type Latch ; 10位D类锁存器\n
| 型号： | 74ACT841SCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 10-Bit D-Type Latch
|
| 文件： | 总7页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised September 2000
74ACT841
10-Bit Transparent Latch with 3-STATE Outputs
General Description
Features
The ACT841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ACT841 is a 10-bit transparent
latch, a 10-bit version of the ACT373.
■ ACT841 has TTL-compatible inputs
■ Outputs source/sink 24 mA
■ Non-inverting 3-STATE outputs
Ordering Code:
Order Number Package Number
Package Description
74ACT841SC
74ACT841MTC
74ACT841SPC
M24B
MTC24
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Data Inputs
3-STATE Outputs
D0–D9
O0–O9
OE
Output Enable
Latch Enable
LE
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010156
www.fairchildsemi.com
Functional Description
The ACT841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
Inputs
Internal
Output
Function
O
OE
X
LE
X
D
X
L
Q
X
Z
Z
High Z
H
H
H
L
H
H
L
L
High Z
H
X
L
H
Z
High Z
NC
L
Z
Latched
Transparent
Transparent
Latched
H
H
L
L
L
H
X
H
H
L
NC
NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC + 0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
140°C
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
V
IN = VIL or VIH
OH = −24 mA
OH = −24 mA (Note 2)
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
OL = 24 mA
OL = 24 mA (Note 2)
4.5
5.5
0.36
0.36
0.44
0.44
I
I
IIN
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
5.5
5.5
5.5
±0.1
±0.5
±1.0
±5.0
1.5
µA
µA
µA
VI = VCC, GND
IOZ
VI = VIL, VIH
VO = VCC, GND
ICCT
0.6
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
8.0
80.0
µA
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
3
www.fairchildsemi.com
AC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
C
L = 50 pF
C
L = 50 pF
Max
Symbol
Parameter
(V)
Units
(Note 4)
Min
Typ
Max
Min
tPLH
Propagation Delay
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
5.5
5.5
5.5
5.5
5.5
5.5
6.0
6.0
9.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
10.0
10.0
10.0
10.0
10.5
10.5
11.0
11.0
ns
ns
ns
ns
ns
ns
ns
ns
Dn to On
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
2.0
2.0
2.0
2.0
2.0
2.0
2.0
9.5
9.0
Dn to On
Propagation Delay
LE to On
Propagation Delay
LE to On
9.0
Output Enable Time
OE to On
9.5
Output Enable Time
OE to On
9.5
Output Disable Time
OE to On
10.5
10.5
Output Disable Time
OE to On
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
VCC
T
A = +25°C
TA = −40°C to +85°C
CL = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 5)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to LE
5.0
−0.5
0.5
1.0
ns
tH
Hold Time, HIGH or LOW
5.0
5.0
0.5
2.0
2.0
3.5
2.0
3.5
ns
ns
Dn to LE
tW
LE Pulse Width, HIGH
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
pF
Conditions
CC = OPEN
CC = 5.0V
CIN
Input Capacitance
4.5
44
V
CPD
Power Dissipation Capacitance
pF
V
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
7
www.fairchildsemi.com
相关型号：
74ACT841SDC
Bus Driver, ACT Series, 1-Func, 10-Bit, True Output, CMOS, CDIP24, 0.300 INCH, SLIM, CERAMIC, DIP-24
FAIRCHILD
74ACT842DCQR
Bus Driver, ACT Series, 1-Func, 10-Bit, Inverted Output, CMOS, CDIP24, CERAMIC, DIP-24
FAIRCHILD
74ACT842FCQR
Bus Driver, ACT Series, 1-Func, 10-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT842FCX
Bus Driver, ACT Series, 1-Func, 10-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT842FCXR
Bus Driver, ACT Series, 1-Func, 10-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT842LCT
Bus Driver, ACT Series, 1-Func, 10-Bit, Inverted Output, CMOS, CQCC28, CERAMIC, LCC-28
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明