74ACT899 [FAIRCHILD]

9-Bit Latchable Transceiver with Parity Generator/Checker; 9位闭锁收发器奇偶校验发生器/校验器
74ACT899
型号: 74ACT899
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

9-Bit Latchable Transceiver with Parity Generator/Checker
9位闭锁收发器奇偶校验发生器/校验器

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中文:  中文翻译
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January 1990  
Revised December 1998  
74ACT899  
9-Bit Latchable Transceiver with Parity  
Generator/Checker  
General Description  
Features  
Latchable transceiver with output sink of 24 mA  
The ACT899 is a 9-bit to 9-bit parity transceiver with trans-  
parent latches. The device can operate as a feed-through  
transceiver or it can generate/check parity from the 8-bit  
data busses in either direction. The ACT899 features inde-  
pendent latch enables for the A-to-B direction and the B-to-  
A direction, a select pin for ODD/EVEN parity, and sepa-  
rate error signal output pins for checking parity.  
Option to select generate parity and check or  
“feed-through” data/parity in directions A-to-B or B-to-A  
Independent latch enable for A-to-B and B-to-A  
directions  
Select pin for ODD/EVEN parity  
ERRA and ERRB output pins for parity checking  
Ability to simultaneously generate and check parity  
May be used in system applications in place of the 280  
May be used in system applications in place of the 657  
and 373 (no need to change T/R to check parity)  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACT899QC  
V28A  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Assignment for PCC  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010637.prf  
www.fairchildsemi.com  
Pin Descriptions  
Functional Description  
The ACT899 has three principal modes of operation which  
are outlined below. These modes apply to both the A-to-B  
and B-to-A directions.  
Pin Names  
Description  
A0–A7  
A Bus Data Inputs/Data Outputs  
B Bus Data Inputs/Data Outputs  
A and B Bus Parity Inputs  
Bus A (B) communicates to Bus B (A), parity is gener-  
ated and passed on to the B (A) Bus as BPAR (APAR). If  
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,  
the parity generated from B[0:7] (A[0:7]) can be checked  
and monitored by ERRB (ERRA).  
B0–B7  
APAR, BPAR  
ODD/EVEN  
ODD/EVEN Parity Select,  
Active LOW for EVEN Parity  
Bus A (B) communicates to Bus B (A) in a feed-through  
mode if SEL is HIGH. Parity is still generated and  
checked as ERRA and ERRB in the feed-through mode  
(can be used as an interrupt to signal a data/parity bit  
error to the CPU).  
GBA, GAB  
SEL  
Output Enables for A or B Bus,  
Active LOW  
Select Pin for Feed-Through or Generate  
Mode, LOW for Generate Mode  
Independent Latch Enables (LEA and LEB) allow other  
permutations of generating/checking (see Function  
Table).  
LEA, LEB  
Latch Enables for A and B Latches,  
HIGH for Transparent Mode  
ERRA, ERRB Error Signals for Checking Generated  
Parity with Parity In, LOW if Error Occurs  
Function Table  
Inputs  
Operation  
GAB GBA SEL LEA LEB  
H
H
H
L
X
L
X
L
X
H
Busses A and B are 3-STATE.  
Generates parity from B[0:7] based on O/E (Note 1). Generated parity APAR.  
Generated parity checked against BPAR and output as ERRB.  
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity APAR. Generated  
parity checked against BPAR and output as ERRB. Generated parity also fed back  
through the A latch for generate/check as ERRA.  
H
H
H
L
L
L
L
H
H
X
X
H
L
H
H
Generates parity from B latch data based on O/E. Generated parity APAR.  
Generated parity checked against latched BPAR and output as ERRB .  
BPAR/B[0:7] APAR/A0:7] Feed-through mode. Generated parity checked  
against BPAR and output as ERRB.  
BPAR/B[0:7] APAR/A[0:7]  
Feed-through mode. Generated parity checked against BPAR and output as ERRB.  
Generated parity also fed back through the A latch for generate/check as ERRA.  
L
L
H
H
L
L
H
H
L
Generates parity for A[0:7] based on O/E. Generated parity BPAR. Generated  
parity checked against APAR and output as ERRA.  
H
Generates parity from A[0:7] based on O/E. Generated parity BPAR. Generated  
parity checked against APAR and output as ERRA. Generated parity also fed back  
through the B latch for generate/check as ERRB.  
L
L
H
H
L
L
X
L
Generates parity from A latch data based on O/E. Generated parity BPAR. Gen-  
erated parity checked against latched APAR and output as ERRA .  
H
H
APAR/A[0:7] BPAR/B[0:7]  
Feed-through mode. Generated parity checked against APAR and output as ERRA.  
APAR/A[0:7] BPAR/B[0:7]  
L
H
H
H
H
Feed-through mode. Generated parity checked against APAR and output as ERRA.  
Generated parity also fed back through the B latch for generate/check as ERRB.  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Note 1: O/E = ODD/EVEN  
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2
Functional Block Diagram  
AC Path  
A , APAR B , BPAR  
n
n
(B , BPAR A , APAR)  
n
n
FIGURE 1.  
A
BPAR  
n
(B APAR)  
n
FIGURE 2.  
3
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A
ERRA  
n
(B ERRB)  
n
FIGURE 3.  
O/E ERRA  
O/E ERRB  
FIGURE 4.  
O/E BPAR  
(O/E APAR)  
FIGURE 5.  
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4
APAR ERRA  
(BPAR ERRB)  
FIGURE 6.  
ZH, HZ  
FIGURE 7.  
ZL, LZ  
FIGURE 8.  
SEL BPAR  
(SEL APAR)  
FIGURE 9.  
5
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LEA BPAR, B[0:7]  
(LEB APAR, A[0:7])  
FIGURE 10.  
FIGURE 11.  
FIGURE 12.  
TS(H), TH(H)  
LEA APAR, A[0:7]  
(LEB BPAR, B[0:7])  
TS(L), TH(L)  
LEA APAR, A[0:7]  
(LEB BPAR, B[0:7])  
FIGURE 13.  
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6
Sink Current  
±300 mA  
140°C  
Absolute Maximum Ratings(Note 2)  
Junction Temperature (TJ)  
Supply Voltage (VCC  
)
0.5V to +7.0V  
DC Input Diode Current (IIK  
VI = −0.5V  
)
Recommended Operating  
Conditions  
20 mA  
+20 mA  
VI = VCC + 0.5V  
Supply Voltage (VCC  
Input Voltage (VI)  
)
4.5V to 5.5V  
0V to VCC  
DC Input Voltage (VI)  
0.5V to VCC + 0.5V  
DC Output Diode Current (IOK  
)
Output Voltage (VO)  
0V to VCC  
V
V
O = −0.5V  
20 mA  
+20 mA  
Operating Temperature (TA)  
Minimum Input Edge Rate V/t  
VIN from 0.8V to 2.0V  
40°C to +85°C  
125 mV/ns  
O = VCC + 0.5V  
DC Output Voltage (VO)  
DC Output Source  
0.5V to VCC + 0.5V  
VCC @ 4.5V, 5.5V  
or Sink Current (IO)  
±50 mA  
Note 2: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception, to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
±50 mA  
Storage Temperature (TSTG  
DC Latch-Up Source or  
)
65°C to +150°C  
DC Electrical Characteristics  
V
T
= +25°C  
T = −40°C to +85°C  
A
Symbol  
Parameter  
Units  
Conditions  
CC  
A
(V)  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
V
V
Minimum HIGH Level  
Input Voltage  
2.0  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
V
V
V
= 0.1V  
IH  
OUT  
1.5  
2.0  
0.8  
0.8  
4.4  
5.4  
or V 0.1V  
CC  
Maximum LOW Level  
Input Voltage  
1.5  
V
= 0.1V  
IL  
OUT  
1.5  
or V 0.1V  
CC  
Minimum HIGH Level  
Output Voltage  
4.49  
5.49  
I
= −50 µA  
OH  
OUT  
V
= V or V  
IN  
IL  
IH  
4.5  
5.5  
4.5  
5.5  
3.86  
4.86  
0.1  
3.76  
4.76  
0.1  
V
V
I
I
I
= −24 mA  
OH  
OH  
OUT  
= −24 mA (Note 3)  
V
Maximum LOW Level  
Output Voltage  
0.001  
0.001  
= 50 µA  
OL  
0.1  
0.1  
V
= V or V  
IN  
OL  
OL  
IL  
IH  
4.5  
5.5  
5.5  
0.36  
0.36  
±0.1  
0.44  
0.44  
±1.0  
V
I
I
= 24 mA  
= 24 mA (Note 3)  
I
I
Maximum Input  
µA  
µA  
V = V , GND  
I CC  
IN  
Leakage Current  
Maximum 3-STATE  
Leakage Current  
5.5  
±0.5  
±5.0  
V = V , V  
OZ  
I
IL  
IH  
V
= V , GND  
CC  
O
I
I
I
I
Maximum I /Input  
CC  
5.5  
5.5  
5.5  
5.5  
0.6  
1.5  
75  
mA  
mA  
mA  
µA  
V = V 2.1V  
CCT  
OLD  
OHD  
CC  
I
CC  
Minimum Dynamic  
Output Current (Note 4)  
Maximum Quiescent  
Supply Current  
V
V
V
= 1.65V Max  
OLD  
OHD  
75  
80.0  
= 3.85V Min  
8.0  
= V  
CC  
IN  
or GND  
Note 3: Maximum of 9 outputs loaded; thresholds on input associated with output under test.  
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.  
7
www.fairchildsemi.com  
AC Electrical Characteristics  
V
T
= +25°C  
= 50 pF  
T = −40°C to +85°C  
A
CC  
A
C
C = 50 pF  
L
Symbol  
Parameter  
(V)  
(Note 5)  
5.0  
Units  
ns  
Fig. No.  
L
Min  
Typ  
Max  
Min  
Max  
t
t
t
t
t
t
t
t
Propagation Delay  
A , B to B , A  
2.5  
7.5  
11.5  
2.5  
1.5  
2.5  
2.0  
12.0  
Figure 1  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
n
n
n
n
Propagation Delay  
5.0  
5.0  
5.0  
1.5  
2.5  
2.0  
6.0  
8.5  
8.0  
8.5  
9.0  
ns  
Figure 1  
Figure 2  
Figure 3  
APAR, BPAR to BPAR, APAR  
Propagation Delay  
12.0  
11.5  
12.5  
12.0  
ns  
A , B to BPAR, APAR  
n
n
Propagation Delay  
ns  
A , B to ERRA, ERRB  
n
n
t
t
Propagation Delay  
5.0  
5.0  
5.0  
5.0  
2.0  
2.5  
1.5  
1.5  
8.0  
8.0  
7.5  
6.5  
11.5  
11.5  
10.5  
9.0  
2.0  
2.5  
1.5  
1.5  
12.0  
12.0  
11.5  
9.5  
ns  
ns  
ns  
ns  
Figure 4  
Figure 5  
Figure 6  
Figure 9  
PLH  
PHL  
ODD/EVEN to ERRA, ERRB  
Propagation Delay  
t
t
PLH  
PHL  
ODD/EVEN to APAR, BPAR  
Propagation Delay  
t
t
PLH  
PHL  
APAR, BPAR to ERRA, ERRB  
Propagation Delay  
t
t
PLH  
PHL  
SEL to APAR, BPAR  
Propagation Delay  
t
t
t
t
t
t
5.0  
5.0  
5.0  
2.5  
2.0  
2.5  
7.0  
8.0  
8.0  
10.5  
11.5  
11.5  
2.5  
2.0  
2.5  
11.0  
12.0  
12.0  
ns  
ns  
ns  
Figure 10  
Figure 11  
Figure 10  
Figure 11  
Figure 12  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
LEB to A , B  
n
n
Propagation Delay  
LEA to APAR, BPAR  
Propagation Delay  
LEA, LEB to ERRA, ERRB  
Output Enable Time  
t
t
5.0  
5.0  
5.0  
5.0  
2.5  
1.5  
1.5  
1.5  
7.0  
6.0  
6.5  
6.5  
10.5  
9.0  
2.5  
1.5  
1.5  
1.5  
11.0  
9.5  
9.5  
9.5  
ns  
ns  
ns  
ns  
Figure 7  
Figure 8  
PZH  
PZL  
GBA or GAB to A , B  
n
n
t
t
Output Enable Time  
Figure 7  
Figure 8  
PZH  
PZL  
GBA or GAB to BPAR or APAR  
Output Disable Time  
t
t
9.5  
Figure 7  
Figure 8  
PHZ  
PHL  
GBA or GAB to A , B  
n
n
t
t
Output Disable Time  
9.5  
Figure 7  
Figure 8  
PHZ  
PLZ  
GBA or GAB to BPAR, APAR  
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.  
AC Operating Requirements  
V
T
= +25°C  
T = −40°C to +85°C  
A
CC  
A
C
= 50 pF  
C = 50 pF  
L
Symbol  
Parameter  
(V)  
Units  
Fig. No.  
L
(Note 6)  
Guaranteed Minimum  
3.0  
t
Setup Time, HIGH or LOW  
5.0  
3.0  
1.5  
4.0  
ns  
ns  
ns  
Figure 11  
Figure 12  
Figure 11  
Figure 12  
Figure 13  
S
A , B , PAR to LEA, LEB  
n
n
t
t
Hold Time, HIGH or LOW  
A , B , PAR to LEA, LEB  
5.0  
5.0  
1.5  
4.0  
H
n
n
Pulse Width for LEB, LEA  
W
Note 6: Voltage Range 5.0 = 5.0V ± 0.5V.  
Capacitance  
Symbol  
Parameter  
Typ  
4.5  
Units  
pF  
Conditions  
C
Input Capacitance  
V
= 5.0V  
= 5.0V  
IN  
CC  
CC  
C
Power Dissipation Capacitance  
210  
pF  
V
PD  
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8
Physical Dimensions inches (millimeters) unless otherwise noted  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square  
Package Number V28A  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  

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