74ACTQ16541_05 [FAIRCHILD]
16-Bit Buffer/Line Driver with 3-STATE Outputs; 16位与3态输出缓冲器/线路驱动器
| 型号： | 74ACTQ16541_05 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1991
Revised May 2005
74ACTQ16541
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ Utilizes Fairchild FACT Quiet Series technology
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte
■ 16-bit version of the ACTQ541
The ACTQ16541 utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
■ Outputs source/sink 24 mA
■ Additional specs for Multiple Output Switching
■ Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16541SSC
74ACTQ16541MTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
O0–O15
Inputs
Outputs
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation
© 2005 Fairchild Semiconductor Corporation
DS010936
www.fairchildsemi.com
Functional Description
Truth Tables
The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dent of the other. The control pins can be shorted together
to obtain full 16-bit operation. The 3-STATE outputs are
controlled by an Output Enable (OEn) input for each byte.
Inputs
Outputs
O0–O7
OE1
OE2
I0–I7
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
When OEn is LOW, the outputs are in 2-state mode. When
OEn is HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the
inputs.
Inputs
OE4
Outputs
O8–O15
OE3
I8–I15
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
0.5V to +7.0V
DC Input Diode Current (IIK
VI = 0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
20 mA
Input Voltage (VI)
VI = VCC + 0.5V
+20 mA
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
VO 0.5V
)
Operating Temperature (TA)
40 C to +85 C
125 mV/ns
=
20 mA
+20 mA
Minimum Input Edge Rate ( V/ t)
VO = VCC + 0.5V
V
IN from 0.8V to 2.0V
DC Output Voltage (VO)
0.5V to VCC + 0.5V
50 mA
VCC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
50 mA
Storage Temperature
65 C to +150 C
DC Electrical Characteristics
V
T
= +25 C
T = 40 C to +85 C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
Minimum HIGH
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
OUT
IH
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or V
0.1V
CC
V
Maximum LOW
Input Voltage
1.5
V
= 0.1V
IL
OUT
1.5
or V
0.1V
50
CC
V
Minimum HIGH
Output Voltage
4.49
5.49
I
=
OUT
A
OH
V
= V or V
IL IH
IN
OH
OH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
A
I
I
I
=
=
24 mA
24 mA (Note 2)
V
Maximum LOW
Output Voltage
0.001
0.001
= 50 A
OUT
OL
0.1
0.1
V
= V or V
IL
IN
OL
OL
IH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
= 24 mA
= 24 mA (Note 2)
I
Maximum 3-STATE
V = V , V
OZ
I
IL
IH
5.5
0.5
0.1
5.0
Leakage Current
V
= V , GND
O
CC
I
I
I
I
I
Maximum Input Leakage Current
5.5
5.5
5.5
1.0
1.5
80.0
75
A
mA
A
V = V , GND
IN
I
CC
CC
Maximum I /Input
CC
0.6
V = V
2.1V
CCT
CC
I
Max Quiescent Supply Current
Minimum Dynamic
8.0
V
V
V
= V or GND
CC
IN
mA
mA
= 1.65V Max
= 3.85V Min
OLD
OHD
OLD
OHD
5.5
5.0
5.0
5.0
5.0
Output Current (Note 3)
Quiet Output
75
V
V
V
V
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
OLP
OLV
OHP
OHV
0.5
0.5
0.8
1.0
V
V
V
V
Maximum Dynamic V
Quiet Output
OL
Minimum Dynamic V
Maximum
OL
V
+
V
+
OH
OH
1.0
1.5
Overshoot
Minimum
V
1.0
V
1.8
OH
OH
V
Droop
CC
V
V
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.0
5.0
1.7
1.2
2.0
0.8
V
V
IHD
ILD
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n 1) input switching 0V to 3V. Input under test switching 3V to threshold (V ).
ILD
3
www.fairchildsemi.com
AC Electrical Characteristics
V
T
= +25 C
= 50 pF
T =
A
40 C to +85 C
C = 50 pF
L
CC
A
C
Symbol
Parameter
(V)
Units
L
(Note 8)
Min
3.0
2.5
2.6
2.7
2.7
2.4
Typ
5.2
4.8
5.0
5.4
5.6
5.2
Max
7.3
7.3
7.4
8.0
8.3
7.9
Min
3.0
2.5
2.6
2.7
2.7
2.4
Max
t
t
t
t
t
t
Propagation Delay
7.8
7.8
7.9
8.5
8.7
8.4
PLH
5.0
5.0
5.0
ns
ns
ns
Data to Output
PHL
PZH
PZL
PHZ
PLZ
Output Enable Time
Output Disable Time
Note 8: Voltage Range 5.0 is 5.0V 0.5V.
Extended AC Electrical Characteristics
T
=
40 C to +85 C
= 50 pF
A
C
T
=
40 C to +85 C
= 250 pF
L
L
A
V
C
Symbol
Parameter
16 Outputs Switching
(Note 11)
Units
CC
(V)
(Note 12)
Min Max
(Note 9)
Min
4.0
3.4
3.3
3.3
4.3
3.8
Typ
Max
11.6
9.6
t
Propagation Delay,
5.6
4.8
14.3
13.1
PLH
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
Data to Output
PHL
PZH
PZL
Output Enable Time
10.1
10.0
10.1
9.6
(Note 13)
Output Disable Time
PHZ
PLZ
(Note 14)
Pin to Pin Skew, HL
Data to Output
OSHL
1.2
2.5
4.3
(Note 10)
t
Pin to Pin Skew, LH
Data to Output
OSLH
(Note 10)
t
Pin to Pin Skew,
LH/HL Data to Output
OST
(Note 10)
Note 9: Voltage Range 5.0 is 5.0V 0.5V.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t ), LOW-to-HIGH (t ), or any combination switching LOW-to-HIGH and/or HIGH-
OSHL
OSLH
to-LOW (t
).
OST
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC Network (500 , 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
Conditions
C
C
V
V
= 5.0V
= 5.0V
IN
CC
CC
pF
PD
www.fairchildsemi.com
4
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
V
OLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50 coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLVon the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case for active and enable transition.
500
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50 coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note A: V
and V
are measured with respect to ground reference.
OHV
OLP
Note B: Input pulses have the following characteristics: f = 1 MHz,
t
= 3 ns, t = 3 ns, skew 150 ps.
f
r
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
7
www.fairchildsemi.com
相关型号：
74ACTQ16646CW
Registered Bus Transceiver, ACT Series, 2-Func, 8-Bit, True Output, CMOS, DIE
FAIRCHILD
74ACTQ16646MSAJ
ACT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, EIAJ TYPE 2, SSOP-56
TI
©2020 ICPDF网 联系我们和版权申明