74ACTQ245MTCX_NL [FAIRCHILD]
Quiet Series⑩ Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs; 安静的系列？八路双向收发器3 -STATE输入/输出
| 型号： | 74ACTQ245MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Series⑩ Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs |
| 文件： | 总11页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1989
Revised March 2005
74ACQ245 • 74ACTQ245
Quiet Series¥ Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
Features
■ ICC and IOZ reduced by 50%
The ACQ/ACTQ245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus-
oriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirec-
tional transceiver. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard ACT245
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Ordering Code:
Package
Order Number
Package Description
Number
74ACQ245SC
74ACQ245SJ
M20B
M20D
N20A
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ245PC
74ACTQ245SC
74ACTQ245SJ
74ACTQ245QSC
74ACTQ245MSA
74ACTQ245MTC
MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
MSA20
MTC20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ245MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACTQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010236
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
Transmit/Receive Input
T/R
A0–A7
B0–B7
Side A 3-STATE Inputs or 3-STATE Outputs
Side B 3-STATE Inputs or 3-STATE Outputs
Truth Table
Inputs
Outputs
OE
L
T/R
L
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
L
H
Logic Symbols
H
X
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
IEEE/IEC
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC 0.5V
ACTQ
DC Input Voltage (VI)
0.5V to VCC 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
VO 0.5V
)
0V to VCC
20 mA
20 mA
Operating Temperature (TA)
Minimum Input Edge Rate V/ t
ACQ Devices
40 C to 85 C
VO VCC 0.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
50 mA
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate V/ t
ACTQ Devices
125 mV/ ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
65 C to 150 C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
300 mA
140 C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics for ACQ
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
1.5
2.1
2.1
3.15
3.85
0.9
V
0.1V
IH
OUT
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
0.1V
CC
Maximum LOW Level
Input Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V
CC
Minimum HIGH Level
Output Voltage
OH
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
24 mA
V
V
24 mA (Note 3)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
OL
IL
3.0
4.5
5.5
5.5
0.36
0.36
0.36
0.1
0.44
0.44
0.44
1.0
I
I
I
12 mA
24 mA
V
A
24 mA (Note 3)
V , GND
CC
I
Maximum Input
V
IN
I
(Note 5)
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
I
5.5
5.5
5.5
75
75
mA
mA
A
V
V
V
1.65V Max
3.85V Min
OLD
OLD
OHD
IN
I
OHD
I
4.0
0.3
40.0
V
CC
CC
(Note 5)
or GND
V (OE) V , V
IL IH
I
Maximum I/O
OZT
I
Leakage Current
5.5
3.0
A
V
V
V
, GND
CC
I
V
, GND
CC
O
3
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DC Electrical Characteristics for ACQ (Continued)
V
T
25 C
T
40 C to 85 C
Guaranteed Limits
CC
A
A
Symbol
Parameter
Quiet Output
Units
Conditions
(V)
Typ
V
V
V
V
Figure 1, Figure 2
(Note 6)(Note 7)
Figure 1, Figure 2
(Note 6)(Note 7)
OLP
5.0
1.1
1.5
V
V
V
V
Maximum Dynamic V
Quiet Output
OL
OLV
IHD
ILD
5.0
5.0
5.0
0.6
3.1
1.9
1.2
3.5
1.5
Minimum Dynamic V
OL
Minimum HIGH Level
(Note 6)(Note 8)
(Note 6)(Note 8)
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
Note 6: DIP package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND.
Note 8: Max number of Data Inputs (n) switching. (n 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V ),
ILD
0V to threshold (V ), f 1 MHz.
IHD
DC Electrical Characteristics for ACTQ
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
IH
OUT
V
V
V
Input Voltage
1.5
2.0
0.8
0.8
4.4
5.4
or V
0.1V
0.1V
0.1V
50
CC
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
A
OH
OUT
V
V or V
IL IH
IN
OH
OH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
I
I
24 mA
24 mA (Note 9)
V
V
V
Maximum LOW Level
Output Voltage
0.001
0.001
OL
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
5.5
5.5
0.36
0.36
0.1
0.44
0.44
1.0
V
I
I
24 mA
24 mA (Note 9)
I
I
Maximum Input Leakage Current
Maximum 3-STATE
A
A
V
V
V
V
V
V
V
V
V
, GND
IN
I
CC
IL
0.3
3.0
, V
OZT
I
IH
Leakage Current
V
, GND
O
I
CC
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
A
V
2.1V
CCT
OLD
OHD
CC
CC
Minimum Dynamic
1.65V Max
3.85V Min
OLD
OHD
IN
Output Current (Note 10)
Maximum Quiescent Supply Current
Quiet Output
75
4.0
1.5
40.0
V
or GND
CC
V
Figure 1, Figure 2
(Note 11)(Note 12)
Figure 1, Figure 2
(Note 11)(Note 12)
(Note 11)(Note 13)
(Note 11)(Note 13)
OLP
5.0
5.0
1.1
0.6
V
V
Maximum Dynamic V
Quiet Output
OL
V
OLV
1.2
Minimum Dynamic V
OL
V
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.0
5.0
1.9
1.2
2.2
0.8
V
V
IHD
ILD
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
Note 11: DIP package.
Note 12: Max number of outputs defined as (n). n 1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 13: Max number of Data Inputs (n) switching. (n 1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V ),
ILD
0V to threshold (V ) f 1 MHz.
IHD
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4
AC Electrical Characteristics for ACQ
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 14)
3.3
Units
L
Min
2.0
1.5
3.0
2.0
1.0
1.0
Typ
Max
10.0
6.5
t
t
t
t
t
t
t
t
Propagation Delay
7.5
5.0
8.5
6.0
8.5
7.5
1.0
0.5
2.0
1.5
3.0
2.0
1.0
1.0
10.5
7.0
PHL
ns
ns
ns
ns
Data to Output
5.0
PLH
Output Enable Time
3.3
13.0
8.5
13.5
9.0
PZL
5.0
PZH
PHZ
PLZ
Output Disable Time
3.3
14.5
9.5
15.0
10.0
1.5
5.0
Output to Output Skew (Note 15)
Data to Output
3.3
1.5
OSHL
OSLH
5.0
1.0
1.0
Note 14: Voltage Range 5.0 is 5.0V 0.5V
Voltage Range 3.3 is 3.3V 0.3V
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
AC Electrical Characteristics for ACTQ
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
Typ
C
L
Symbol
Parameter
(V)
(Note 16)
5.0
Units
L
Min
Max
t
Propagation Delay
1.5
5.5
7.0
1.5
7.5
ns
PHL
t
t
t
t
t
Data to Output
PLH
, t
Output Enable Time
Output Disable Time
Output to Output Skew (Note 17)
Data to Output
5.0
5.0
5.0
2.0
1.0
7.0
8.0
0.5
9.0
10.0
1.0
2.0
1.0
9.5
10.5
1.0
ns
ns
ns
PZL PZH
, t
PHZ PLZ
OSHL
OSLH
Note 16: Voltage Range 5.0 is 5.0V 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
Capacitance
Symbol
Parameter
Input Capacitance
Typ
4.5
Units
Conditions
C
C
C
pF
pF
pF
V
V
V
OPEN
5.0V
IN
CC
CC
CC
Input/Output Capacitance
15
I/O
PD
Power Dissipation Capacitance
80.0
5.0V
5
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50 coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50 coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 18: V
and V
are measured with respect to ground reference.
OLP
OHV
Note 19: Input pulses have the following characteristics: f 1 MHz, t
r
3 ns, t 3 ns, skew 150 ps.
f
FIGURE 2. Simultaneous Switching Test Circuit
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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