74ACTQ543SC [FAIRCHILD]
Quiet Series⑩ Octal Registered Transceiver with 3-STATE Outputs; 安静Series⑩八路寄存收发器与3态输出
| 型号： | 74ACTQ543SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Series⑩ Octal Registered Transceiver with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1990
Revised August 2000
74ACQ543• 74ACTQ543
Quiet Series Octal Registered Transceiver
with 3-STATE Outputs
General Description
Features
■ Guaranteed simultaneous switching noise level and
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ 8-bit octal latched transceiver
■ Separate controls for data flow in each direction
■ Back-to-back registers for storage
■ Outputs source/sink 24 mA
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
■ 300 mil slim PDIP/SOIC
Ordering Code:
Order Number Package Number
Package Description
74ACQ543SC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACQ543SPC
74ACTQ543SC
74ACTQ543QSC
74ACTQ543SPC
M24B
MQA24
N24C
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010154
www.fairchildsemi.com
Logic Symbols
Functional Description
The ACQ/ACTQ543 contains two sets of eight D-type
latches, with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB) input must be LOW in order to enter data
from A0–A7 or take data from B0–B7, as indicated in the
Data I/O Control Table. With CEAB LOW, a LOW signal on
the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition
of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change with the A inputs. With
CEAB and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA inputs
IEEE/IEC
Data I/O Control Table
Inputs
Latch Status Output Buffers
CEAB LEAB OEAB
H
X
L
X
H
L
X
X
X
H
L
Latched
Latched
Transparent
—
High Z
—
—
X
X
High Z
Driving
L
X
—
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage VCC
ACQ
−20 mA
+20 mA
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
DC Latch-up Source or
Sink Current
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
± 300 mA
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics for ACQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
IOH = −12 mA
V
V
IOH = −24 mA
IOH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
IOUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
IOL = 12 mA
V
IOL = 24 mA
IOL = 24 mA (Note 2)
IIN
Maximum Input
VI = VCC
,
5.5
± 0.1
± 1.0
µA
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
GND
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
IOHD
ICC
−75
V
V
5.5
8.0
80.0
µA
(Note 4)
IOZT
or GND
Maximum I/O
VI (OE) = VIL, VIH
VI = VCC, GND
Leakage Current
5.5
± 0.6
± 6.0
µA
VO = VCC, GND
3
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DC Electrical Characteristics for ACQ (Continued)
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
Symbol
Parameter
Quiet Output
Units
Conditions
Figures 1, 2
Typ
Guaranteed Limits
VOLP
5.0
5.0
5.0
5.0
1.1
1.5
−1.2
3.5
V
V
V
V
Maximum Dynamic VOL
Quiet Output
(Note 5)(Note 6)
Figures 1, 2
VOLV
VIHD
VILD
−0.6
3.1
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
(Note 5)(Note 6)
(Note 5)(Note 7)
(Note 5)(Note 7)
1.9
1.5
Note 2: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
VIH
V
V
V
1.5
Maximum LOW Level
Input Voltage
1.5
V
VIL
1.5
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
VOH
V
IN = VIL or VIH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
IOH = −24 mA
I
I
OH = −24 mA (Note 8)
OUT = 50 µA
Maximum LOW Level
Output Voltage
0.001
0.001
0.1
0.1
VOL
VIN = VIL or VIH
4.5
5.5
5.5
0.36
0.36
± 0.1
0.44
0.44
± 1.0
IOL = 24 mA
IOL = 24 mA (Note 8)
VI = VCC, GND
V(OE) = VIL, VIH
IIN
Maximum Input Leakage Current
Maximum I/O
µA
µA
IOZT
5.5
±0.6
6.0
Leakage Current
V
O = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
5.5
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
µA
VI = VCC − 2.1V
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 9)
Maximum Quiescent Supply Current
Quiet Output
−75
80.0
8.0
1.5
Figures 1, 2
VOLP
5.0
5.0
1.1
V
V
Maximum Dynamic VOL
Quiet Output
(Note 10)(Note 11)
Figures 1, 2
VOLV
VIHD
VILD
−0.6
−1.2
Minimum Dynamic VOL
(Note 10)(Note 11)
Minimum HIGH Level Dynamic
Input Voltage
5.0
5.0
1.9
1.2
2.2
0.8
V
V
(Note 10)(Note 12)
(Note 10)(Note 12)
Maximum LOW Level Dynamic
Input Voltage
Note 8: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: DIP package
Note 11: Max number of outputs defined as (n). (n−1) Data Inputs are driven 0V to 3V, one output @ GND.
Note 12: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f =1 MHz.
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4
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 13)
3.3
Units
Min
1.5
1.5
Typ
8.0
5.0
Max
11.0
7.0
Min
tPLH
Propagation Delay
1.5
1.5
11.5
7.5
tPHL
Transparent Mode
5.0
ns
ns
An to Bn or Bn to An
tPLH
tPHL
tPZH
tPZL
Propagation Delay
3.3
5.0
1.5
1.5
9.0
6.0
12.5
8.0
1.5
1.5
13.0
8.5
LEBA, LEAB to An, Bn
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output to Output
3.3
5.0
1.5
1.5
10.5
7.0
15.0
9.5
1.5
1.5
15.5
10.0
ns
tPHZ
tPLZ
3.3
5.0
3.3
5.0
1.0
1.0
8.0
5.0
1.0
0.5
11.0
7.0
1.5
1.0
1.0
1.0
11.5
7.5
1.5
1.0
ns
ns
tOSHL
tOSLH
Skew (Note 14)
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for AC
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
C
Symbol
Parameter
(V)
(Note 15)
3.3
Units
ns
Typ
tS
Setup Time, HIGH or LOW
3.0
3.0
1.5
4.0
An or Bn to LEBA or LEAB
5.0
tH
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
Latch Enable
3.3
1.5
4.0
ns
5.0
tW
3.3
ns
Pulse Width, LOW
5.0
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.0V ± 0.3V
5
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AC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
ns
(Note 16)
Min
Typ
Max
Min
tPLH
Propagation Delay
tPHL
Transparent Mode
An to Bn or Bn to An
Propagation Delay
LEBA, LEAB
5.0
5.0
5.0
1.5
5.5
6.5
8.0
7.5
1.5
1.5
1.5
1.0
8.0
9.0
tPLH
tPHL
1.5
1.5
1.0
8.5
ns
to An, Bn
tPZH
tPZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output to Output
10.0
10.5
ns
tPHZ
tPLZ
5.0
5.0
5.5
0.5
7.5
1.0
8.0
1.0
ns
ns
tOSHL
tOSLH
Skew (Note 17)
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACTQ
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
C
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 18)
Typ
Guaranteed Minimum
tS
tS
tW
Setup Time, HIGH or LOW
An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW
5.0
5.0
5.0
3.0
1.5
4.0
3.0
ns
ns
ns
1.5
4.0
A
n or Bn to LEBA or LEAB
Latch Enable
Pulse Width, LOW
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
CC = OPEN
CC = 5.0V
CIN
Input Capacitance
V
CPD
Power Dissipation Capacitance
70.0
pF
V
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6
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability on the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 19: VOHVand VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics:
r = 3 ns, tf = 3 ns, skew < 150 ps.
f = 1 MHz,
t
FIGURE 2. Simultaneous Switching Test Circuit
7
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA24
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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