74ACTQ574SJX [FAIRCHILD]
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20;
| 型号： | 74ACTQ574SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20 总线驱动器 总线收发器 触发器 逻辑集成电路 光电二极管 |
| 文件： | 总10页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1990
Revised November 1999
74ACQ574 • 74ACTQ574
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
Features
■ ICC and IOZ reduced by 50%
The ACQ/ACTQ574 is a high-speed, low-power octal D-
type flip-flop with a buffered Common Clock (CP) and a
buffered common Output Enable (OE). The information
presented to the D inputs is stored in the flip-flops on the
LOW-to-HIGH clock (CP) transition.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
ACQ/ACTQ574 utilizes FACT Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
■ Functionally identical to the ACQ/ACTQ374
■ 3-STATE outputs drive bus lines or buffer memory
address registers
The ACQ/ACTQ574 is functionally identical to the
ACTQ374 but with different pin-out.
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard AC/ACT574
Ordering Code:
Order Number Package Number
Package Description
74ACQ574SC
74ACQ574SJ
74ACQ574PC
74ACTQ574SC
74ACTQ574SJ
74ACTQ574PC
M20B
M20D
N20A
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010634
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Logic Symbols
Functional Description
The ACQ/ACTQ574 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D-type inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the state of
the flip-flops.
IEEE/IEC
Function Table
Inputs
OE CP
Internal Outputs
Function
D
Q
ON
H
H
H
H
L
H
H
L
H
L
NC
NC
L
Z
Z
Hold
Hold
Load
Load
Z
H
L
H
Z
L
L
Data Available
L
H
L
H
H
Data Available
L
H
H
NC
NC
NC
NC
No Change in Data
No Change in Data
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
±300 mA
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics for ACQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
5.5
±0.1
±1.0
µA
VI = VCC, GND
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
IOHD
ICC
−75
5.5
4.0
40.0
µA
(Note 4)
IOZ
or GND
Maximum 3-STATE
Leakage Current
VI (OE) = VIL, VIH
VI = VCC, GND
5.5
±0.25
±2.5
µA
VO = VCC, GND
3
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DC Electrical Characteristics for ACQ (Continued)
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
Symbol
VOLP
Parameter
Quiet Output
Units
Conditions
Typ
Guaranteed Limits
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
5.0
5.0
5.0
5.0
1.1
−0.6
3.1
1.5
V
V
V
V
Maximum Dynamic VOL
Quiet Output
VOLV
VIHD
VILD
−1.2
3.5
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
(Note 5)(Note 7)
(Note 5)(Note 7)
1.9
1.5
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
Note 5: DIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 7: Maximum number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (VILD), 0V to threshold (VIHD). f = 1 MHz.
DC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.85
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH= −24 mA
OH= −24 mA (Note 8)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
I
I
OL = 24 mA
OL = 24 mA (Note 8)
IIN
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
µA
µA
VI = VCC, GND
VI = VIL, VIH
IOZ
5.5
±0.25
±2.5
V
O = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
Output Current (Note 9)
Maximum Quiescent
Supply Current
−75
5.5
5.0
5.0
5.0
5.0
4.0
1.5
40.0
µA
V
or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
Figure 1, Figure 2
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
1.1
−0.6
1.9
Maximum Dynamic VOL
Quiet Output
−1.2
2.2
V
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
(Note 10)(Note 12)
(Note 10)(Note 12)
1.2
0.8
V
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: DIP package.
Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
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4
DC Electrical Characteristics for ACTQ (Continued)
Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics for ACQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 13)
3.3
Units
Min
75
Typ
Max
Min
fMAX
Maximum Clock
70
85
MHz
ns
Frequency
5.0
90
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
CP to On
3.3
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
5.0
Output Enable Time
3.3
5.0
3.3
5.0
3.3
5.0
3.0
2.0
1.0
1.0
9.5
6.5
9.5
8.0
1.0
0.5
13.0
8.5
3.0
2.0
1.0
1.0
13.5
9.0
ns
Output Disable Time
14.5
9.5
15.0
10.0
1.5
ns
Output to Output Skew (Note 14)
CP to On
1.5
ns
1.0
1.0
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACQ
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
C
C
L = 50 pF
Symbol
Parameter
(V)
(Note 15)
3.3
Units
Typ
0
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
3.0
3.0
1.5
1.5
4.0
4.0
3.0
3.0
1.5
1.5
4.0
4.0
ns
ns
ns
5.0
0
tH
Hold Time, HIGH or LOW
3.3
0
Dn to CP
5.0
0
tW
CP Pulse Width,
HIGH or LOW
3.3
2.0
2.0
5.0
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Electrical Characteristics for ACTQ
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 16)
5.0
Units
Min
Typ
Max
Min
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
tOSLH
Maximum Clock Frequency
Propagation Delay
85
80
MHz
ns
5.0
5.0
5.0
5.0
2.0
2.0
1.0
7.0
7.0
8.0
0.5
9.0
9.0
2.0
9.5
9.5
CP to On
Output Enable
2.0
1.0
ns
ns
ns
Time
Output Disable
10.0
1.0
10.5
1.0
Time
Output to Output Skew (Note 17)
CP to On
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5
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AC Operating Requirements for ACTQ
VCC
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 18)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
0
3.0
1.5
4.0
3.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
0
1.5
4.0
Dn to CP
tW
CP Pulse Width,
HIGH or LOW
2.0
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
40.0
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case for active and enable transition. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 19: VOHV and VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
7
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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