74ACTQ821_00 [FAIRCHILD]
Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs; 宁静系列10位D型触发器带3态输出
| 型号： | 74ACTQ821_00 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1990
Revised September 2000
74ACTQ821
Quiet Series 10-Bit D-Type Flip-Flop
with 3-STATE Outputs
General Description
Features
■ Guaranteed simultaneous switching noise level and
The ACTQ821 is a 10-bit D-type flip-flop with non-inverting
3-STATE outputs arranged in a broadside pinout. The
ACTQ821 utilizes Fairchild’s Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Non-inverting 3-STATE outputs for bus interfacing
■ 4 kV minimum ESD immunity
features
■ Outputs source/sink 24 mA
Ordering Code:
Order Number Package Number
Package Description
74ACTQ821SC
74ACTQ821SPC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Data Inputs
Data Outputs
D0–D9
O0–O9
OE
Output Enable Input
Clock Input
CP
FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010686
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Functional Description
Function Table
The ACTQ821 consists of ten-bit D-type edge-triggered
flip-flops. The buffered Clock (CP) and buffered Output
Enable (OE) are common to all flip-flops. The flip-flops will
store the state of their individual D inputs that meet the
setup and hold time requirements on the LOW-to-HIGH CP
transition. With OE LOW the contents of the flip-flops are
available at the outputs. When OE is HIGH the outputs go
to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Inputs
CP
Internal
Outputs
Function
OE
H
D
L
Q
L
O
Z
Z
L
High Z
High Z
Load
H
H
L
H
L
L
L
H
H
H
Load
The ACTQ821 is functionally and pin compatible with the
AM29821.
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
− 0.5V to + 7.0V
DC Input Diode Current (IIK
VI = − 0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
− 20 mA
+ 20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
− 0.5V to VCC + 0.5V
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
Minimum Input Edge Rate ∆V/∆t
VIN from 0.8V to 2.0V
− 40°C to + 85°C
DC Output Diode Current (IOK
)
V
V
O = − 0.5V
− 20 mA
+ 20 mA
125 mV/ns
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
− 0.5V to VCC + 0.5V
V
CC @ 4.5V, 5.5V
or Sink Current (IO)
± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
DC Latch-Up Source
or Sink Current
)
− 65°C to + 150°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
± 300 mA
140°C
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics
VCC
T
A = + 25°C
TA = − 40°C to + 85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
Input Voltage
1.5
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = − 50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = − 24 mA
OH = − 24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
VI = VCC,
5.5
5.5
±0.1
±0.5
±1.0
±5.0
µA
µA
Leakage Current
GND
IOZ
Maximum 3-STATE
Leakage Current
VI = VIL, VIH
VO = VCC, GND
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
−75
5.5
5.0
5.0
5.0
5.0
8.0
1.5
80.0
µA
V
or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
1.1
− 0.6
1.9
Maximum Dynamic VOL
Quiet Output
− 1.2
2.2
V
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
(Note 4)(Note 6)
(Note 4)(Note 6)
1.2
0.8
V
3
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DC Electrical Characteristics (Continued)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Maximum number of data inputs (n) switching. (n−1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
VCC
T
A = + 25°C
T
A = − 40°C to + 85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 7)
Min
Typ
Max
Min
fMAX
Maximum Clock
5.0
5.0
5.0
5.0
5.0
120
110
2.5
2.5
1.0
MHz
ns
Frequency
tPLH
tPHL
tPZH
tPZL
Propagation Delay
CP to On
3.0
3.0
1.0
6.5
7.5
6.5
0.5
9.5
10.5
8.5
10.5
11.5
9.0
Output Enable Time
OE to On
ns
tPHZ
tPLZ
tOSLH
tOSHL
Output Disable Time
OE to On
ns
Output to Output Skew
CP to On (Note 8)
1.0
1.0
ns
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements
VCC
TA = + 25°C
TA = − 40°C to + 85°C
CL = 50 pF
CL = 50 pF
Symbol
Parameter
(V)
Units
(Note 9)
Typ
Guaranteed Minimum
tS
tH
tH
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
3.0
3.0
ns
ns
ns
Hold Time, HIGH or LOW
1.5
4.5
1.5
5.5
Dn to CP
CP Pulse Width
HIGH or LOW
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
CC = OPEN
CC = 5.0V
CIN
Input Capacitance
V
CPD
Power Dissipation Capacitance
55.0
pF
V
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4
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level VIH until the
output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 10: VOHV and VOLP are measured with respect to ground reference.
Note 11: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
5
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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instructions for use provided in the labeling, can be rea-
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user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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