74ALVC162374T [FAIRCHILD]
Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in Outputs; 低电压16位D型触发器具有3.6V容限输入和输出，并26з系列电阻的输出
| 型号： | 74ALVC162374T |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in Outputs |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2001
Revised October 2001
74ALVC162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in Outputs
General Description
Features
The ALVC162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
■ 1.65V–3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ 26Ω series resistors in outputs
■ tPD (CLK to On)
3.9 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
9.6 ns max for 1.65V to 1.95V VCC
The ALVC162374 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers and
bus transceivers/transmitters.
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
The 74ALVC162374 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Descriptions
74ALVC162374T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
Inputs
I0–I15
O0–O15
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500688
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Connection Diagram
Truth Tables
Inputs
OE1
Outputs
O0–O7
CP1
I0–I7
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
H
L
= HIGH Voltage Level
= LOW Voltage Level
X
Z
O
= Immaterial (HIGH or LOW, inputs may not float)
= High Impedance
0 = Previous O0 before HIGH-to-LOW of CP
Functional Description
The 74ALVC162374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The device is byte controlled with each byte function-
ing identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each flip-
flop will store the state of their individual I inputs that meet
the setup and hold time requirements on the LOW-to-HIGH
Clock (CPn) transition. With the Output Enable (OEn) LOW,
the contents of the flip-flops are available at the outputs.
When OEn is HIGH, the outputs go to the high impedance
state. Operations of the OEn input does not affect the state
of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 3)
−0.5V to VCC +0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x VCC
0.7
V
V
0.8
VOH
I
I
I
I
OH = −100 µA
OH = −2 mA
OH = −4 mA
OH = −6 mA
VCC - 0.2
1.2
1.9
1.7
2.4
2
2.3
2.3
3
I
I
I
I
I
I
OH = −8 mA
OH = −12 mA
OL = 100 µA
OL = 2 mA
2.7
3.0
2
VOL
LOW Level Output Voltage
1.65 - 3.6
1.65
0.2
0.45
0.4
OL = 4 mA
2.3
OL = 6 mA
2.3
0.55
0.55
0.6
V
3
I
I
OL = 8 mA
2.7
OL = 12 mA
3
0.8
II
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
3.6
±5.0
±10
40
µA
µA
µA
µA
IOZ
ICC
∆ICC
3.6
VI = VCC or GND, IO = 0
IH = VCC − 0.6V
3.6
V
3 - 3.6
750
3
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AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
C
L = 50 pF
CL = 30 pF
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
V
CC = 2.5V ± 0.2V
VCC = 1.8V ± 0.15V
Min
Max
Min
Max
Min
Max
Min
Max
fMAX
PHL, tPL
Maximum Clock Frequency
Propagation Delay
Bus to Bus
250
200
200
100
ns
ns
t
1.3
3.9
1.5
5.3
1.0
4.8
1.5
9.6
tPZL, tPZH
PLZ, tPHZ
Output Enable Time
Output Disable Time
Pulse Width
1.3
1.3
1.5
1.5
1.0
4.4
4.5
1.5
1.5
1.5
1.5
1.0
5.9
4.9
1.0
1.0
1.5
1.5
1.0
5.4
4.4
1.5
1.5
4.0
2.5
1.0
9.8
7.9
ns
ns
ns
ns
ns
t
tW
tS
Setup Time
tH
Hold Time
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
VI = 0V or VCC
VI = 0V or VCC
3.3
3.3
3.3
2.5
6
7
pF
pF
COUT
CPD
Outputs Enabled f = 10 MHz, CL = 50 pF
20
20
pF
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
VOL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.3V
V
OH − 0.15V
V
OH − 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
REC Waveforms
t
5
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Body Width
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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