74ALVC162835MTD [FAIRCHILD]
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| 型号： | 74ALVC162835MTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 总线驱动器 |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
Revised February 2002
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26Ω Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Features
■ Compatible with PC100 DIMM module specifications
■ 1.65V to 3.6V VCC specifications provided
■ 3.6V tolerant inputs and outputs
■ 26Ω series resistors in outputs
■ tPD (CLK to On)
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Outputs (On) on
5.4 ns max for 3.0V to 3.6V VCC
6.3 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
■ Power-off high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Latchup conforms to JEDEC JED78
■ ESD performance:
The ALVC162835 is designed with 26Ω series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
Human body model > 2000V
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
Machine model >200V
Note 1: To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pulldown resistor; the minimum
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Package
Order Number
Package Description
Number
74ALVC162835T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS500646
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
LE
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
CLK
I
1 - I18
Data Inputs
O1 - O18
3-STATE Outputs
Truth Table
Inputs
CLK
Outputs
On
OE
LE
In
H
L
L
L
L
L
L
X
H
H
L
X
X
X
↑
X
L
Z
L
H
L
H
L
H
L
↑
H
X
X
L
H
L
O0 (Note 2)
L
O0 (Note 3)
H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
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2
Absolute Maximum Ratings(Note 4)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 5)
−0.5V to VCC + 0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
)
DC VCC or Ground Current per
Supply Pin (ICC or Ground)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.7
2.0
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x VCC
0.7
V
V
0.8
VOH
I
I
I
I
OH = −100 µA
OH = −2 mA
OH = −4 mA
OH = −6 mA
1.65 - 3.6 VCC - 0.2
1.65
2.3
1.2
1.9
1.7
2.4
2
2.3
3.0
I
I
I
I
I
I
OH = −8 mA
OH = −12 mA
OL = 100 µA
OL = 2 mA
2.7
3.0
2
VOL
LOW Level Output Voltage
1.65 - 3.6
1.65
2.3
0.2
0.45
0.4
OL = 4 mA
OL = 6 mA
2.3
0.55
0.55
0.6
V
3.0
I
I
OL = 8 mA
2.7
OL = 12 mA
3
0.8
II
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
3.6
±5.0
±10
40
µA
µA
µA
µA
IOZ
ICC
∆ICC
3.6
VI = VCC or GND, IO = 0
IH = VCC − 0.6V
3.6
V
3 - 3.6
750
3
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AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
C
L = 50 pF
C
L = 30 pF
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
V
CC = 2.7V
V
CC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min
Max
Min
Max
Min
Max
Min
Max
fCLOCK
tW
Clock Frequency
Pulse Width LE High
CLK High or Low
Setup Time Data Before CLK ↑
Data Before CLK ↓ CLK High
150
150
150
100
MHz
ns
3.3
3.3
1.7
1.5
1.0
0.7
3.3
3.3
2.1
1.6
1.1
0.6
3.3
3.3
2.2
1.9
1.3
0.6
4.0
4.0
2.5
tS
ns
CLK Low
tH
Hold Time
Data After CLK ↑
Data After LE ↓
1.0
CLK High
or Low
ns
MHz
ns
1.4
1.7
1.4
fMAX
Maximum Clock Frequency
150
1.0
1.3
1.4
1.1
1.3
150
150
1.0
1.3
1.4
1.4
1.0
100
1.5
1.5
2.0
1.5
1.5
t
PHL, tPLH Propagation I to O
Delay LE to O
CLK to O
PZL, tPZH Output Enable Time
4.2
5.1
5.4
5.5
4.5
5.0
5.8
6.1
6.5
4.9
5.0
5.9
6.3
6.3
4.9
9.8
9.8
9.2
9.8
7.9
t
ns
ns
tPLZ, tPHZ Output Disable Time
AC Electrical Characteristics Over Load (Note 7)
RL = 500Ω, VCC = 3.3V ± 0.15V
T
A = −0°C to +85°C
T
A = −0°C to +65°C
L = 50 pF
Symbol
Parameter
Units
CL = 0 pF
C
Min
0.9
1.4
Max
2.0
Min
1.0
1.9
Max
4.0
tPHL, tPLH
tPHL, tPLH
Propagation Delay Bus to Bus
Propagation Delay Clock to Bus
ns
ns
2.9
5.0
Note 7: Characterized only.
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
Input Capacitance
Control
Data
VI = 0V or VCC
VI = 0V or VCC
VI = 0V, or VCC
3.3
3.3
3.3
3.3
2.5
3.3
2.5
3.5
5
pF
pF
COUT
CPD
Output Capacitance
7
Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 0 pF
40
35
14
125
pF
Outputs Disabled f = 10 MHz, CL = 0 pF
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4
I
- V
Characteristics
OUT
OUT
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Drive
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
5
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AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 3. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
1.8 ± 0.15V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
V
OL + 0.15V
V
OL + 0.15V
OH − 0.15V
VCC*2
Vy
V
OH − 0.3V
V
OH − 0.3V
V
OH − 0.15V
V
VL
6V
6V
VCC*2
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
tr = tf ≤ 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
tr = tf ≤ 2.0ns, 10% to 90%
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6
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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